665 results about "Transmission gate" patented technology

To provide an image sensor in which the conversion gain (CG) is improved, the arrangement efficiency and size of pixel transistors are increased, and a metal wiring layer is reduced.SOLUTION: An image sensor of the present invention includes a pixel including two photodiodes (PDs) disposed on both sides in a first direction, a deep trench isolation (DTI) structure including an internal DTI structure that separates the two PDs in the pixel from each other and extends in a second direction that is orthogonal to the first direction and an external DTI structure that separates the pixels from each other and extends in the first direction or the second direction, a floating diffusion (FD) region that is disposed between a central part of the external DTI structure extending in the first direction and an edge of the internal DTI structure, and a transmission gate (TG) disposed adjacent to the FD region and disposed at least one by one in the PD. The two PDs in the pixel share the FD region.SELECTED DRAWING: Figure 2

A voltage mode weak-PUF circuit with rich challenge-response pairs comprises four decoders, two PUF arrays, a sequential control circuit and a voltage comparator. One-to-two PUF arrays are used to replace existing one-to-one PUF arrays to increase the number of challenge-response pairs by 2N times, from 2N realized by the one-to-one PUF arrays to 2N×2N, wherein N=a+b. Each PUF cell comprises m*n PUF cells and n transmission gates, and adopts a simple common-source amplifier structure formed by a first PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein any one PUF cell in one PUF array can be compared with any one PUF cell in the other PUF array to generate an output response. The number of output responses is 2N, so the proportion of the PUF cells for generating one challenge-response pair is 2N / 2N=1 / 2N, and the reuse rate of the same PUF cell is merely 1 / 2N.

A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.

Sensing circuitry for an implantable stimulator device is disclosed. The sensing circuitry includes a downselector with switching networks used to couple selected electrode nodes and / or DC voltages to one or more sense amps. The switching networks comprise high-voltage devices that are controlled in accordance with a high-voltage power supply voltage VH. VH may be generated by a boost circuit, and may be set to the higher of a boosted voltage and a compliance voltage that powers the stimulation circuitry. The switching networks include three switches, some of which may comprise transfer gates. The downselector can be controlled to couple one or more electrodes nodes to a particular sense amp during sensing durations. The downselector can also be controlled during stimulation durations to couple one or more electrodes nodes together, thus supplementing operation of the stimulation circuitry.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

The invention relates to the technical field of integrated circuit design, and discloses a PAD circuit for a chip, the chip and electronic equipment, in the PAD circuit, a bleeder transistor is connected with a target PAD in the chip, the input end of a first transmission gate is connected with an analog signal end in the chip, the output end of the first transmission gate is connected with the target PAD, and the output end of the first transmission gate is connected with the analog signal end of the chip. The input end of the first transmission gate is connected with one analog signal end in the chip, the input end of the second transmission gate is connected with the other analog signal end in the chip, the output end of the second transmission gate is connected with a target PAD, the input end of the transmission gate control module is connected with the control signal end in the chip, and the two output ends of the transmission gate control module are connected with the control end of the first transmission gate and the control end of the second transmission gate respectively. And the first control module is configured to output a first control signal and a second control signal to the first transmission gate and the second transmission gate respectively based on an original control signal output by a control signal end. The PAD circuit helps to reduce the design difficulty of an integrated circuit in a chip.

The invention discloses a bit line voltage transmission circuit, which is characterized in that grid voltages of a first NMOS (N-channel Metal Oxide Semiconductor) tube and a PMOS (P-channel Metal Oxide Semiconductor) tube of a transmission gate between an IO (Input / Output) node and a bit line are respectively connected with a first control signal and a second control signal, and a pad electrode of the first PMOS tube is connected with a third control signal. When the first to third control signals are power supply voltage, first negative voltage and first positive voltage, the transmission gate is switched on. The first positive voltage is greater than or equal to the IO voltage and less than the power supply voltage, and is provided by the positive voltage signal generation circuit. The positive voltage signal generating circuit comprises a second NMOS tube, a third NMOS tube and a second PMOS tube. The grid electrode of the second NMOS tube and the drain electrode of the third NMOS tube are connected to a first node. The source electrode of the second NMOS tube and the grid electrode of the third NMOS tube are connected to a second node, and the second node serves as the output end of the first positive voltage. The source electrode of the third NMOS tube is connected with the source electrode of the second PMOS tube, and the drain electrode of the second PMOS tube is grounded. A first pull-up circuit is formed between the first node and the power supply voltage. The first pull-up circuit and the second PMOS tube are both controlled by a first enable signal.

An integrated circuit providing hardware security. The integrated circuit comprising a wire grid, wherein the wire grid comprises: (i) a wire grid spanning two metal layers comprising horizontal wires and vertical wires, (ii) a switch at each intersection of the horizontal wires and the vertical wires, wherein each switch comprises a transmission gate, (iii) one or more loop areas, wherein, for each intersection, the transmission gate is programmable to control connectivity at the intersection forming the one or more loop areas, and (iv) one or more amplifiers configured with the loop areas to provide one or more functions including (a) detecting trojans, (b) defending against fault injections by partially canceling injected magnetic fields with induced currents, (c) cancel fault injections by canceling injected magnetic fields, or (d) masking side-channel leakage by generate noising magnetic fields.

The invention relates to the technical field of integrated circuit design, in particular to a latch circuit capable of effectively self-recovering three-node data flipping and a chip. The circuit comprises a pull-up tube part, a pull-down tube part, a signal inverting part, a clock control inverting part, a transmission tube part and a transmission gate part. According to the latch circuit capable of effectively self-recovering three-node data flipping provided by the invention, the eight storage nodes S1 to S8 are correspondingly reinforced by adopting a means of combining polarity reinforcement and source isolation reinforcement, and are matched with the signal inverting part, the clock control inverting part, the transmission tube part and the transmission gate part for use, so that the circuit has complete SNU, DNU and TNU self-recovery capability, and the reliability of the circuit is improved. And the power consumption is low. According to the invention, the problem that the existing circuit cannot reduce the power consumption under the condition of resisting SNU, DNU and TNU at the same time is solved.

This invention relates to the field of semiconductor packaging technology, and more particularly to a fan-out board-level packaging bonding machine, comprising a support and a cavity. The cavity is fixed inside the support, and a vacuum transfer gate is provided at the front end of the cavity. A pressure applying mechanism is mounted on the top of the support and extends into the cavity. An upper bonding platform is mounted on the bottom of the pressure applying mechanism. A lower bonding platform is provided at the bottom of the cavity. An alignment mechanism and a receiving mechanism are mounted inside the cavity. This invention, through the structural design of the receiving mechanism, alignment mechanism, pressure applying mechanism, and top PIN mechanism, achieves product loading and unloading, high-precision alignment, and bonding. Furthermore, it features high flatness of each bonding layer, high parallelism between bonding surfaces, high uniformity of force acting on the product, and high uniformity of platform temperature. It also allows for controlled temperature rise and fall, enabling the board-level packaging to accommodate more chips, improving production efficiency and reducing costs.

A disclosed flip-flop includes primary and secondary sections connected to switchable and continuous power supplies, respectively. The primary section includes logic outputting first control signals, a primary latch controlled by the first control signals, and a data output device connected to an output terminal of the primary latch. The secondary section includes logic outputting second control signals and a secondary latch. A first transmission gate controlled by the second control signals is connected between the output terminal of the primary latch and an input terminal of the secondary latch. A second transmission gate controlled by the first and second control signals is connected between output and input terminals of the secondary latch. In a normal mode, both sections receive power and the first transmission gate is conductive. In a retention mode, the primary section is powered down, the first transmission gate is non-conductive and the second transmission gate is conductive.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The invention provides an SOT-MRAM memory calculation unit, array, system and method supporting exclusive-or operation, which support data writing and reading and exclusive-or operation and complete common exclusive-or operation in a memory to reduce data transmission so as to relieve the storage wall problem. The SOT-MRAM storage and calculation unit provided by the invention comprises a first NMOS (N-channel Metal Oxide Semiconductor) tube, a first transmission gate and a magnetic tunnel junction SOT-MTJ, the SOT-MRAM storage and calculation array disclosed by the invention comprises four SOT-MRAM storage and calculation units which are arranged in a 2 * 2 manner; the SOT-MRAM storage and calculation system disclosed by the invention comprises an SOT-MRAM storage and calculation array, two induction circuit modules and an XOR operation circuit module, the SOT-MRAM storage and calculation method comprises the following steps of data writing operation, data reading operation and XOR operation.

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. Comprising an oscillator module which comprises a feedback loop and a current detection circuit; the hiccup module is used for gating and outputting an input signal by a data selector according to the level of the input PWM logic control signal so as to control the on-off of a transmission gate, establishing a charging and discharging process and providing a delay starting function for the oscillator module; and the jittering frequency module outputs current sources Iref0 of different sizes by performing combined gating on a current source I'ref and current sources I1-I4, outputs four paths of current sources Iref1-Iref4 of different sizes through a current mirror array mirror image, and provides charging and discharging current for the oscillator module and the hiccup module. By dynamically adjusting the PWM frequency, the switching frequency is matched with the load requirement, the invalid switching frequency is reduced, and the power consumption is greatly reduced.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first trench in a substrate, disposing a first gate electrode in the first trench, and disposing a dummy gate electrode on the first gate electrode in the first trench. The method also includes removing the dummy gate electrode from the first gate electrode and forming a first doped region in the first gate electrode.

A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal.

Circuits and methods for defining functionality of swappable pins are provided. A power-on-reset (POR) circuit detects that a supply voltage is above a POR threshold during start-up or a reset operation. Transmission gate circuits monitor inputs from a first pin and the second pin and deactivate once the POR circuit detects that the supply voltage is above the POR threshold. A latch circuit receives outputs of the transmission gate circuits as inputs. Once the supply voltage is above the POR threshold, the latch circuit generates a first output corresponding to the first pin, and a second output corresponding to the second pin, where the first pin is defined as a I / O pin and the second pin is defined as a capacitance pin or vice versa based on the first output and the second output.

A dynamic flip-flop circuit with a feedback loop includes a input tristate circuit configured to receive a data signal and a clock signal to output a tristate output data signal. The dynamic flip-flop circuit also includes a feedforward circuit configured to receive the tristate output data signal as input to output a feedforward output data signal. The dynamic flip-flop circuit also includes a feedback loop circuit configured to connect the output of the feedforward circuit and the output of the input tristate circuit. The feedback loop circuit includes a transmission gate circuit that is partially on.

An integrated circuit structure is provided. The integrated circuit structure includes at least one static random-access memory (SRAM) cell. The SRAM cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. The first active region and the second active region follow a first routing direction. The first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. The first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. Each of the at least one SRAM cell has a Y-pitch along the first routing direction. The Y-pitch is 4X contacted poly pitch.

Embodiments disclosed herein relate to device testing using scan chains including various flip-flop devices in a multi-bit flip-flop configuration. A circuit device included herein includes a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit is coupled to receive a clock signal and an input, and the second flip-flop circuit is coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub-circuit, a first latch sub-circuit, a first latch tristate, a second latch sub-circuit, and a first output inverter. The second latch sub-circuit includes a first transmission gate, a first inverter, and a second inverter. The second flip-flop sub-circuit includes a second transmission gate, a first clock tristate, a third latch sub-circuit, a second latch tristate, a fourth latch sub-circuit, and a second output inverter. The fourth latch sub-circuit includes a third transmission gate, a third inverter, and a fourth inverter.

To provide a semiconductor device such as an image sensor in which an off voltage is sequentially applied to dual transfer gates so as to block a backflow phenomenon, in which electrons return to a photoelectric converter from a floating diffusion region.SOLUTION: An image sensor 503 includes a plurality of unit pixels. Each of the unit pixels UP includes: a pair of a first transfer gate TG1 and a second transfer gate TG2; a photoelectric converter PD; and a floating diffusion region positioned at a distance from the photoelectric converter. The first transfer gate and the second transfer gate are disposed asymmetrically with respect to the photoelectric converter and the floating diffusion region.SELECTED DRAWING: Figure 5

The application relates to the technical field of latches, and discloses a low-overhead four-point flip-flop reinforced latch, which comprises a transmission gate assembly and an inverter assembly connected with the transmission gate assembly, and a node assembly is formed between the transmission gate assembly and the inverter assembly; the transmission gate assembly comprises transmission gates TG1-TG12; the inverter assembly comprises inverters DI1-DI24; and the node assembly comprises nodes N1-N24 located on the inverter assembly. The application has higher reliability, lower power consumption and greatly reduced delay, and can be widely applied to the fields of aerospace and medical treatment and the like which have high latch reliability requirements.

A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source / drain feature of a pass-gate transistor of one of the first plurality of the memory cells.

A back side illumination (BSI) image sensor includes an epitaxial substrate, a deep trench isolation (DTI) structure from one surface to the other surface of the epitaxial substrate, a buried oxide layer on the epitaxial substrate, an epitaxial layer, a well region, a floating diffusion (FD) region, a shallow trench isolation (STI) structure, and vertical transfer gates (VTGs). The buried oxide layer has openings exposing the epitaxial substrate, and the epitaxial layer is formed on the epitaxial substrate and covers the buried oxide layer. The well region is in the epitaxial layer and the epitaxial substrate. The FD region is in the well region above the buried oxide layer, and a width of the buried oxide layer is larger than that of the FD region. The STI structure is in the epitaxial layer. The VTGs are in the epitaxial layer and through the openings of the buried oxide layer.

An integrated circuit includes a first inverter and a first transmission gate constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A latch is formed with the first inverter and the first clocked inverter. The first transmission gate is connected to between an output of the first inverter. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.

A switching circuit includes a transmission gate, two base control sub-circuits each including a first transistor and a second transistor, a third transistor, and a fourth transistor. The transmission gate includes two I / O terminals, two gate control terminals, and two base control terminals, and is configured to conduct or not conduct the two I / O terminals according to the voltage of the two gate control terminals. The two base voltage control sub-circuits, the third transistor and the fourth transistor forms a double balance circuit structure and is electrically connected to the transmission gate. The double balance circuit changes the voltage of the base control terminals according to the voltage of the I / O terminals of the transmission gate.

The present invention discloses an 8T2R non-volatile SRAM unit circuit, including a non-volatile data storage circuit composed of two resistive random access memories RRAM, a resistive random access memory UR on the top and a resistive random access memory BR on the bottom; a transmission gate circuit composed of an N-type MOSFET and a P-type MOSFET, the N-type MOSFET is recorded as NT, and the P-type MOSFET is recorded as PT; two P-type MOSFETs and two N-type MOSFETs constitute two inverters, and the two inverters are connected end to end, the two P-type MOSFETs are respectively recorded as a left pull-up transistor LUT and a right pull-up transistor RUT, the two N-type MOSFETs are respectively recorded as a left pull-down transistor LDT and a right pull-down transistor RDT, and the left access transistor LAT and the right access transistor RAT constitute a storage unit of a 6T-SRAM. The circuit adds a non-volatile unit RRAM on the basis of the read, write and hold capabilities of the SRAM, so that the SRAM has the ability to not lose power-off data and to recover power-on data.

The invention discloses a photosensitive pixel element containing a P-type thin film transistor transmission gate and an image sensor. The photosensitive pixel element comprises a substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the single-layer or double-layer P-type thin film semiconductor layer is positioned above the dielectric layer and is in ohmic contact with the signal reading electrode through the opening part; the photoelectric conversion layer is located above the P-type thin film semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.

A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.