399 results about "Transmission gate" patented technology

Sensing circuitry for an implantable stimulator device is disclosed. The sensing circuitry includes a downselector with switching networks used to couple selected electrode nodes and / or DC voltages to one or more sense amps. The switching networks comprise high-voltage devices that are controlled in accordance with a high-voltage power supply voltage VH. VH may be generated by a boost circuit, and may be set to the higher of a boosted voltage and a compliance voltage that powers the stimulation circuitry. The switching networks include three switches, some of which may comprise transfer gates. The downselector can be controlled to couple one or more electrodes nodes to a particular sense amp during sensing durations. The downselector can also be controlled during stimulation durations to couple one or more electrodes nodes together, thus supplementing operation of the stimulation circuitry.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

The invention relates to the technical field of integrated circuit design, in particular to a latch circuit capable of effectively self-recovering three-node data flipping and a chip. The circuit comprises a pull-up tube part, a pull-down tube part, a signal inverting part, a clock control inverting part, a transmission tube part and a transmission gate part. According to the latch circuit capable of effectively self-recovering three-node data flipping provided by the invention, the eight storage nodes S1 to S8 are correspondingly reinforced by adopting a means of combining polarity reinforcement and source isolation reinforcement, and are matched with the signal inverting part, the clock control inverting part, the transmission tube part and the transmission gate part for use, so that the circuit has complete SNU, DNU and TNU self-recovery capability, and the reliability of the circuit is improved. And the power consumption is low. According to the invention, the problem that the existing circuit cannot reduce the power consumption under the condition of resisting SNU, DNU and TNU at the same time is solved.

This invention relates to the field of semiconductor packaging technology, and more particularly to a fan-out board-level packaging bonding machine, comprising a support and a cavity. The cavity is fixed inside the support, and a vacuum transfer gate is provided at the front end of the cavity. A pressure applying mechanism is mounted on the top of the support and extends into the cavity. An upper bonding platform is mounted on the bottom of the pressure applying mechanism. A lower bonding platform is provided at the bottom of the cavity. An alignment mechanism and a receiving mechanism are mounted inside the cavity. This invention, through the structural design of the receiving mechanism, alignment mechanism, pressure applying mechanism, and top PIN mechanism, achieves product loading and unloading, high-precision alignment, and bonding. Furthermore, it features high flatness of each bonding layer, high parallelism between bonding surfaces, high uniformity of force acting on the product, and high uniformity of platform temperature. It also allows for controlled temperature rise and fall, enabling the board-level packaging to accommodate more chips, improving production efficiency and reducing costs.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. Comprising an oscillator module which comprises a feedback loop and a current detection circuit; the hiccup module is used for gating and outputting an input signal by a data selector according to the level of the input PWM logic control signal so as to control the on-off of a transmission gate, establishing a charging and discharging process and providing a delay starting function for the oscillator module; and the jittering frequency module outputs current sources Iref0 of different sizes by performing combined gating on a current source I'ref and current sources I1-I4, outputs four paths of current sources Iref1-Iref4 of different sizes through a current mirror array mirror image, and provides charging and discharging current for the oscillator module and the hiccup module. By dynamically adjusting the PWM frequency, the switching frequency is matched with the load requirement, the invalid switching frequency is reduced, and the power consumption is greatly reduced.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first trench in a substrate, disposing a first gate electrode in the first trench, and disposing a dummy gate electrode on the first gate electrode in the first trench. The method also includes removing the dummy gate electrode from the first gate electrode and forming a first doped region in the first gate electrode.

A dynamic flip-flop circuit with a feedback loop includes a input tristate circuit configured to receive a data signal and a clock signal to output a tristate output data signal. The dynamic flip-flop circuit also includes a feedforward circuit configured to receive the tristate output data signal as input to output a feedforward output data signal. The dynamic flip-flop circuit also includes a feedback loop circuit configured to connect the output of the feedforward circuit and the output of the input tristate circuit. The feedback loop circuit includes a transmission gate circuit that is partially on.

An integrated circuit structure is provided. The integrated circuit structure includes at least one static random-access memory (SRAM) cell. The SRAM cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. The first active region and the second active region follow a first routing direction. The first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. The first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. Each of the at least one SRAM cell has a Y-pitch along the first routing direction. The Y-pitch is 4X contacted poly pitch.

Embodiments disclosed herein relate to device testing using scan chains including various flip-flop devices in a multi-bit flip-flop configuration. A circuit device included herein includes a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit is coupled to receive a clock signal and an input, and the second flip-flop circuit is coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub-circuit, a first latch sub-circuit, a first latch tristate, a second latch sub-circuit, and a first output inverter. The second latch sub-circuit includes a first transmission gate, a first inverter, and a second inverter. The second flip-flop sub-circuit includes a second transmission gate, a first clock tristate, a third latch sub-circuit, a second latch tristate, a fourth latch sub-circuit, and a second output inverter. The fourth latch sub-circuit includes a third transmission gate, a third inverter, and a fourth inverter.

The application relates to the technical field of latches, and discloses a low-overhead four-point flip-flop reinforced latch, which comprises a transmission gate assembly and an inverter assembly connected with the transmission gate assembly, and a node assembly is formed between the transmission gate assembly and the inverter assembly; the transmission gate assembly comprises transmission gates TG1-TG12; the inverter assembly comprises inverters DI1-DI24; and the node assembly comprises nodes N1-N24 located on the inverter assembly. The application has higher reliability, lower power consumption and greatly reduced delay, and can be widely applied to the fields of aerospace and medical treatment and the like which have high latch reliability requirements.

A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source / drain feature of a pass-gate transistor of one of the first plurality of the memory cells.

A back side illumination (BSI) image sensor includes an epitaxial substrate, a deep trench isolation (DTI) structure from one surface to the other surface of the epitaxial substrate, a buried oxide layer on the epitaxial substrate, an epitaxial layer, a well region, a floating diffusion (FD) region, a shallow trench isolation (STI) structure, and vertical transfer gates (VTGs). The buried oxide layer has openings exposing the epitaxial substrate, and the epitaxial layer is formed on the epitaxial substrate and covers the buried oxide layer. The well region is in the epitaxial layer and the epitaxial substrate. The FD region is in the well region above the buried oxide layer, and a width of the buried oxide layer is larger than that of the FD region. The STI structure is in the epitaxial layer. The VTGs are in the epitaxial layer and through the openings of the buried oxide layer.

An integrated circuit includes a first inverter and a first transmission gate constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A latch is formed with the first inverter and the first clocked inverter. The first transmission gate is connected to between an output of the first inverter. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.

The invention discloses a photosensitive pixel element containing a P-type thin film transistor transmission gate and an image sensor. The photosensitive pixel element comprises a substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the single-layer or double-layer P-type thin film semiconductor layer is positioned above the dielectric layer and is in ohmic contact with the signal reading electrode through the opening part; the photoelectric conversion layer is located above the P-type thin film semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.

A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.

A memory circuit includes a memory cell, a bit line, a bit line bar, a pass-gate transistor coupled to the memory cell and the bit line, a sense amplifier coupled to the bit line, the bit line bar and the pass-gate transistor, and a pre-charge circuit coupled to the first node, and configured to pre-charge the first node to a pre-charge voltage in response to a pre-charge control signal. The sense amplifier includes a first path between the bit line and the bit line bar. The first path includes a first isolation transistor configured to receive an isolation control signal, and being coupled between the bit line and a first node, and a first inverter configured to receive a sense amplifier enable signal, and being coupled between a second node and a third node.

The application discloses a kind of low conduction resistance flatness analog switch structure of circuit design technical field, including CMOS transmission gate circuit and gate voltage adjusting circuit, CMOS transmission gate circuit includes transmission gate and auxiliary circuit, transmission gate and auxiliary circuit are electrically connected, CMOS transmission gate circuit is used for the signal transmission of main path;Gate voltage adjusting circuit is connected between the gate of PMOS pipe of CMOS transmission gate circuit and the gate of NMOS pipe.The whole input voltage range is handled by gate voltage adjusting circuit in the application, according to input voltage variation, output different slope gate control voltage, to reduce the conduction resistance variation of CMOS transmission gate, to reduce the purpose of conduction resistance flatness.

The present application discloses an LDO circuit with a switchable power supply terminal, which includes an error amplifier EA. The error amplifier EA is connected to a chip output module and a chip input module through transmission gates TG1 and TG2 respectively. The output module and the input module have the same structure, and both include a control unit, a switching unit, and a voltage unit. In the same module: the control unit controls the switch of the switching unit under the action of a control signal. When the switching unit is turned off, the corresponding transmission gate of this module is turned on, enabling the error amplifier EA to communicate with this module, and the output voltage generated by the voltage unit of this module serves as the output of the LDO. When the switching unit is turned on, the corresponding transmission gate of this module is turned off, disconnecting the error amplifier EA from this module, and the voltage unit of this module is turned off. The present invention can achieve the switching of the LDO power supply terminal with only one error amplifier, effectively saving chip area.

A cryogenic quasi-static embedded DRAM (CQS-eDRAM) for energy-efficient computing-in-memory (CIM) is provided. A CQS-eDRAM array includes four-transistor transmission gate gain-cell (4T TGGC) memory cells, and each of the 4T TGGC memory cells includes a P-channel metal oxide semiconductor (PMOS) transistor P1 and three N-channel metal oxide semiconductor (NMOS) transistors N1, N2, and N3. A cryogenic 4T TGGC topology is provided. A quasi-static storage operation is achieved at a cryogenic temperature by fully utilizing advantages of the cryogenic 4T TGGC topology in reducing leakage and a line transmission delay. In addition, a cryogenic write bit line (WBL) bias technology and a dedicated readout circuit are adopted to optimize power consumptions of read and write operations.

This application relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in the field of integrated circuit design technology. The latch includes: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module using two four-input inverting CE units and inversion operation to generate voltages for sensitive nodes A and B from signals from N1 to N7 and Q. This latch has good TNU (Terror-Noise Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

The application discloses a weak PUF circuit with rich excitation response based on MOS tube leakage current, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, a first PUF array, a second PUF array, two transmission gate arrays and one shared header, each PUF array comprises two column units, q is an integer greater than 1, each column unit comprises two NMOS units, p is an integer greater than 1, each NMOS unit comprises an NMOS tube, under the decoding action of the first decoder, the third decoder and the second decoder, the fourth decoder on the excitation signal, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array to generate a final output response, and the advantage is that the PUF entropy source utilization rate is improved by 2 times while the hardware overhead is kept small, and the number of CRPs is significantly improved. q p p+q ​​​

The invention relates to a fast latch based on logic isolation. The fast latch comprises a transmission gate module which adopts a plurality of transmission gates controlled by clock signals to transmit input signals to corresponding generation nodes. The generation module is used for generating a feedback node signal by adopting a plurality of mutually connected phase inverters; the feedback module is used for receiving feedback node signals and feeding back each feedback node signal to a corresponding generation node by adopting a cross feedback loop, and in a normal working state, when a clock signal is at a high level, the fast latch works in a transparent mode; when the clock CLK is at a low level, enabling the fast latch to work in a holding mode; and when a single node or double nodes are overturned, the quick latch is self-repaired. According to the latch, logic isolation is realized through a cross feedback loop, and soft errors can be repaired and correct data can be stored even if a radiation event occurs; the fast latch can provide complete DNU elasticity, and has a faster speed and a smaller area.

An SRAM device and its formation method are disclosed. The formation method includes: providing a substrate comprising a first type of device region and a second type of device region; the first type of SRAM device having a maximum channel width; both the first and second type of device regions comprising a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; forming a stacked structure on the substrate, comprising a first sacrificial layer and a channel layer; the width of each stacked structure in the second type of device region being equal to a preset width of the corresponding transistor region in the first type of device region; performing a channel width adjustment process; in the second type of device region, removing a portion of the channel layer width from any one or two of the transistor regions (transmission gate transistor region, pull-down transistor region, and pull-up transistor region); after removing the portion of the channel layer width, removing the first sacrificial layer; and after removing the first sacrificial layer, forming a gate structure spanning the channel layer. This invention uses the same design layout to form the stacked structure, saving design costs.

A boron (B) layer may be formed as a passivation layer in a recess in which a vertical transfer gate is to be formed. The recess may then be filled with a gate electrode of the vertical transfer gate over the passivation layer (and / or one or more intervening layers) to form the vertical transfer gate. The passivation layer may be formed in the recess by epitaxial growth. The use of epitaxy to grow the passivation layer enables precise control over the profile, uniformity, and boron concentration in the passivation layer. Moreover, the use of epitaxy to grow the passivation layer may reduce the diffusion length of the passivation layer into the substrate of the pixel sensor, which provides increased area in the pixel sensor for the photodiode.

This application discloses a differential transmitter circuit, chip, and electronic device. The differential transmitter circuit includes: a single-slip differential drive enhancement circuit, including a single-ended digital input terminal (IN) and a first differential output terminal (IN_P, IN_N), used to convert the input single-ended digital signal into a pair of differential signals; a differential drive circuit, connected to the first differential output terminal (IN_P, IN_N), including a second differential output terminal (OUT_P, OUT_N), used to convert the differential signals into differential output voltages; wherein, the single-slip differential drive enhancement circuit includes a transmission gate (Tran) and an inverter, used to generate the differential signals with a phase difference of 180° and timing matching. The embodiments of this application aim to solve the technical problems of slow response speed, poor common-mode stability, high power consumption, and insufficient noise suppression capability in the prior art when transmitter circuits are used in LVDS interface applications.

The application relates to a line driver impedance calibration overvoltage protection circuit and method, which is applied to an Ethernet and comprises a first impedance calibration circuit and an overvoltage protection circuit. The first impedance calibration circuit comprises a plurality of first transmission gates, two ends of each first transmission gate are connected with a first resistor and a second resistor respectively, and the first transmission gate can be controlled to be turned on or turned off to adjust the impedance between the line driver and the first connection end to a preset value. The overvoltage protection circuit is used for detecting the amplitude of the opposite end signal received by the hybrid circuit, comparing the amplitude of the opposite end signal with a predetermined threshold value, outputting a comparison signal, and controlling the amplitude of the local end signal sent by the line driver according to the comparison signal. The application can realize impedance calibration, the transmission gate works at the intermediate voltage, the voltage interval range is smaller, the overvoltage of the transmission gate is protected, the tolerance of the reliability of the Ethernet is better, the amplitude of the local end is limited, and then the overvoltage protection of the impedance calibration is realized.

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a memory cell on the substrate, wherein the memory cell comprises a first transistor and a second transistor which are used as pull-down transistors, a third transistor and a fourth transistor which are used as pull-up transistors, and a fifth transistor and a sixth transistor which are used as transmission gate transistors; wherein the first transistor and the third transistor are stacked, the top of a first grid electrode of the first transistor is connected with the bottom of a third grid electrode of the third transistor, and the first grid electrode and a fifth grid electrode of the fifth transistor share a channel layer; the second transistor and the fourth transistor are stacked, the top of a second grid electrode of the second transistor is connected with the bottom of a fourth grid electrode of the fourth transistor, and the second grid electrode of the second transistor and a sixth grid electrode of the sixth transistor share a channel layer. According to the technical scheme, the integration level of the semiconductor structure can be improved.

The present disclosure provides a semiconductor structure comprising a substrate having a front side and a back side; an SRAM circuit having SRAM bit cells formed on a front side of the substrate, where each SRAM bit cell includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each SRAM bit cell is connected to the WBL, the WBLB, the RBL, the Vdd, and the Vss; a first subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the front side of the substrate to a first of the SRAM bit cells; a second subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the backside of the substrate to the first SRAM bit cell.