290 results about "Transmission gate" patented technology

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

This invention relates to the field of semiconductor packaging technology, and more particularly to a fan-out board-level packaging bonding machine, comprising a support and a cavity. The cavity is fixed inside the support, and a vacuum transfer gate is provided at the front end of the cavity. A pressure applying mechanism is mounted on the top of the support and extends into the cavity. An upper bonding platform is mounted on the bottom of the pressure applying mechanism. A lower bonding platform is provided at the bottom of the cavity. An alignment mechanism and a receiving mechanism are mounted inside the cavity. This invention, through the structural design of the receiving mechanism, alignment mechanism, pressure applying mechanism, and top PIN mechanism, achieves product loading and unloading, high-precision alignment, and bonding. Furthermore, it features high flatness of each bonding layer, high parallelism between bonding surfaces, high uniformity of force acting on the product, and high uniformity of platform temperature. It also allows for controlled temperature rise and fall, enabling the board-level packaging to accommodate more chips, improving production efficiency and reducing costs.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. Comprising an oscillator module which comprises a feedback loop and a current detection circuit; the hiccup module is used for gating and outputting an input signal by a data selector according to the level of the input PWM logic control signal so as to control the on-off of a transmission gate, establishing a charging and discharging process and providing a delay starting function for the oscillator module; and the jittering frequency module outputs current sources Iref0 of different sizes by performing combined gating on a current source I'ref and current sources I1-I4, outputs four paths of current sources Iref1-Iref4 of different sizes through a current mirror array mirror image, and provides charging and discharging current for the oscillator module and the hiccup module. By dynamically adjusting the PWM frequency, the switching frequency is matched with the load requirement, the invalid switching frequency is reduced, and the power consumption is greatly reduced.

The application relates to the technical field of latches, and discloses a low-overhead four-point flip-flop reinforced latch, which comprises a transmission gate assembly and an inverter assembly connected with the transmission gate assembly, and a node assembly is formed between the transmission gate assembly and the inverter assembly; the transmission gate assembly comprises transmission gates TG1-TG12; the inverter assembly comprises inverters DI1-DI24; and the node assembly comprises nodes N1-N24 located on the inverter assembly. The application has higher reliability, lower power consumption and greatly reduced delay, and can be widely applied to the fields of aerospace and medical treatment and the like which have high latch reliability requirements.

A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source / drain feature of a pass-gate transistor of one of the first plurality of the memory cells.

The invention discloses a photosensitive pixel element containing a P-type thin film transistor transmission gate and an image sensor. The photosensitive pixel element comprises a substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the single-layer or double-layer P-type thin film semiconductor layer is positioned above the dielectric layer and is in ohmic contact with the signal reading electrode through the opening part; the photoelectric conversion layer is located above the P-type thin film semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.

A memory circuit includes a memory cell, a bit line, a bit line bar, a pass-gate transistor coupled to the memory cell and the bit line, a sense amplifier coupled to the bit line, the bit line bar and the pass-gate transistor, and a pre-charge circuit coupled to the first node, and configured to pre-charge the first node to a pre-charge voltage in response to a pre-charge control signal. The sense amplifier includes a first path between the bit line and the bit line bar. The first path includes a first isolation transistor configured to receive an isolation control signal, and being coupled between the bit line and a first node, and a first inverter configured to receive a sense amplifier enable signal, and being coupled between a second node and a third node.

The application discloses a kind of low conduction resistance flatness analog switch structure of circuit design technical field, including CMOS transmission gate circuit and gate voltage adjusting circuit, CMOS transmission gate circuit includes transmission gate and auxiliary circuit, transmission gate and auxiliary circuit are electrically connected, CMOS transmission gate circuit is used for the signal transmission of main path;Gate voltage adjusting circuit is connected between the gate of PMOS pipe of CMOS transmission gate circuit and the gate of NMOS pipe.The whole input voltage range is handled by gate voltage adjusting circuit in the application, according to input voltage variation, output different slope gate control voltage, to reduce the conduction resistance variation of CMOS transmission gate, to reduce the purpose of conduction resistance flatness.

This application relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in the field of integrated circuit design technology. The latch includes: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module using two four-input inverting CE units and inversion operation to generate voltages for sensitive nodes A and B from signals from N1 to N7 and Q. This latch has good TNU (Terror-Noise Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

The application discloses a weak PUF circuit with rich excitation response based on MOS tube leakage current, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, a first PUF array, a second PUF array, two transmission gate arrays and one shared header, each PUF array comprises two column units, q is an integer greater than 1, each column unit comprises two NMOS units, p is an integer greater than 1, each NMOS unit comprises an NMOS tube, under the decoding action of the first decoder, the third decoder and the second decoder, the fourth decoder on the excitation signal, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array to generate a final output response, and the advantage is that the PUF entropy source utilization rate is improved by 2 times while the hardware overhead is kept small, and the number of CRPs is significantly improved. q p p+q ​​​

An SRAM device and its formation method are disclosed. The formation method includes: providing a substrate comprising a first type of device region and a second type of device region; the first type of SRAM device having a maximum channel width; both the first and second type of device regions comprising a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; forming a stacked structure on the substrate, comprising a first sacrificial layer and a channel layer; the width of each stacked structure in the second type of device region being equal to a preset width of the corresponding transistor region in the first type of device region; performing a channel width adjustment process; in the second type of device region, removing a portion of the channel layer width from any one or two of the transistor regions (transmission gate transistor region, pull-down transistor region, and pull-up transistor region); after removing the portion of the channel layer width, removing the first sacrificial layer; and after removing the first sacrificial layer, forming a gate structure spanning the channel layer. This invention uses the same design layout to form the stacked structure, saving design costs.

A boron (B) layer may be formed as a passivation layer in a recess in which a vertical transfer gate is to be formed. The recess may then be filled with a gate electrode of the vertical transfer gate over the passivation layer (and / or one or more intervening layers) to form the vertical transfer gate. The passivation layer may be formed in the recess by epitaxial growth. The use of epitaxy to grow the passivation layer enables precise control over the profile, uniformity, and boron concentration in the passivation layer. Moreover, the use of epitaxy to grow the passivation layer may reduce the diffusion length of the passivation layer into the substrate of the pixel sensor, which provides increased area in the pixel sensor for the photodiode.

This application discloses a differential transmitter circuit, chip, and electronic device. The differential transmitter circuit includes: a single-slip differential drive enhancement circuit, including a single-ended digital input terminal (IN) and a first differential output terminal (IN_P, IN_N), used to convert the input single-ended digital signal into a pair of differential signals; a differential drive circuit, connected to the first differential output terminal (IN_P, IN_N), including a second differential output terminal (OUT_P, OUT_N), used to convert the differential signals into differential output voltages; wherein, the single-slip differential drive enhancement circuit includes a transmission gate (Tran) and an inverter, used to generate the differential signals with a phase difference of 180° and timing matching. The embodiments of this application aim to solve the technical problems of slow response speed, poor common-mode stability, high power consumption, and insufficient noise suppression capability in the prior art when transmitter circuits are used in LVDS interface applications.

The application relates to a line driver impedance calibration overvoltage protection circuit and method, which is applied to an Ethernet and comprises a first impedance calibration circuit and an overvoltage protection circuit. The first impedance calibration circuit comprises a plurality of first transmission gates, two ends of each first transmission gate are connected with a first resistor and a second resistor respectively, and the first transmission gate can be controlled to be turned on or turned off to adjust the impedance between the line driver and the first connection end to a preset value. The overvoltage protection circuit is used for detecting the amplitude of the opposite end signal received by the hybrid circuit, comparing the amplitude of the opposite end signal with a predetermined threshold value, outputting a comparison signal, and controlling the amplitude of the local end signal sent by the line driver according to the comparison signal. The application can realize impedance calibration, the transmission gate works at the intermediate voltage, the voltage interval range is smaller, the overvoltage of the transmission gate is protected, the tolerance of the reliability of the Ethernet is better, the amplitude of the local end is limited, and then the overvoltage protection of the impedance calibration is realized.

The present disclosure provides a semiconductor structure comprising a substrate having a front side and a back side; an SRAM circuit having SRAM bit cells formed on a front side of the substrate, where each SRAM bit cell includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each SRAM bit cell is connected to the WBL, the WBLB, the RBL, the Vdd, and the Vss; a first subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the front side of the substrate to a first of the SRAM bit cells; a second subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the backside of the substrate to the first SRAM bit cell.

Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor comprises a substrate which comprises a photodiode, a storage node and a floating diffusion region which are arranged in parallel, and the storage node is arranged between the photodiode and the floating diffusion region; the transmission tube grid electrode is arranged between the photodiode and the storage node; the reset tube grid electrode is arranged between the storage node and the floating diffusion region; the protection layer is arranged on the substrate and the grid electrode; the first dielectric layer is arranged on the protective layer; the metal shading structure is arranged in the first dielectric layer on the transmission tube grid electrode, part of the storage nodes and part of the reset tube grid electrode in a segmented manner; the second dielectric layer is arranged on the first dielectric layer and the metal shading structure; and the first metal layer is arranged on the second dielectric layer and is in negative pressure bias connection with the metal shading structure on the storage node. According to the invention, the dark current and parasitic light response of the storage node can be reduced, and the quality of the image sensor is improved.

The invention relates to a memory cell including a dual anti-fuse device, a memory structure, and a method of operation. A memory cell is disclosed that includes a dual anti-fuse device between a first pass-gate transistor and a second pass-gate transistor. A dual antifuse device includes first and second antifuses having a common terminal and also each having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between the first bit line and an additional terminal for the first pass-gate transistor. The second pass gate transistor is connected between the second bit line and an additional terminal of the second pass gate transistor. A common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a word line. A memory structure including an array of such memory cells and related methods of operation are also disclosed. Within the array, different word line and bit line bias conditions may be employed to reliably perform program or read operations for selected antifuses in selected cells.

The invention provides a high-voltage level shift circuit with high dVdt suppression capability, which is used for converting a signal in a low-voltage domain into a signal in a high-voltage domain and comprises an encyclopedia level shift module, a PMOS (P-channel Metal Oxide Semiconductor) coupling module, a noise current elimination module, a current compensation module, a transmission gate module and an RS (Reed-Solomon) latch module, the level shift module is used for transmitting signals from a low-voltage domain to a high-voltage domain, the PMOS coupling module is used for converting voltage signals transmitted by the level shift module into current signals, accelerating signal transmission and preventing common-mode signals from passing through, and the noise current elimination module is used for mirroring current, accelerating signal transmission and counteracting common-mode noise induction current. The current compensation module is used for compensating the current of a node, the transmission gate is used for transmitting a signal output by the noise elimination module to the RS latch, the RS latch module is used for recovering an edge narrow pulse signal into a square signal, and according to the scheme, the dV / dt noise suppression capability of the circuit is enhanced while low power consumption and low delay are achieved.

To provide an image sensor with improved electrical and optical characteristics. [Solution] The image sensor of the present invention comprises a semiconductor substrate, a pixel isolation structure disposed within the semiconductor substrate and defining first and second pixel regions, a transmission gate electrode provided to the first pixel region, a floating diffusion region provided to the first pixel region on one side of the transmission gate electrode, a pixel gate electrode provided to the second pixel region, a source / drain region provided to the second pixel region on one side of the pixel gate electrode, a connecting conductive pattern disposed on the first surface of the semiconductor substrate and connecting the floating diffusion region and the source / drain region, including an edge portion adjacent to the outer wall, and a blocking pattern disposed between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate.

The present invention belongs to the field of integrated circuit technology, specifically relating to a 9T1C storage-calculation circuit, a multiplication-accumulation circuit, an in-memory arithmetic circuit, and a chip. The 9T1C storage-calculation circuit has data read / write retention functions and multiplication operations. The 9T1C storage-calculation circuit is composed of six NMOS transistors N0 to N5, three PMOS transistors P0 to P2, and one capacitor C0. P0, N0, P1, and N1 in the circuit form a cross-coupling structure for latching data. N2 and N3 serve as transmission transistors, located on the left and right sides of the cross-coupling structure, respectively, as two storage node write paths. N4 and P2 form a transmission gate. N5 serves as a calculation control terminal, and C0 serves as a capacitor for transmitting voltage differences. The multiplication-accumulation arithmetic circuit includes an arithmetic array composed of 9T1C storage-calculation circuits arranged in columns, a word line group, a bit line group, an input signal line IL, an output signal line OL, a column switch S, and a quantization circuit. Furthermore, the in-memory arithmetic circuit is formed. Compared with existing solutions, the present invention improves the performance of the storage-calculation circuit in terms of power consumption, stability, accuracy, and computational efficiency.

The invention provides an 8T SRAM (Static Random Access Memory) unit, an 8T SRAM and a preparation method thereof, the 8T SRAM unit comprises a substrate, a pull-up transistor group, a pull-down transistor group and a transmission gate transistor group, the pull-up transistor group and the transmission gate transistor group are integrated on the front surface of the substrate, the pull-down transistor group is integrated on the back surface of the substrate, and the transmission gate transistor group is integrated on the back surface of the substrate. The first pull-down group comprises a first pull-down transistor and a second pull-down transistor which are arranged in parallel, and the second pull-down group comprises a third pull-down transistor and a fourth pull-down transistor which are arranged in parallel; the first pull-up transistor and the first pull-down group form a first phase inverter, the second pull-up transistor and the second pull-down group form a second phase inverter, and the first phase inverter and the second phase inverter are in cross coupling; the transmission gate transistor group comprises a first transmission gate transistor and a second transmission gate transistor, the first transmission gate transistor is connected with the first phase inverter, and the second transmission gate transistor is connected with the second phase inverter. According to the invention, the stability of the SRAM unit is improved.

Device for operating a passive infrared (PIR) detector with a first connection (IN) and a second connection (IP), the device comprising: - an electrical circuit arrangement (R G ), wherein the electrical circuit arrangement (R G ) forms a leakage resistance between the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR) to discharge the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR); wherein the electrical circuit arrangement (R G ) includes a switch-capacitor circuit with transfer gates and storage capacities; and the device is set up for this purpose: - the transfer gates of the electrical circuit arrangement (R G) to switch alternately with a first clock (φ1) and a second clock (Φ2), and to advance a charge quantity by one node with each half-clock using the storage capacities, whereby the first clock (φ1) and the second clock (Φ2) do not overlap and, apart from the non-overlap, the first clock (φ1) is the inverse of the second clock (Φ2); and - to switch off the first clock (φ1) and the second clock (Φ2) during a measurement phase, so that the device is in a measurement state and the charge flow through the electrical circuit arrangement (R G ) is prevented.

This invention discloses a frequency dithering control circuit, a control chip, and a switching power supply. The frequency dithering control circuit includes: a narrow pulse generation module, used to convert an input high-level enable signal into a low-level narrow pulse after the control chip is started; a current source charging and discharging module, used to charge a capacitor connected to a pin of the control chip when a low-level narrow pulse is received, and simultaneously output a first voltage signal based on the voltage signal detected at its detection terminal; and to discharge the capacitor when no low-level narrow pulse is received at its input terminal; a level shifting module, used to convert the first voltage signal into a second voltage signal, either the supply voltage or ground level, and then output it; and a frequency dithering switch module, used to control the conduction and cutoff of the transmission gate based on the second voltage signal, the narrow pulse, and the enable signal, thereby enabling and disabling the frequency dithering function of the control chip. This invention reduces the design difficulty for application engineers.

An apparatus includes a capacitor, a first plurality of transistors, a transmission gate, and a second plurality of transistors. The first plurality of transistors is coupled in series with each other via the capacitor. The first plurality of transistors are coupled between a first supply voltage terminal and a ground terminal. The transmission gate is coupled to a second supply voltage terminal. The second plurality of transistors are coupled to the transmission gate via the capacitor. The second plurality of transistors are coupled to a data input terminal and an output terminal.

An initial control voltage generating circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. The transmission gate resistor includes a P-channel type MOS (PMOS) transistor and an N-channel type MOS (NMOS) transistor coupled in parallel between the output node and the ground voltage terminal.

The invention discloses a time-to-digital converter based on a vernier double-chain structure, and relates to the technical field of integrated circuits. The converter comprises a signal holding circuit, a vernier double-chain rough measurement module, a data selector, a special time amplifier module and a digital coding unit, the vernier double-chain rough measurement module is composed of a main delay chain and a vernier delay chain, and 10ps-level rough measurement is achieved by adjusting the width-to-length ratio of an MOS tube of a phase inverter to control the delay difference of a unit. The data selector gates a residual time difference signal to the special time amplifier module, and the special time amplifier module is matched with a transmission gate through an RC network to realize 11mV / ps high-linearity time-voltage conversion; the digital coding unit integrates the rough measurement result and the accurate measurement result, and finally the 3.0 ps system resolution is achieved. A'rough measurement-fine measurement 'two-stage measurement architecture is adopted, a single-amplifier time division multiplexing design is adopted, a measurement dead zone is effectively eliminated, the chip area and power consumption are greatly reduced, and the device is particularly suitable for high-precision time measurement application such as laser radar and quantum calculation.

This invention discloses an image sensor and its fabrication method, belonging to the field of semiconductor technology. The image sensor includes at least: a substrate with a first isolation structure and a second isolation structure spaced apart within it; a photodiode, spaced apart from the first isolation structure and disposed within the substrate; a transmission gate, disposed on the substrate away from the photodiode and the first isolation structure; a floating diffusion region disposed within the substrate between the transmission gate and the second isolation structure, wherein the height of the side of the second isolation structure closest to the floating diffusion region is lower than the substrate surface, and a groove is formed therein; a source follower gate, spaced apart from the transmission gate and partially covering the second isolation structure; and a sidewall structure disposed around the transmission gate and the source follower gate, wherein the distance between the side edge of the transmission gate and the edge of the floating diffusion region is greater than the distance between the side edge of the transmission gate and the edge of the sidewall structure. The image sensor and its fabrication method provided by this invention can reduce white spot phenomena and dark current during imaging.