1065 results about "Transmission gate" patented technology

A shift register having a plurality of circuit cells successively connected in a chain formation is proposed. Each of the circuit cells includes a first inversion gate, a first transmission gate, connected to an output of the first inversion gate, being switched by a clock, and a second inversion gate connected to an output of the first transmission gate. The circuit cell further includes a first P-channel transistor, connected between an output of the second inversion gate and an input of the first inversion gate, being switched by the clock, a second transmission gate, connected to the output of the second inversion gate, being switched by an inversion clock, and a second P-channel transistor, connected to the output of the first transmission gate, being switched by the inversion clock. In the shift register, the plurality of circuit cells are successively connected such that the input of the first inversion gate of the circuit cell is connected to an output of a second transmission gate of a former-stage circuit cell, and the output of the first inversion gate of the circuit cell is connected to an output of a second P-channel transistor of the former-stage circuit cell.

A drive circuit is provided for an OLED pixel display. The drive circuit is adapted for use with a reference voltage source. It includes a first transistor and an OLED. The output circuit of the first transistor is operably connected between the reference voltage source and the OLED. Transmission gate means responsive to a control signal are provided to transmit a data signal to the first transistor. Means are provided for controlling the first transistor in accordance with a time domain modulation signal to provide an average current to the OLED which is a function of the data signal.

The present invention discloses an on die termination circuit. The on die termination circuit used in a DDR2 employs transmission gates as pull-up and pull-down switches, equalizes pull-up and pull-down resistance values by changing connection relations between switches and resistors, and maintains a constant voltage of an input pin.

The invention discloses a low-power dissipation RS latch unit and a low-power dissipation master-slave D flip-flop, which is characterized in that the low-power dissipation RS latch unit comprises an input driving and synchronizing circuit, a pull-down circuit, a function control circuit, a first phase inverter and a second phase inverter, wherein the first phase inverter and the second phase inverter are mutually overlapped and coupled. The low power dissipation master-slave D flip-flop is composed of an input phase inverter, a clock phase inverter, a first low-power dissipation RS latch unit and a second low-power dissipation RS latch unit, wherein the first low power dissipation RS latch unit and the second low power dissipation RS latch unit have the same inner structure and are cascaded. The low power dissipation master-slave D flip-flop has the advantages that the low-power dissipation RS latch units use three kinds of leaked power consumption lowering technology, i.e. P-type logic technology, function control technology and double-threshold technology, so that the low-power dissipation RS latch units have better leaked power consumption inhibiting performance. The low-power dissipation master-slave D flip-flop has simple and totally symmetrical circuit structure. Compared with the traditional single-threshold transmission gate D trigger circuit, the invention can save 80% of leaked power consumption and 40% of total power consumption in the 90 nm process, so that the invention is suitable to serve as a digital circuit unit to the design of low-power consumption integrated circuits in the deep sub-micron CMOS process.

A master-slave type flip-flop circuit consisting of a master latch and a slave latch, wherein the master latch comprises: a first clocked inverter to which data are input and a first latch circuit configuring a closed circuit with a first inverter and a second clocked inverter so that an output of the first clocked inverter is input to the first inverter and; the slave latch comprises: a transmission gate to which an output from the first latch circuit is input and a second latch circuit configuring a closed circuit with a second inverter and a third clocked inverter so that an output of the transmission gate is input to the second inverter, respective components configuring the master latch and the slave latch are configured with Sea Of Gate (hereinafter to be referred to as SOG) configuring a gate array, a basic cell of the SOG consists of triplely arrayed N-type transistors and corresponding triplely arrayed P-type transistors, the triplely arrayed N-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size and the triplely arrayed P-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size.

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

The invention provides a relaxation oscillator of which the linearity is significantly improved. The relaxation oscillator comprises an oscillating circuit, a reference level self-regulating circuit and a transmission gate selective signal generating circuit. Capacitor voltage overshoot caused by delay of a control circuit is worked out by detecting the voltage peak of charge and discharge capacitors in the oscillating circuit, and accordingly the reference level of comparators in the oscillating circuit is reduced by a corresponding quantity to serve as a new reference level so that the oscillation amplitude of the charge and discharge capacitors can be just a theoretical value. According to the high-linearity relaxation oscillator, when the new reference level is larger than zero, influence, brought by the capacitor voltage overshoot caused by delay of the control circuit, of the charge and discharge capacitors on output frequency is eliminated, and the linearity of a frequency-control circuit of the relaxation oscillator is significantly improved. The transmission gate selective signal generating circuit provides the initial reference level for the comparators by controlling transmission gates and transmits the new reference level to the reverse phase ends of the comparators when the new reference level is generated, and therefore the initial reference level can be isolated from the reverse phase ends of the comparators.

Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.

A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

The present invention relates to a pumped pixel that includes a first photo-diode accumulating charge in response to impinging photons, a second photo-diode and a floating diffusion positioned on a substrate of the pixel. The pixel also includes a charge barrier positioned on the substrate between the first photo-diode and the second photo-diode, where the charge barrier temporarily blocks charge transfer between the first photo-diode and the second photo-diode. Also included is a pump gate positioned on the substrate adjacent to the charge barrier. The pump gate pumps the accumulated charge from the first photo-diode to the second photo-diode through the charge barrier in response to a pump voltage applied by a controller. Also included is a transfer gate positioned on the substrate between the second photo-diode and the floating diffusion. The transfer gate transfers the pumped charge from the second photo-diode to the floating diffusion in response to a transfer voltage applied by a controller.

A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. A set of 64 transmission gates is configured to receive the 64 four data values. A first input signal is applied to the set of 64 transmission gates, thereby routing 32 of the 64 data values. A set of 32 transmission gates is coupled to receive the 32 data values routed by the set of 64 transmission gates. A second input signal is applied to the set of 32 transmission gates, thereby routing 16 of the 32 data values. A 16:1 multiplexer receives the sixteen data values routed by the set of 32 transmission gates. Third, fourth, fifth and sixth input signals are applied to the 16:1 multiplexer, thereby routing one of the 16 data values as the output of the LUT.

A sensor scan driver may include a shift register unit for driving photodiodes, a transmission gate unit for changing a voltage range of sensor scan signals generated by the shift register unit, and a buffer unit for supplying the sensor scan signals supplied from the transmission gate unit to the photodiodes, wherein the transmission gate unit includes first and second transmission gates, each including an electrode adapted to receive an output signal of the shift register unit, another electrode adapted to receive the inverted output signal of the shift register unit, an input terminal coupled to first and second power sources, respectively, and an output terminal coupled to an output terminal of the transmission gate unit.

The current consumed by latching data and during standby are significantly decreased in order to realize reduced power consumption. In this memory cell, source voltages V_RET and V_DD are supplied to latch circuit 10 and output circuit 32 from different systems. Latch circuit 10 can be separated from a peripheral circuit by NMOS transistor 20 and transmission gate 24. MOS transistors 12, 14, 16, and 18, which constitute latch circuit 10 and MOS transistors 20, 26, and 28, which constitute the switch circuit, are configured using low-leakage MOS transistors with leakage current significantly lower than those of standard MOS transistors used to configure the peripheral circuit including output circuit 32.

The invention provides a shift register, a grid driving device and a display device. The shift register comprises a latch, a transmission gate, a first thin film transistor, a second thin film transistor, a third thin film transistor and a first inverter, wherein a grid of the first thin film transistor is connected with a reset terminal of the shift register, a drain of the first thin film transistor is respectively connected with a drain of the second thin film transistor and an input terminal of the latch, a grid of the second thin film transistor is connected with an input terminal of theshift register, a grid of the third thin film transistor is connected with an inverted output terminal of the latch, a drain of the third thin film transistor is connected with an input terminal of the first inverter, an output terminal of the transmission gate is connected with the drain of the third thin film transistor, an input terminal of the transmission gate is connected with a clock signal input terminal, the drain of the third thin film transistor is connected with a normal phase output terminal of the shift register, and an output terminal of the first inverter is connected with an inverted output terminal of the shift register. The shift register can realize signal shift by the aid of one latch.

The present invention provides an energy recovering driver that includes a pull-up control, a pull-down control and a transmission gate. The pull up control is responsive to a pull-up control signal and a clock signal to turn the transmission gate ON and OFF and predetermined positions of the clock signal. The pull-down control is responsive to a pull-down control signal and the clock signal to turn the transmission gate ON and OFF at other predetermined locations of the clock signal. The transmission gate transmits the clock signal when at an ON condition and does not transmit the clock signal when in an OFF condition.

The invention discloses a GOA (Gate Driver On Array) unit, a driving method of the GOA unit, a GOA circuit and a display device, and belongs to the field of display technologies. The GOA unit comprises an input module, a power consumption reduction module, a reset module, a shifting register module and an output module, wherein the input module is connected with an input signal end, a first node and a control signal end; the power consumption reduction module is connected with the input signal end, a clock signal end, a power supply signal end and a second node; the reset module is connected with the power supply signal end, the control signal end and a third node; the shifting register module is connected with the first node, the second node, the third node and a fourth node; the output module is connected with the fourth node, the clock signal end, the power supply signal end, the control signal end and the output signal end; and the shifting register module comprises an inverter and a transmission gate. According to the invention, problems that the power loss of the GOA unit is high and that the electric potential of output signals cannot be determined are solved, and effects of reducing the power loss and improving the accuracy of the output signals are achieved.

The present invention offers an object proximity detector and an object position detector. The variation of frequency of an oscillator is used to detect the proximity of an object to the sensor plates. The dependence of frequency on process parameter is minimized by a compensation capacitor. It is not need to calibrate the product during the manufacture. In order to magnify the sensitivity, the sensor plates are placed in the feedback loop of the oscillator, instead of at the input of the oscillator. The independence of the process parameter and increasing of the sensitivity can be achieved by adding the compensation capacitor and place the sensor plates in the feedback loop at the same time. Multiple transmission gates are connected to the input and the output of the oscillator, and the sensor plates are connected to the transmission gates to form an object position detector.

Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.

The invention discloses a solid state imaging device, a method of producing solid state imaging device, and an electronic apparatus. A solid state imaging device includes: a substrate; a photoelectric conversion unit that is formed on the substrate to generate and accumulate signal charges according to light quantity of incident light; a vertical transmission gate electrode that is formed to be embedded in a groove portion formed in a depth direction from one side face of the substrate according to a depth of the photoelectric conversion unit; and an overflow path that is formed on a bottom portion of the transmission gate to overflow the signal charges accumulated in the photoelectric conversion unit.

A transmission line is terminated by a buffer. The buffer isolates a load from the transmission line using a transmission gate. The transmission gate is turned off and does not conduct most of the time, but turns on when a transition is detected on the transmission line, allowing the transmission line to directly drive the load for a short time. Once the load is switched beyond a logic threshold voltage, the transmission gate is again turned off and a latch or latching transistors driven by the transmission line continue to drive the isolated load to power or ground voltages. Driver transistors are also enabled when the transmission gate is turned on, driving either the output (load) node or the input (transmission line) node with the new data. Feedback from the output node disables the transmission gate and driver transistors once the output has been driven past the logic threshold.

The invention discloses a single event radiation effect resistant reinforced latch circuit. The single event radiation effect resistant reinforced latch circuit comprises a first transmission gate unit, a second transmission gate unit, a Schmitt inverter, a conventional input separation inverter, a first input separation clock-controlled inverter, a second input separation clock-controlled inverter, a delay circuit and a MullerC unit circuit. When the single event radiation effect resistant reinforced latch circuit operates under a transparent mode, a hysteresis effect of the Schmitt inverter and a delay difference of a latch interior unit are effectively used and SET pulses from a combinational logic unit are shielded through the MullerC unit; when the single event radiation effect resistant reinforced latch circuit operates under a latch mode, any interior node generating SEU due to the irradiation effect can be recovered through states of other nodes through a DIC unit structure having a self-recovery capability and correct output of the latch is guaranteed; accordingly the single event radiation effect resistant reinforced latch circuit has the advantages of effectively eliminating the radiation effect influences and being applicable to a clock gating circuit and small in power consumption and area costs.