165 results about "Transmission gate" patented technology

The invention discloses a photosensitive pixel element containing a P-type thin film transistor transmission gate and an image sensor. The photosensitive pixel element comprises a substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the single-layer or double-layer P-type thin film semiconductor layer is positioned above the dielectric layer and is in ohmic contact with the signal reading electrode through the opening part; the photoelectric conversion layer is located above the P-type thin film semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.

A memory circuit includes a memory cell, a bit line, a bit line bar, a pass-gate transistor coupled to the memory cell and the bit line, a sense amplifier coupled to the bit line, the bit line bar and the pass-gate transistor, and a pre-charge circuit coupled to the first node, and configured to pre-charge the first node to a pre-charge voltage in response to a pre-charge control signal. The sense amplifier includes a first path between the bit line and the bit line bar. The first path includes a first isolation transistor configured to receive an isolation control signal, and being coupled between the bit line and a first node, and a first inverter configured to receive a sense amplifier enable signal, and being coupled between a second node and a third node.

This application relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in the field of integrated circuit design technology. The latch includes: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module using two four-input inverting CE units and inversion operation to generate voltages for sensitive nodes A and B from signals from N1 to N7 and Q. This latch has good TNU (Terror-Noise Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

The application discloses a weak PUF circuit with rich excitation response based on MOS tube leakage current, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, a first PUF array, a second PUF array, two transmission gate arrays and one shared header, each PUF array comprises two column units, q is an integer greater than 1, each column unit comprises two NMOS units, p is an integer greater than 1, each NMOS unit comprises an NMOS tube, under the decoding action of the first decoder, the third decoder and the second decoder, the fourth decoder on the excitation signal, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array to generate a final output response, and the advantage is that the PUF entropy source utilization rate is improved by 2 times while the hardware overhead is kept small, and the number of CRPs is significantly improved. q p p+q ​​​

An SRAM device and its formation method are disclosed. The formation method includes: providing a substrate comprising a first type of device region and a second type of device region; the first type of SRAM device having a maximum channel width; both the first and second type of device regions comprising a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; forming a stacked structure on the substrate, comprising a first sacrificial layer and a channel layer; the width of each stacked structure in the second type of device region being equal to a preset width of the corresponding transistor region in the first type of device region; performing a channel width adjustment process; in the second type of device region, removing a portion of the channel layer width from any one or two of the transistor regions (transmission gate transistor region, pull-down transistor region, and pull-up transistor region); after removing the portion of the channel layer width, removing the first sacrificial layer; and after removing the first sacrificial layer, forming a gate structure spanning the channel layer. This invention uses the same design layout to form the stacked structure, saving design costs.

This application discloses a differential transmitter circuit, chip, and electronic device. The differential transmitter circuit includes: a single-slip differential drive enhancement circuit, including a single-ended digital input terminal (IN) and a first differential output terminal (IN_P, IN_N), used to convert the input single-ended digital signal into a pair of differential signals; a differential drive circuit, connected to the first differential output terminal (IN_P, IN_N), including a second differential output terminal (OUT_P, OUT_N), used to convert the differential signals into differential output voltages; wherein, the single-slip differential drive enhancement circuit includes a transmission gate (Tran) and an inverter, used to generate the differential signals with a phase difference of 180° and timing matching. The embodiments of this application aim to solve the technical problems of slow response speed, poor common-mode stability, high power consumption, and insufficient noise suppression capability in the prior art when transmitter circuits are used in LVDS interface applications.

The present disclosure provides a semiconductor structure comprising a substrate having a front side and a back side; an SRAM circuit having SRAM bit cells formed on a front side of the substrate, where each SRAM bit cell includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each SRAM bit cell is connected to the WBL, the WBLB, the RBL, the Vdd, and the Vss; a first subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the front side of the substrate to a first of the SRAM bit cells; a second subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the backside of the substrate to the first SRAM bit cell.

Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

The invention relates to a memory cell including a dual anti-fuse device, a memory structure, and a method of operation. A memory cell is disclosed that includes a dual anti-fuse device between a first pass-gate transistor and a second pass-gate transistor. A dual antifuse device includes first and second antifuses having a common terminal and also each having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between the first bit line and an additional terminal for the first pass-gate transistor. The second pass gate transistor is connected between the second bit line and an additional terminal of the second pass gate transistor. A common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a word line. A memory structure including an array of such memory cells and related methods of operation are also disclosed. Within the array, different word line and bit line bias conditions may be employed to reliably perform program or read operations for selected antifuses in selected cells.

The invention provides a high-voltage level shift circuit with high dVdt suppression capability, which is used for converting a signal in a low-voltage domain into a signal in a high-voltage domain and comprises an encyclopedia level shift module, a PMOS (P-channel Metal Oxide Semiconductor) coupling module, a noise current elimination module, a current compensation module, a transmission gate module and an RS (Reed-Solomon) latch module, the level shift module is used for transmitting signals from a low-voltage domain to a high-voltage domain, the PMOS coupling module is used for converting voltage signals transmitted by the level shift module into current signals, accelerating signal transmission and preventing common-mode signals from passing through, and the noise current elimination module is used for mirroring current, accelerating signal transmission and counteracting common-mode noise induction current. The current compensation module is used for compensating the current of a node, the transmission gate is used for transmitting a signal output by the noise elimination module to the RS latch, the RS latch module is used for recovering an edge narrow pulse signal into a square signal, and according to the scheme, the dV / dt noise suppression capability of the circuit is enhanced while low power consumption and low delay are achieved.

To provide an image sensor with improved electrical and optical characteristics. [Solution] The image sensor of the present invention comprises a semiconductor substrate, a pixel isolation structure disposed within the semiconductor substrate and defining first and second pixel regions, a transmission gate electrode provided to the first pixel region, a floating diffusion region provided to the first pixel region on one side of the transmission gate electrode, a pixel gate electrode provided to the second pixel region, a source / drain region provided to the second pixel region on one side of the pixel gate electrode, a connecting conductive pattern disposed on the first surface of the semiconductor substrate and connecting the floating diffusion region and the source / drain region, including an edge portion adjacent to the outer wall, and a blocking pattern disposed between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate.

The invention provides an 8T SRAM (Static Random Access Memory) unit, an 8T SRAM and a preparation method thereof, the 8T SRAM unit comprises a substrate, a pull-up transistor group, a pull-down transistor group and a transmission gate transistor group, the pull-up transistor group and the transmission gate transistor group are integrated on the front surface of the substrate, the pull-down transistor group is integrated on the back surface of the substrate, and the transmission gate transistor group is integrated on the back surface of the substrate. The first pull-down group comprises a first pull-down transistor and a second pull-down transistor which are arranged in parallel, and the second pull-down group comprises a third pull-down transistor and a fourth pull-down transistor which are arranged in parallel; the first pull-up transistor and the first pull-down group form a first phase inverter, the second pull-up transistor and the second pull-down group form a second phase inverter, and the first phase inverter and the second phase inverter are in cross coupling; the transmission gate transistor group comprises a first transmission gate transistor and a second transmission gate transistor, the first transmission gate transistor is connected with the first phase inverter, and the second transmission gate transistor is connected with the second phase inverter. According to the invention, the stability of the SRAM unit is improved.

Device for operating a passive infrared (PIR) detector with a first connection (IN) and a second connection (IP), the device comprising: - an electrical circuit arrangement (R G ), wherein the electrical circuit arrangement (R G ) forms a leakage resistance between the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR) to discharge the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR); wherein the electrical circuit arrangement (R G ) includes a switch-capacitor circuit with transfer gates and storage capacities; and the device is set up for this purpose: - the transfer gates of the electrical circuit arrangement (R G) to switch alternately with a first clock (φ1) and a second clock (Φ2), and to advance a charge quantity by one node with each half-clock using the storage capacities, whereby the first clock (φ1) and the second clock (Φ2) do not overlap and, apart from the non-overlap, the first clock (φ1) is the inverse of the second clock (Φ2); and - to switch off the first clock (φ1) and the second clock (Φ2) during a measurement phase, so that the device is in a measurement state and the charge flow through the electrical circuit arrangement (R G ) is prevented.

This invention discloses a frequency dithering control circuit, a control chip, and a switching power supply. The frequency dithering control circuit includes: a narrow pulse generation module, used to convert an input high-level enable signal into a low-level narrow pulse after the control chip is started; a current source charging and discharging module, used to charge a capacitor connected to a pin of the control chip when a low-level narrow pulse is received, and simultaneously output a first voltage signal based on the voltage signal detected at its detection terminal; and to discharge the capacitor when no low-level narrow pulse is received at its input terminal; a level shifting module, used to convert the first voltage signal into a second voltage signal, either the supply voltage or ground level, and then output it; and a frequency dithering switch module, used to control the conduction and cutoff of the transmission gate based on the second voltage signal, the narrow pulse, and the enable signal, thereby enabling and disabling the frequency dithering function of the control chip. This invention reduces the design difficulty for application engineers.

An apparatus includes a capacitor, a first plurality of transistors, a transmission gate, and a second plurality of transistors. The first plurality of transistors is coupled in series with each other via the capacitor. The first plurality of transistors are coupled between a first supply voltage terminal and a ground terminal. The transmission gate is coupled to a second supply voltage terminal. The second plurality of transistors are coupled to the transmission gate via the capacitor. The second plurality of transistors are coupled to a data input terminal and an output terminal.

An initial control voltage generating circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. The transmission gate resistor includes a P-channel type MOS (PMOS) transistor and an N-channel type MOS (NMOS) transistor coupled in parallel between the output node and the ground voltage terminal.

The invention discloses a time-to-digital converter based on a vernier double-chain structure, and relates to the technical field of integrated circuits. The converter comprises a signal holding circuit, a vernier double-chain rough measurement module, a data selector, a special time amplifier module and a digital coding unit, the vernier double-chain rough measurement module is composed of a main delay chain and a vernier delay chain, and 10ps-level rough measurement is achieved by adjusting the width-to-length ratio of an MOS tube of a phase inverter to control the delay difference of a unit. The data selector gates a residual time difference signal to the special time amplifier module, and the special time amplifier module is matched with a transmission gate through an RC network to realize 11mV / ps high-linearity time-voltage conversion; the digital coding unit integrates the rough measurement result and the accurate measurement result, and finally the 3.0 ps system resolution is achieved. A'rough measurement-fine measurement 'two-stage measurement architecture is adopted, a single-amplifier time division multiplexing design is adopted, a measurement dead zone is effectively eliminated, the chip area and power consumption are greatly reduced, and the device is particularly suitable for high-precision time measurement application such as laser radar and quantum calculation.

This invention discloses an image sensor and its fabrication method, belonging to the field of semiconductor technology. The image sensor includes at least: a substrate with a first isolation structure and a second isolation structure spaced apart within it; a photodiode, spaced apart from the first isolation structure and disposed within the substrate; a transmission gate, disposed on the substrate away from the photodiode and the first isolation structure; a floating diffusion region disposed within the substrate between the transmission gate and the second isolation structure, wherein the height of the side of the second isolation structure closest to the floating diffusion region is lower than the substrate surface, and a groove is formed therein; a source follower gate, spaced apart from the transmission gate and partially covering the second isolation structure; and a sidewall structure disposed around the transmission gate and the source follower gate, wherein the distance between the side edge of the transmission gate and the edge of the floating diffusion region is greater than the distance between the side edge of the transmission gate and the edge of the sidewall structure. The image sensor and its fabrication method provided by this invention can reduce white spot phenomena and dark current during imaging.

A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a first complementary inverter configured to receive a carry in signal, a second complementary inverter having an input coupled to the first complementary inverter and having an output at which a carry out signal is produced, and an output buffer subcircuit coupled to the input of the second complementary inverter. The output buffer subcircuit can include a first output buffer transistor coupled in series with a second output buffer transistor. The first complementary inverter can receive the carry in signal through a transmission gate that is controlled by two shift register clock signals.

The invention relates to the field of D-type edge triggers, in particular to a D-type edge trigger with a power-on initial state following CLK, which comprises a POR module, an initial state control module, a clock control module and a trigger module, the trigger module comprises a front loop latch unit and a rear loop latch unit, the POR module controls a power-on signal enH to turn over, and the initial state control module controls the clock control module to turn over. The trigger is controlled to be powered on and reset, the clock control module outputs an inverted clock signal clka and an in-phase clock signal clkb to the initial state control module, the high level and the low level of the control signal rst and the control signal perst are controlled, and it is ensured that the control signal rst and the clock signal CLK are in the same phase; on-off of transmission gates of the front loop latch unit and the rear loop latch unit is controlled, and a NAND gate is utilized to ensure that a control signal Q and a clock signal CLK in an initial state are in the same phase.

A system for calculating DNA short-read alignment comprises a memory comprising a plurality of memory cells, the memory comprising first and second regions, a plurality of transmission gates, a plurality of sense amplifiers, each having first and second outputs connected to each bitline in the memory, a plurality of logic gates, each connected to the first and second outputs of each sense amplifier, a digital peripheral circuit connected to the outputs of the logic gates, and a processor configured to perform steps comprising performing a Burrows-Wheeler transform on a nucleotide sequence represented as a string, storing the transformed nucleotide sequence in the first region of the memory, storing a short-read nucleotide sequence in the second region of the memory, activating first and second rows of the memory, and calculating DNA short-read alignment using the digital peripheral circuit.

The invention discloses a PTL-based processor calculation unit design method, which comprises the following steps: multiplexing a processor dual-port register, and obtaining the input of a PTL basic gate circuit from the output of the dual-port register, so as to form a PTL gate circuit as the design basis of a processor calculation unit. The PTL basic gate circuit comprises a NOT gate, an AND gate, an OR gate, an NAND gate, a NOR gate, an XOR gate, an XNOR gate or a transmission gate. And the processor calculation unit comprises an adder, a multiplier or a logical operation unit. And the dual-port register outputs complementary signal pair input of the PTL basic gate circuit.

The application relates to a laser radar detection chip integrating sensing and calculation, characterized by comprising a detection front end, a pixel array and an analog-digital conversion and readout circuit connected in sequence, wherein the pixel array comprises multiple pixel columns, a first bus and a second bus corresponding to each column, and a first differential calculation capacitor and a second differential calculation capacitor corresponding to each column; the first bus is connected with the first differential calculation capacitor; the second bus is connected with the second differential calculation capacitor; a first transmission gate switch is connected between the first buses of adjacent columns; a second transmission gate switch is connected between the second buses of adjacent columns; a pixel in the pixel array comprises an in-pixel detection circuit and an in-pixel multiplication circuit; the in-pixel multiplication circuit is connected with the in-pixel detection circuit and the corresponding first bus and second bus. Compared with the prior art, the application greatly improves the energy efficiency of the detection system, reduces the calculation delay, and reduces the bandwidth consumption and power consumption caused by the movement of redundant data.

The application discloses a method for calibrating a misadjustment voltage, a comparison device and a decision feedback equalization circuit. The method calibrates the misadjustment voltage by adjusting the voltage of the reference input end of the comparator. The method does not need to short the input end of the comparator, so it does not need to insert a transmission gate in the receiving link, thus not affecting the signal quality of the receiving end. After calibration, the eye diagram of the receiving end of the comparator is obviously larger, and the margin of the whole receiving end is greatly increased. In addition, for two single-ended signal comparators constituting the structure of the decision feedback equalizer, the method for synchronously adjusting the reference voltages of the two comparators is used to calibrate the misadjustment voltage, and the DFE strength is combined, so that the DFE and the misadjustment voltage calibration are simultaneously performed, and the logic complexity of the calibration system is greatly simplified.

An IC device includes a first complementary field-effect transistor (CFET) static random-access memory (SRAM) cell in a semiconductor wafer, the first CFET SRAM cell including a first internal node and a first pass gate including a first source / drain (S / D) region and a second S / D region electrically connected to the first internal node, and a second CFET SRAM cell in the semiconductor wafer, the second CFET SRAM cell including a second internal node and a second pass gate including a third S / D region and a fourth S / D region electrically connected to the second internal node, wherein the first S / D region is aligned with the third S / D region in a direction perpendicular to a frontside of the semiconductor wafer and a backside of the semiconductor wafer

The invention relates to the field of memories, and provides a nonvolatile memory, which comprises a bistable latch consisting of four nonvolatile metal compound transistors; the bistable latch is connected with the first transmission gate transistor through a first storage node and connected with the second transmission gate transistor through a second storage node, and the potential states of the first storage node and the second storage node are opposite and used for marking the two storage states of 0 or 1; the first transmission gate transistor and the second transmission gate transistor are both connected with a control main line and are connected or disconnected under the control of the control main line. The invention relates to a memory and a method thereof, and aims to solve the defects of power failure volatility, data loss risk, huge dynamic / static energy consumption and device heating of an SRAM (Static Random Access Memory) in the related technology, the memory provided by the scheme of the invention adopts a nonvolatile metal compound transistor, so that the memory also has nonvolatile property, and the data security is improved.

This invention discloses a CMOS transmission gate sampling switch circuit, a charge injection compensation method, an electronic device, and a storage medium. The CMOS transmission gate sampling switch circuit includes: a CMOS transmission gate, an output compensation circuit, and an input compensation circuit. The CMOS transmission gate includes a first NMOS transistor MN1 and a first PMOS transistor MP1. The gate of MP1 is connected to a second logic signal, and the gate of MN1 is connected to a first logic signal. The output compensation circuit includes MP2 for compensating for charge injection in the MP1 channel and MN2 for compensating for charge injection in the MN1 channel. The input compensation circuit includes MP3 for compensating for charge injection in the MP1 channel and MN3 for compensating for charge injection in the MN1 channel. The CMOS transmission gate sampling switch circuit, charge injection compensation method, electronic device, and storage medium proposed in this invention can effectively suppress injection errors while maintaining a miniaturized structure, overcoming the performance limitations caused by charge injection in existing designs.

This application provides an SRAM cell and an SRAM memory device. The SRAM cell includes a substrate, and a latch module, a write module, and a read module integrated on the substrate. The latch module includes a pull-up transistor group and a pull-down transistor group, forming a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled to form a first memory node and a second memory node. The write module includes a first transmission gate transistor group, which connects a first write word line and a first write bit line pair. The first transmission gate transistor group includes a first transmission gate transistor and a second transmission gate transistor. The first transmission gate transistor is connected to the first memory node, and the second transmission gate transistor is connected to the second memory node. The read module includes a first read module and a second read module, which are connected to the first memory node and the second read module is connected to the second memory node. This application improves parallel access capabilities.

The invention relates to a fail-safe input-output circuit. A circuit includes an input-output, a power supply terminal (113), a reference terminal (117), transistors (122) and (123), a driver circuit (120), and a bias generation circuit (125). The driver circuit (120) includes: a first inverter having an output; a second inverter having an input, an output, and a first power supply input and a second power supply input; and a transfer gate having an input, an output, and an enable input. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transfer gate is coupled to an output of a driver circuit (120), the first supply input of the second inverter is coupled to the output of the transfer gate, and the second supply input of the second inverter is coupled to the output of the driver circuit (120). And the second supply input of the second inverter is coupled to a reference terminal (117).