147 results about "Critical signal" patented technology

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

Mechanisms and techniques operate in a scalable or non-scalable processing architecture computerized device to execute critical code while overcoming interference from interruptions. A critical signal handler is registered and a non-operating system thread sets a value of a critical code register to indicate a critical execution condition. The non-operating system thread then executes a critical code section until an interruption occurs. In response to the interruption to the critical code section, an operating system thread detects if the critical code register is equivalent to a critical execution condition and if so, sets the value of the critical code register to indicate a critical execution failure. Upon returning to execution of the critical code section, the critical code section attempts to execute a contingent instruction in the critical code section that is contingent upon the value of the critical code register. The attempted execution of the contingent instruction triggers a critical trap signal when the critical code register is set to a value that indicates the critical execution failure. The critical execution signal handler processes the critical trap signal to avoid any interference that may have been caused by the interruption.

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

The invention relates to a buffer cell circuit for resisting the single-particle transient state which mainly consists of a single-particle transient-suppression buffer circuit and a signal-delay circuit, wherein, the signal-delay circuit consists of an inverter and a delay unit, the single-particle transient-suppression buffer circuit is an N-shaped single-particle transient-suppression buffer circuit or a P-shaped single-particle transient-suppression buffer circuit. With the adoption of the buffer circuit of the invention, the single-particle transient pulse which is generated on an input signal and provided with a pulse width smaller than the delay time internally set in a buffer, is eliminated, and key signals such as a clock, a reset, data, and the like, are effectively protected. At the same time, the buffer also possesses the strong ability for resisting single-particle transient state. In addition, The design for a circuit resisting single-particle is reinforced by adopting the buffer cell circuit for resisting the single-particle transient state, so that the area caused by the reinforcement of single-particle resistance and the power consumption are remarkably reduced compared with the common reinforcing methods, such as the triple modular redundancy, and the like.

A data processing system including a control chip, a central processing unit and a printed circuit board is provided. In the data processing system, the printed circuit board not only supports the control chip and the central processing unit, but also serves as an interface for transferring signals between the control chip and the central processing unit. Critical signals can be transmitted from the central processing unit to the control chip via the printed circuit with a better return path.

A method and apparatus are provided for transmission/reception of signals between automatic test equipment (ATE) and a device under test (DUT). A probe card has a plurality of associated proximate active probe integrated circuits (APIC) connected to a plurality of probes. Each APIC interfaces with one or more test interface points on the DUT through probes. Each APIC receives and processes signalscommunicated between the ATE and the DUT. Low information content signals transmitted from the ATE are processed into high information content signals for transmission to the probe immediately adjacent the APIC, and high information content or time critical signals received by the APIC from the DUT are transmitted as low information content signals to the ATE. Because the APIC is immediately adjacent the probe there is minimum loss or distortion of the information in the signal from the DUT.

The invention discloses a log management method, which records the log of the electronic system in a manner independent of the operating system, including: collecting the key signal of the key hardware by directly connecting with the key hardware of the electronic system, and not being affected by the electronic system during the collection process. The operating system control directly introduces key signals into the hardware controller; the hardware controller generates and saves logs according to the collected key signals. The state information of the system is collected and stored through the set hardware controller to generate logs, and there is no need to generate corresponding logs only through the current operating system of the system as in the prior art. In this way, when the system fails, such as crash, power failure, etc., it can also record the current status information of the system in time, generate and save the log, prevent the loss of key information, and improve the reliability and maintainability of the system.

The invention discloses an automobile semi-physical simulation experimental system combining a controller area network (CAN) bus and an electronic control unit, and belongs to the technical field of automobile design and development. The automobile semi-physical simulation system mainly comprises two parts: an entity part and a virtual simulation part, wherein the entity part is connected with the CAN bus through all systems including wheels, a frame, a power system and sensors of all control systems on an automobile chassis; the CAN bus is connected with the virtual simulation part through the electronic control unit; the virtual simulation part comprises a road view and a mathematical model; physical hardware is embedded into the simulation system; a software and hardware technique and an electronic technique are combined together; a computer is used for establishing a virtual model for reflecting an objective law; the virtual model is used for performing experiments; and certain acquired key signals are sent out by real hardware. The automobile semi-physical simulation system saves the cost compared with pure hardware, and has higher reliability compared with pure software.

The invention provides a system and a method for debugging an FPGA (field programmable gate array). The system comprises an FPGA logic module to be tested, a signal acquisition unit module, a trigger condition circuit unit module and a data transmission unit module, wherein the signal acquisition unit module acquires trigger signals transmitted from the FPGA logic module to be tested, and the trigger condition circuit unit module controls stopping of signal acquisition of the signal acquisition unit. The method adds a trigger condition circuit unit for debugging and a signal acquisition unit for acquiring key signals. The system and the method for debugging the FPGA have the advantages that external cables in debugging are omitted, the system is convenient to use, external high-capacity storage resources of the FPGA can be used, analyzable data volume after condition trigger is increased, and rapider positioning is benefited.

A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers and/or for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. Since the strobe may have a delay that is unknown (due to varying distances from the driver, clock jitter, and/or other causes), it is important to re-synchronize to the internal clock, and to do so with the smallest delay possible. This synchronization is provided in a way that also eliminates potential problems due to bus-master changeover, and in a way that minimizes time-critical signal generation. One aspect provides a method and/or apparatus for reliable data capture. The method includes: providing an N-stage latch including a first stage latch and a second stage latch, wherein N is two or larger; loading every Nth word of a data stream into the first stage latch using a first signal based on a strobe passed in the data stream; loading every N+1st word of the data stream into the second stage latch using a second signal based on the strobe passed in the data stream; unloading every Nth word from the first stage latch using a third signal based on an internal bus clock; and unloading every N+1st word from the second stage latch using a fourth signal based on the internal bus clock. In some embodiments, the first signal and the second signal are further based on a first stage selector and on a data_ready signal passed in the data stream.

Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.

The invention relates to an ISODATA-based interference source classification and identification algorithm and an ISODATA-based interference source classification and identification device, which belong to the field of electronic information, and perform classification and identification on unknown interference sources in space. The ISODATA-based interference source classification and identification algorithm comprises the steps of: acquiring PDW of signals in a region by using an interference source monitoring and positioning device, subjecting each class of eigenvalue output by the interference source monitoring and positioning device to one-dimensional ISODATA resolving, extracting an original eigenvalue within a time period from a queue to be retrived in an eigenvalue database, performing clustering analysis on the original eigenvalue by adopting multi-dimensional ISODATA, outputting a number of clustering and a feature clustering center value to a user in real time, and regarding the number of clustering and the feature clustering center value as effective features of a most possible interference signal. The ISODATA-based interference source classification and identification algorithm and the ISODATA-based interference source classification and identification device perform quasi-real-time unsupervised clustering analysis on an original monitoring result of the interferencesource monitoring and positioning device so as to present feature parameters of key signals in the monitoring result to the user, have higher flexibility, and are more reasonable.

An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).

The invention relates to a signal appliance fault source searching method for a signal central monitoring system. The signal appliance fault source searching method comprises the following steps that firstly, a key signal appliance fault source searching knowledge base is established; secondly, a fault source searching method is defined, the signal appliance warning information can be divided into three classes according to the linkage mode and can be divided into four classes according to the influence ways, and a source searching analyzing result is comprehensively controlled according to time parameters; thirdly, a fault source searching rule is converted, namely, a logical fault source searching rule is converted into a fault source searching information rule list; fourthly, the dynamic detecting judgment of a fault warning buffer pool is carried out, namely, a warning storage buffer pool is established, the dynamical warning source analysis is achieved through the fault source searching information rule list, and a warning result with the relation expression capability is finally formed through a plurality of related warning basis relevance modes; fifthly, the source warning is shown, and the fault analyzing method is refined. Compared with the prior art, the signal appliance fault source searching method has the advantage that the warning quality and the effectiveness are improved.

A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU signals and generates CPU performance data based on the critical CPU signals. An adaptive CPU throttler (THR) module uses the CPU performance data, along with a CPU percent idle value fed back from the operating system, to generate a CPU throttle control signal during predefined run-time segments of the CPU run time. The CPU throttle control signal links back to the CPU and adaptively adjusts CPU throttling and, therefore, power usage of the CPU during each of the run-time segments.