Method and circuit for reliable data capture in the presence of bus-master changeovers

Abstract

A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers and/or for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. Since the strobe may have a delay that is unknown (due to varying distances from the driver, clock jitter, and/or other causes), it is important to re-synchronize to the internal clock, and to do so with the smallest delay possible. This synchronization is provided in a way that also eliminates potential problems due to bus-master changeover, and in a way that minimizes time-critical signal generation. One aspect provides a method and/or apparatus for reliable data capture. The method includes: providing an N-stage latch including a first stage latch and a second stage latch, wherein N is two or larger; loading every Nth word of a data stream into the first stage latch using a first signal based on a strobe passed in the data stream; loading every N+1st word of the data stream into the second stage latch using a second signal based on the strobe passed in the data stream; unloading every Nth word from the first stage latch using a third signal based on an internal bus clock; and unloading every N+1st word from the second stage latch using a fourth signal based on the internal bus clock. In some embodiments, the first signal and the second signal are further based on a first stage selector and on a data_ready signal passed in the data stream.

Description

FIELD OF THE INVENTIONThis invention relates to the field of computer error correction, and more specifically to a method and apparatus for reliable data capture in the presence of bus-master changeovers.BACKGROUND OF THE INVENTIONMultiprocessor systems often include a single bus to which a plurality of processors are connected. Many such busses have a bus master (e.g., one of the processors) that controls or initiates data transfers, while the other processors or other devices on the bus are slaves. Some systems allow changes as to which device or processor is the bus master, such that the current bus master will release the bus, and a short time later, another device becomes bus master. Such computer systems include single-processor systems (using a single processor coupled on a bus to a plurality of other devices), as well as multiple-processor systems.Some such systems include a tri-state bus (or similar bus), wherein devices connected to the bus can drive the voltage low (e.g.,...

AI Technical Summary

Benefits of technology

Still another aspect of the present invention provides a method for reliable data capture from a bus, the method including: providing an N-stage FIFO including a first stage and a second stage, wherein N is two or larger; loading every Nth word of a data stream into the first stage using a first signal based on a stage selector, and on a strobe and a data_ready signal passed in the data stream; loading every N+1st word of the data stream i

Problems solved by technology

During periods in which one or more lines of the bus are in an undriven or high-impedance state, these lines are quite susceptible to noise, e.g., electromagnetic signals are picked up by the high-impedance lines, such that they can have a voltage that is interpreted by receivers on the line as a voltage or a clock edge.

As signal frequencies increase, radiated electromagnetic sig

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