341 results about "Failure analysis" patented technology

The invention relates to an aero-engine stator part crack critical dimension comprehensive determination method and system, and belongs to the technical field of aviation, the method comprises the following steps: obtaining an aero-engine typical hot end stator part geometric model and material parameters, and carrying out static strength analysis according to fluid-thermal-solid coupling load characteristics in actual working conditions; inserting an initial crack into a first principal stress plane of a dangerous part of the real component, carrying out crack propagation simulation to determine a crack propagation path, and calculating a critical crack size of a dangerous point; analyzing critical crack sizes under different failure modes, such as cooling failure and buckling failure; and integrating analysis results under the multi-failure mode, and determining a comprehensive critical dimension as a final judgment standard. According to the method, through combination of fracture failure and function failure analysis, accurate judgment of the critical dimension of the crack is realized, limitation of a traditional single fracture criterion is broken through, comprehensive function failure analysis is realized, the accuracy of a maintenance decision is remarkably improved, and a scientific basis is provided for condition-based maintenance decision.

The techniques disclosed herein provide a system for condensing large log files to enable interoperability with transformer-based large language models in automated failure analysis. In various contexts such as enterprise cloud services, log files can be large oftentimes containing millions of lexical units that can incur significant processing time and resource consumption. As such, the disclosed techniques provide a system for producing a directional knowledge graph representing a condensed form of a log file for automated failure analysis. Firstly, the log file is preprocessed to filter information that is irrelevant to the failure that previously occurred. The filtered lexical units are then used to generate a directional knowledge graph comprising a plurality of vertices which correspond to individual lexical units, and which are connected by edges representing the semantic connection between the lexical units. In this way, the directional knowledge graph significantly reduces processing times and improves resource consumption.

The invention discloses a multi-axis multi-field coupling fatigue test device, and belongs to the technical field of material testing. The device comprises a rack, a multi-axis loading unit, an environment simulation unit, a dynamic sealing interface and a cooperative control system. The core of the device is that the test sample can simultaneously bear the coupling effect of multi-axis mechanical stress (pulling, pressing and twisting) and various environmental fields (such as high and low temperatures, corrosive media, illumination and electric fields) through a highly integrated design; and the dynamic sealing problem of the actuator rod in the environment box is solved through an innovative dynamic sealing interface (such as labyrinth-magnetofluid composite sealing). According to the invention, accurate linkage control of multiple channels is realized through the cooperative control system, the service environment of key parts under actual complex working conditions can be truly simulated, and a reliable test platform is provided for failure analysis and life prediction of products under multi-field coupling.

The invention relates to the technical field of chip test vector intelligent generation scheme design, in particular to a failure analysis-oriented chip test vector intelligent generation method and system. The method comprises the following steps: acquiring a chip design netlist, a fault model and a known failure mode; analyzing potential design or manufacturing defects based on the information; and according to an analysis result, a targeted test vector capable of effectively exciting and isolating potential defects is automatically generated. The system comprises a corresponding input module, an analysis module and a generation module. According to the method, the design information, the fault model and the historical failure mode are intelligently fused, automatic and precise generation of the test vector is achieved, and the defects that a traditional method is insufficient in test coverage rate, low in failure positioning efficiency and limited in automation degree are overcome. According to the method, the test completeness and the failure analysis efficiency can be remarkably improved, the dependence on artificial experience is reduced, and an efficient technical means is provided for guaranteeing the reliability of the chip.

The invention relates to the technical field of material mechanical property testing, and discloses a composite steel wire tension test method which comprises the following steps: executing a micro-unloading and reloading action at each increment end point of stepping loading, and synchronously calculating to obtain instantaneous system rigidity Ki, dissipated energy Wd and system rigidity change rate K based on force displacement data of the action, according to the method, through a set of built-in judgment rules, firstly, the K value is used for filtering measurement artifacts generated by slippage of the clamp, then the damage inflection point is identified according to irreversible decline of the Ki value, and the physical property of the damage is discriminated in combination with two-dimensional state data of Ki and Wd, so that the traditional one-way destructive test is changed into the traditional one-way destructive test. The method is converted into a staged failure analysis process capable of performing online diagnosis, and provides a direct physical observation window for distinguishing functional damage and structural damage of the material, so that the depth and credibility of information acquisition of the tension test are improved.

A method, computer system, and a computer program product are provided for debugging and determining root cause analysis of a server error. Resource data is obtained as relating to a server with error or debugging needs and grouped based on learned and programmed context specific components to determine a root cause analysis for the error or debugging need. An overall solution is then provided to address the server error or debugging need by evaluation a root cause analysis. The overall solution analyzes a plurality of disparate reasons causing the server error or debugging need and providing a single coherent solution based on interconnectivity of the plurality of disparate reasons. The overall solution is updated by obtaining historical data. A recommendation is then provided for the server to resolve the error or the debugging need based on the updated overall solution.

The embodiment of the invention provides a fault prediction method and electronic equipment, and the method comprises the steps: forming a dominant failure factor group through a basic data set of target equipment in combination with a fault tree and failure analysis data; a hidden failure factor is formed through calculation of the minimum support degree and the confidence degree; combining the weight coefficient of the dominant failure factor of the fault point and the confidence coefficient of the recessive failure factor, analyzing the contribution degree of each failure factor to the fault by utilizing sensitivity, and forming a knowledge base; searching layer by layer and establishing a frequent item set; quantizing confidence coefficients between bottom layer single faults and between the bottom layer faults and the upper layer faults to form an equipment twin fault data model; and through neural network training, a prediction result is obtained through re-fusion of an evidence theory. According to the method, real-time fault prediction is realized, deep mining analysis of historical data is enhanced, the equipment model fault baseline data quality is perfected, the weight between a monitoring point and a failure factor is optimized, and the prediction efficiency and precision are effectively improved.

This invention discloses a method for predicting the high-temperature degradation of resistance in micro-copper pillar bump interconnects, comprising: establishing a relationship between the net flux of Ni atoms and the thickness variation of the Ni-Cu-Sn compound layer based on the thermal diffusion flux of Ni atoms; establishing a relationship between the net flux of Cu atoms and the thickness variations of the Cu6Sn5 and Cu3Sn layers based on the thermal diffusion flux of Cu atoms; and establishing a relationship between the Ni-Cu-Sn compound layer and the Cu6Sn layer based on these thickness variation relationships. s This invention provides an effective solution for predicting the high-temperature degradation of Ni-plated copper pillar bump interconnect resistors, significantly reducing or avoiding the time and economic costs associated with numerous lifetime and failure analysis tests. It establishes a high-temperature growth model for the Cu3Sn layer and its thickness; a high-temperature consumption model for the Cu pads, Sn solder, and Ni layer based on the thickness high-temperature growth model; and a high-temperature degradation model for the resistor based on the thickness high-temperature growth model and the thickness high-temperature consumption model.

The invention provides an operation and maintenance failure analysis and diagnosis method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that related texts of operation and maintenance failures are obtained, and the related texts comprise log texts and / or question texts input by a user and related to the operation and maintenance failures; matching the related text with a pre-constructed knowledge graph, and determining at least one recommended question text corresponding to the related text from the knowledge graph; and on the basis of each recommended question text, diagnosing the cause of the operation and maintenance failure. Through the related text of the operation and maintenance failure and the pre-constructed knowledge graph, accurate diagnosis and analysis of the operation and maintenance failure reason are realized, the accuracy and efficiency of diagnosis of the operation and maintenance failure reason are improved, and meanwhile, the solving efficiency of user problems and the user experience are improved.

The embodiment of the invention discloses an AI failure mode dynamic diagnosis method and system based on a sequence mode and function data analysis, which realize the crossing of AI interaction failure from static type identification to dynamic process diagnosis and improve the depth and timeliness of failure analysis. Accurate and explainable data support is provided for optimization of an artificial intelligence system. Through a sequence pattern mining and function data analysis technology, a failure pattern generated in an interaction process of a user and an artificial intelligence model (such as a large language model, a generative AI or an AI intelligent agent) is identified, analyzed and dynamically tracked, and the influence of the failure pattern is analyzed.

The invention relates to a semiconductor device failure analysis method. The semiconductor device failure analysis method comprises the following steps: selecting at least one failure port in a failure area of a tested semiconductor device as an input port, and acquiring an abnormal signal image of the tested semiconductor device through the input port; performing deviation comparison on the abnormal signal image and a qualified semiconductor device test feedback signal image to obtain an abnormal signal image peak value position; and dissecting the tested semiconductor device step by step from one end, far away from the input port, of the tested semiconductor device until the tail end of the abnormal signal image coincides with the peak position of the abnormal signal image, and finding the physical failure position of the tested semiconductor device. The semiconductor device failure analysis method has the advantages that the failure position can be accurately positioned, and rapid analysis is facilitated.

This utility model discloses a manual testing circuit and device for an IPM driver board. The circuit includes VIN, VCC, GND, G, and A terminals, and UH, VH, WH upper bridge input switch groups, N-segment lower bridge input switch groups, and BR, UH, VH, WH, UL, VL, WL output switch groups, respectively connected to the IPM driver board under test. VIN, VCC, and GND terminals are connected to the UH, VH, WH upper bridge input switch groups and the N-segment lower bridge input switch groups, respectively. G and A terminals are connected to the BR, UH, VH, WH, UL, VL, WL output switch groups, respectively. Using the circuit provided by this utility model, the switching function of the IPM driver board under test can be tested individually. By setting the UH, VH, WH upper bridge switch groups to control the individual power supply of the upper bridge arms of the IPM driver board under test, and by switching the N-segment lower bridge input switch groups to control the individual power supply of each phase of the lower bridge arm, fault analysis of a single bridge arm can be achieved. This allows for the screening of problematic IPM module driver boards before assembly, reducing losses caused by overall module test failures.

The application discloses a failure analysis method and related device, electronic equipment and storage medium, wherein the failure analysis method comprises: detecting based on the description document of the target agent to obtain the design elements of the target agent; analyzing based on the failure mode knowledge base and each design element to determine the first element suspected of existing failure risk and the first risk degree of the first element in each design element; selecting the first element as the second element based on the first risk degree of each first element; generating the test session and the adjudication rule of the second element based on the attack strategy knowledge base and the second element; determining the test reply of the second element based on the adjudication rule of the second element to obtain the second risk degree of the second element. The above scheme can identify the failure risk of the agent in advance before the agent goes online, and quantize the failure risk.

The invention belongs to the technical field of network security, and discloses an optimization filter-based cyber-physical system cascading failure security assessment detection method, which comprises the following steps of: performing data acquisition on a power system by analyzing a CPS (Cyber-Physical System) architecture, and respectively constructing a data uploading model and a data issuing model; then, learning an optimal filter over time by using the sensor observations to filter out malicious sensor observations while retaining other sensor measurements during data stream transmission; and finally, whether the data stream is attacked in the transmission process is judged by analyzing whether the data transmission quantity is suddenly and abnormally increased or decreased, a detector is optimized, and the false alarm rate is reduced. According to the method, cascading failure analysis is carried out on the CPS through the dynamic complex network, the analysis accuracy is enhanced, and therefore the reliability of the CPS is improved.

The invention provides a sample preparation method for PN junction profile contour failure analysis, and the method comprises the following steps: obtaining and cutting a defective wafer, obtaining a to-be-detected wafer, and enabling the defect to be located in the central region of the to-be-detected wafer; after the defect is marked, cutting the wafer to be detected to obtain a rough cutting sample, and enabling the defect to be positioned in a corner area of the rough cutting sample; etching the roughly-cut sample to expose a working area of the roughly-cut sample, and dyeing the working area of the roughly-cut sample; and thinning the rough cut sample to a thickness which can be observed by an electron microscope to obtain a sheet sample. The invention provides a sample preparation method for PN junction profile contour failure analysis, which can simply and accurately position a failure position.

This document describes systems and techniques directed at an interposer assembly for system-level failure analysis. In aspects, the interposer assembly may include a main body with a central aperture configured to provide optical access to an exposed surface of a semiconductor device. A plurality of probe pins may be arranged on the main body surrounding the central aperture, the plurality of probe pins configured to make electrical contact with a corresponding plurality of fine-pitch contact pads on the semiconductor device. The interposer assembly may further include at least one connector disposed on the main body and physically offset from the central aperture configured to receive a memory module. Circuitry within the main body electrically couples the plurality of probe pins to the at least one connector. In such a configuration, accurate optical imaging and fault isolation analysis can be enabled while a semiconductor device is fully operational.

The present disclosure provides a chip failure analysis method and device, which can solve the technical problem that related technologies cannot perform failure analysis on advanced processes. The method comprises: in the case of chip delayering to the contact layer, obtaining electrical measurement results by testing the combination of body diodes of a plurality of metal oxide semiconductor (MOS) tubes and testing the combination of MOS tubes and body diodes; and obtaining a chip failure analysis result according to the electrical measurement results. In the case of chip delayering to the contact layer (i.e. Via 0), the body diode effect of the MOS tube is utilized to directly determine whether Via 0 is abnormal through electrical measurement. The body diode of the MOS tube, the combination of the body diode and the MOS tube are utilized to quickly locate Via 0, and the chip failure analysis result is obtained. At most three pins are required for abnormal electrical testing, and the testing time is shortened by 50%. Furthermore, the carbon deposition on the surface of the sample is reduced, and the introduction of analysis noise is reduced.

The application provides an aero-engine blade fatigue failure analysis method, first, the foreign object damage morphology data of the real blade is collected to form a real blade database, then the design parameters of the simulation blade are obtained according to the morphology and stress distribution of the real blade, and then the finite element model of the simulation blade is established, the modal calculation is carried out, whether the inherent frequency of each order mode meets the set requirement is verified, if the set requirement is met, the foreign object damage simulation of the finite element model of the simulation blade is carried out, the simulation result is obtained, and the consistency verification is carried out with the real blade database, finally, the real model of the simulation blade is made, the FOD test and the HCF test are continuously carried out on the real model of the simulation blade, and the fatigue limit of the real model of the simulation blade after damage is obtained. The method takes the foreign object damage morphology data of the real blade as the reference, realizes the high-cycle fatigue limit test of the foreign object damage simulation blade which is closer to the real working condition, has low cost, high controllability of parameters, and good interpretability.

The application provides a chip-scale package interconnection structure failure analysis method and device, comprising: determining the failure external pin corresponding to the failure CSP package interconnection structure according to the current-voltage characteristic curve corresponding to each external pin; collecting and analyzing the time-domain reflection waveform of the failure external pin by using the electro-optical terahertz pulse reflection technology, positioning the target interconnection failure area in the interconnection path where the failure external pin is located according to the amplitude, time delay and waveform distortion characteristics of the reflection pulse; scanning the target interconnection failure area by using the three-dimensional X-ray microscopic imaging technology, and determining the target position of the failure point on the interconnection path where the failure external pin is located and the corresponding structural defects based on the scanning result. The application realizes the non-destructive failure analysis of the CSP package interconnection structure by combining the electro-optical terahertz pulse reflection technology and the three-dimensional X-ray microscopic imaging technology, and improves the failure point fault positioning accuracy and efficiency.

The application discloses a lithium battery failure analysis method and system based on a multi-channel RAG, and belongs to the technical field of lithium battery failure analysis. The method comprises the following steps: constructing a field knowledge vector library and a multi-level failure analysis knowledge graph; constructing a multi-channel retrieval enhancement generation framework, analyzing a user query intention, and obtaining related knowledge through a multi-channel cooperative mechanism of knowledge graph structure retrieval, knowledge graph semantic retrieval and field knowledge vector retrieval; calling a large language model to infer and generate a failure analysis result, and performing self-adaptive adjustment based on quality evaluation; and dynamically maintaining the knowledge base through internal and external knowledge updating. The application realizes unified modeling and structured expression of multi-source heterogeneous knowledge of failure analysis, improves the relevance and integrity of the retrieval result, reduces the dependence on artificial experience, and enhances the explainability and intelligent level of failure analysis.

The utility model discloses a cylindrical battery external short circuit testing device, which comprises clamping plates (2) arranged at two ends of a battery (1), the inner sides of the clamping plates (2) are provided with fixing sleeves (3), the battery (1) is inserted in the fixing sleeves (3), the clamping plates (2) are provided with stabilizing pieces (8) for clamping the battery (1), the fixing sleeves (3) are internally provided with contact terminals (4), and the contact terminals (4) are connected with the fixing sleeves (3). One side, far away from the fixing sleeve (3), of the clamping plate (2) is provided with a power line (5) and a voltage temperature sensing measuring line (6) which are connected with the contact terminal (4); the position of the cylindrical battery (1) is limited through the fixing sleeve (3), the battery (1) can be stabilized and positioned through the stabilizing piece (8) and the fixing sleeve (3), the voltage and temperature sensing measuring line (6) can be directly connected with a multi-path thermodetector, voltage and temperature at the two ends of the cylindrical battery (1) can be effectively monitored, and failure analysis and research of the battery (1) are facilitated.

The application provides a semiconductor test structure and a breakpoint failure positioning method. The semiconductor test structure comprises a first metal layer, a plurality of first sub-metal blocks arranged in a matrix along an X direction and a Y direction; a second metal layer, a plurality of second sub-metal blocks arranged in the X direction and the Y direction and arranged above the first sub-metal blocks in a staggered manner, the first sub-metal block and the second sub-metal block adjacent to the first sub-metal block in the staggered manner are connected in a head-to-tail manner through a conductive via to form a plurality of interconnected parallel and head-to-tail chain structures; and a dummy metal filling layer, a plurality of identification marks located at the periphery of the chain structure. Obviously, the semiconductor test structure provided by the application is that a plurality of identification marks are newly formed in the X direction and the Y direction in the dummy metal filling layer formed at the periphery of at least two asymmetric sides of the existing test structure for breakpoint failure analysis through filling or etching.

The embodiment of the specification discloses a network equipment thermal failure analysis method, equipment and medium, relates to the technical field of network equipment, and the method comprises the following steps: collecting dynamic field infrared data of a network equipment whole machine and real-time temperature data of each network device through a temperature measurement component of a thermal failure analysis device, wherein the dynamic field infrared data comprises real-time infrared data of a plurality of network devices; screening at least one thermal failure risk device meeting the requirements based on the dynamic field infrared data and the temperature threshold of each network device; determining the real-time temperature data of each thermal failure risk device, generating a temperature rise curve of each thermal failure risk device based on the real-time temperature data and pre-acquired traffic forwarding data; analyzing the temperature rise curve according to pre-acquired network equipment operation requirements to generate a whole machine failure risk; and determining a corresponding thermal design optimization scheme to optimize the thermal failure of the network equipment through the whole machine failure risk.

The application belongs to the technical field of material engineering and failure analysis, and particularly relates to a metal fatigue micro-damage detection method, device, medium and equipment, the method comprising the following steps: acquiring a longitudinal wave sound velocity of a metal material to be detected; calculating a normalized damage index of the metal material to be detected based on the longitudinal wave sound velocity; taking the normalized damage index as an input of a fatigue micro-damage evaluation model that has been constructed, and obtaining a plastic strain of the metal material to be detected, so as to realize fatigue micro-damage detection of the metal material to be detected. The application can improve the sensitivity of metal fatigue micro-damage detection.

The invention discloses a wind power blade subcomponent structure bending torsion loading failure analysis and optimization method, and belongs to the technical field of wind power blade structure mechanical analysis. The analysis method comprises the following steps: establishing a three-dimensional entity finite element model of a wind power blade sub-component, applying pure shimmy, pure torsion and gradient bending-torsion combined load to carry out nonlinear static analysis, extracting critical failure point data, and comparing and analyzing a rear edge buckling waveform, bonding failure migration and contact behavior change, so as to obtain a critical failure point. According to the method, the internal relation of blade rear edge bonding structure failure, buckling waveform and contact behaviors under the bending-torsion coupling working condition is defined, the migration rule of the rear edge failure position along with the torsion angle and the stress distribution difference between the front edge and the rear edge are defined, and the problem that in the prior art, it is difficult to accurately position the blade vulnerable area under bending-torsion coupling is solved; and a mechanical basis is provided for blade structure optimization. The analysis result obtained through the analysis method can be directly used for guiding the anti-bending coupling design of the blade.

This invention discloses a system and method for analyzing switch tube faults based on the SVM algorithm, belonging to the field of switch tube fault diagnosis technology. The system includes a data acquisition module, a database, an intelligent analysis module, an intelligent adjustment module, and a fault diagnosis module. The data acquisition module collects control data and electrical parameter data from several switches in an offshore wind turbine generator during operation. The database stores historical control data and historical electrical parameter data. The intelligent analysis module trains an SVM model and analyzes the impact of different switching frequencies and losses on the accuracy of the SVM model. The intelligent adjustment module adaptively adjusts the data acquisition frequency of electrical parameters at different switch tube nodes. The fault diagnosis module inputs the collected electrical parameter data into the trained SVM model to diagnose switch tube faults.

The application discloses a kind of power environment monitoring systems applied to UPS power supply in computer room, it is related to environmental monitoring technical field, the application includes: UPS equipment environment inspection module, UPS equipment fault analysis module, UPS equipment fault analysis module and local database, by through dust concentration, wind speed, wind direction, line width and temperature five-dimensional data fusion, dynamic wear model is established, the impact of sand and dust to connecting line is simulated, to assess the harm of sand and dust to connecting line, can timely and accurately style connecting line hazard, guarantee the safety of the connecting line of UPS power supply equipment, simultaneously, by gray image analysis vertical direction jitter offset coefficient, vibration-soundprint composite diagnostic model is constructed in combination with operating decibel value, to reduce the failure rate of UPS power supply equipment.

A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and / or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations using a rules-based approach.

The invention provides a chip failure analysis method and device, and can solve the technical problem that failure analysis cannot be carried out on an advanced process in related technologies. The method comprises the following steps: under the condition that a chip is subjected to layer removal to a contact layer, obtaining an electrical property measurement result through combined testing of body diodes of a plurality of metal oxide semiconductor (MOS) tubes and combined testing of the MOS tubes and the body diodes; and obtaining a failure analysis result of the chip according to the electrical property measurement result. Under the condition that a chip is subjected to layer removal to a contact layer (namely Via 0), whether Via 0 is abnormal or not is directly judged through electrical measurement by utilizing the body diode effect of the MOS tube. And quickly positioning at the Via 0 end by using the body diode of the MOS tube and the combination of the body diode and the MOS tube to obtain a failure analysis result of the chip. Three pins are needed at most for an abnormal electrical test, and the test time is shortened by 50%. Furthermore, carbon deposition on the surface of the sample is reduced, and introduction of analysis noise is reduced.

To appropriately reduce flicker caused by random noise in an analysis image used in failure analysis of a semiconductor device.SOLUTION: A learning method is a method for generating an inference model used to reduce flicker caused by random noise from an analysis image that is used in failure analysis of a semiconductor device. The method comprises: a learning acquisition step (S01) for acquiring an analysis image for learning including a target signal related to a semiconductor device and including random noise, and a noise image for learning including no target signal and including random noise; a noise addition step (S02, S03) of reducing the contrast of the analysis image for learning and adding random noise of the noise image for learning to the analysis image for learning with reduced contrast to generate a noise-added image for learning; and a training step (S04) in which machine learning of the inference model is trained using the noise-added image for learning.SELECTED DRAWING: Figure 6