310results about How to "Reduce contact resistance" patented technology

A semiconductor light emitting device includes a semiconductor light emitting portion having a first contact layer of a first conductivity, a second contact layer of a second conductivity and an active layer sandwiched between the first and second contact layers. The device further includes a transparent electrode which substantially entirely covers a surface of the second contact layer in ohmic contact with the surface of the second contact layer and is transparent to a wavelength of light emitted from the semiconductor light emitting portion, and a metal reflection film which is opposed to substantially the entire surface of the transparent electrode and electrically connected to the transparent electrode, and reflects the light emitted from the semiconductor light emitting portion and passing through the transparent electrode toward the semiconductor light emitting portion.

A plurality of solar cells is connected together in a shingled fashion. Each of the solar cells includes grid wires that are attached to an electrode of the solar cell so as to receive charge carriers produced when photons are absorbed by the solar cell. The grid wires are then interconnected with adjacent solar cells when the solar cells are shingled together. The grid wires may be applied to the solar cells via a laminate and the electrical interconnection of the grid wires may be achieved by the use of a conductive epoxy.

The invention provides a silver conductive paste used for positive electrode of solar battery and a preparation technique thereof. The paste comprises silver powder, glass powder, an organic carrier and an additive, wherein the silver powder accounts for 65 to 85 percent of the total weight of the paste and consists of two types of silver powder with different particle sizes; the first type of silver powder has the particle size range of 3 to 15 micrometers and is spherical; the second type of silver powder has the particle size range of 0.1 to 3 micrometers and is spherical; the first type of silver powder accounts for 20 to 50 percent of the total silver powder; the glass powder is of Pb-B-Si-Zn-Ti-Al-O series and accounts for 1 to 10 percent of the total weight of the paste; the organic carrier accounts for 10 to 20 percent of the total weight of the paste; and the additive accounts for 0.1 to 3 percent of the total weight of the paste, and consists of BaO powder and CaO powder. The silver powder with different particle size ranges is mutually filled, thus greatly improving the electrical property of the electrode and improving the photoelectric conversion efficiency of the battery. In addition, the invention can ensure good ohmic contact between the paste and a substrate.

A method for manufacturing a semiconductor device includes the steps of: (a) forming a gate electrode on a substrate, forming source/drain regions and a channel forming region in the substrate, and forming on the source/drain regions a first interlayer insulating layer equal in height to the gate electrode; (b) forming in the first interlayer insulating layer groove-shaped first contact portions connected to the source/drain regions; (c) forming a second interlayer insulating layer on a whole surface; (d) forming hole-shaped second contact portions in portions of the second interlayer insulating layer on the first contact portion; and (e) forming on the second interlayer insulating layer wires connected to the second contact portions.

A galvanic element includes the following elements in the order listed: a current collector associated with an anode; the anode; an ion-conducting separator in the form of a continuous layer; a cathode; and a current collector associated with the cathode. The anode encompasses an ion-conducting support structure, and both the ion-conducting support structure and the separator encompasses an ion-conducting material. The ion-conducing support structure is porous.

A thin film transistor includes a gate electrode; an active layer formed of an oxide and insulated from the gate electrode; and a source electrode and a drain electrode formed of an oxide on the active layer such that the source electrode and the drain electrode are insulated from the gate electrode and electrically connected to the active layer, wherein the active layer, the source and the drain electrode are formed using an atomic layer deposition (ALD) and an insitu process, and a root mean square (RMS) value of the surface roughness of the active layer which contacts with the source and drain electrodes is less than 1 nm in order to reduce the contact resistance between the active layer and the source and drain electrodes, a method of manufacturing the same, an organic light emitting display apparatus including the thin film transistor, and a method of manufacturing the same.

The invention discloses an organic light emitting display device. An auxiliary conductive layer is directly formed on an electrode power line and is exposed out of partial region of the electrode power line; and a second electrode extends to the non-display region and continuously covers the surface, away from the electrode power line, of the auxiliary conductive layer and the exposed surface of the electrode power line. The areas where the second electrode is contacted with the electrode power line and the auxiliary conductive layer are large, the electrode power line thus can easily build a short conductive path via the auxiliary conductive layer, contact resistance between the second electrode and the electrode power line can be effectively reduced, and voltage drop between the electrode power line and the second electrode is reduced. According to the organic light emitting display device manufacturing method disclosed by the invention, the technology is simple, and the manufacturing cost is low.

Embodiments of the invention generally relate to conductive foils having multiple layers for use in photovoltaic modules and methods of forming the same. The conductive foils generally include a layer of aluminum foil having one or more metal layers with decreased contact resistance disposed thereon. An anti-corrosion material and a dielectric material are generally disposed on the upper surface of the metal layer. The conductive foils may be formed on a carrier prior to construction of a photovoltaic module, and then applied to the photovoltaic module as a conductive foil assembly during construction of the photovoltaic module. Methods of forming the conductive foils generally include adhering an aluminum foil to a carrier, removing native oxides from a surface of the aluminum foil, and sputtering a metal onto the aluminum foil. A dielectric material and an anti-corrosion material may then be applied to the upper surface of the sputtered metal.

Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.

An electrode comprises a planar collector, and an active material containing layer disposed on the collector. The active material containing layer comprises a plurality of particles containing an active material, and a binder for binding the particles containing the active material to each other and the particles containing the active material to the collector. The collector has a surface depressed in conformity to a form of the particles containing the active material.

The present invention is to provide a solid electrolytic capacitor having a small equivalent series resistance. In this solid electrolytic capacitor, a capacitor element is buried inside of an outer package of an epoxy resin or the like, the capacitor element including an anode in which a part of an anode lead is buried, a dielectric layer which is formed on the anode and contains a niobium oxide and a cathode which is formed on the dielectric layer. The cathode includes a first electrolyte layer which is formed on the dielectric layer and contains a conductive polymer, an intermediate layer which is formed on the first electrolyte layer and contains organic silane, a second electrolyte layer which is formed on the intermediate layer and contains a conductive polymer, a first conductive layer which is formed on the second electrolyte layer and contains carbon particles and a second conductive layer which is formed on the first conductive layer and contains silver particles. Also, one end of a cathode terminal is connected with the cathode through a third conductive layer containing silver particles. Also, each of the other ends of an anode terminal and cathode terminal is exposed from the outer package.

A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.

In the array substrate where the display region has the non-quadrangle shape, a sub-capacitance line which forms a sub-capacitance is disposed at the pixel, a intersection region of the scanning lead-out line and a signal lead-out line is located at the frame region on the outside of the display region, a common lead-out line which connects the sub-capacitance line in common is disposed at the frame region side where the scanning lead-out line is disposed, the common lead-out line is not disposed in the intersection region, but disposed in a region between a region of the scanning lead-out line and a region of the signal lead-out line while intersecting any one of the scanning lead-out line and the signal lead-out line.

A semiconductor device includes a semiconductor substrate, source and drain regions on the semiconductor substrate, and contact plugs connected to the source and drain regions. The contact plugs includes first impurity-diffused epitaxial layers that contact with the source and drain regions.

A trench PT IGBT (or NPT IGBT) having clamp diodes for ESD protection and prevention of shortage among gate, emitter and collector. The clamp diodes comprise multiple back-to-back Zener Diode composed of doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above said semiconductor power device. Trench gates are formed underneath the contact areas of the clamp diodes as the buffer layer for prevention of shortage.

A pneumatic tire which positively discharges water having flowed into a groove extending in the tire circumferential direction and enhances capability of preventing hydroplaning. The groove is provided in the tread face of the tire and extends in the tire circumferential direction. The wall face of the groove is provided with line portions composed of a plurality of ridges or recesses that are inclined in one direction with respect to the groove longitudinal direction.

The invention discloses a current collector with a surface decorated with vertical orientated grapheme. The surface of the current collector is decorated with a layer of vertical orientated grapheme nanosheets. The invention further discloses a preparation method of the current collector with the surface being decorated with the vertical oriented grapheme. According to the preparation method, a mixed gas composed of carbon source gases, indefinite form carbon etching gases and argon is used as a precursor, the method of enhancing chemical vapor deposition with plasmas is applied, and thus the current collector with the surface being decorated with the vertical orientated grapheme is obtained without adhesion agents. The surface of the current collector obtained through the preparation method is decorated with a layer of net structure composed of the vertical orientated grapheme nanosheets, edges with dense exposed grapheme are provided, therefore, the current collector can get contact with active materials thoroughly, internal resistance is reduced, the purposes of high magnification and high power density energy storage are achieved when the current collector is applied to energy storage devices such a super capacitor and a secondary battery.

The present invention is to provide an anisotropic conductive adhesive (ACA) for ultrasonic wave adhesion, which electrically connects a first electrode, which is an electrode of a connection portion of a first electronic component, with a second electrode, which is an electrode of a connection portion of a second electronic component. The anisotropic conductive adhesive includes an insulating polymer resin, conductive adhesive particles which are melted by heat generated from the ultrasonic waves applied to the anisotropic conductive adhesive, and spacer particles, which have a melting point higher than that of the adhesive particles, and wherein the adhesive particles are melted and made to come in surface contact with at least one electrode selected from the first electrode and the second electrode, and the first electrode and the second electrode are electrically connected with a constant gap maintained between the first electrode and the second electrode by the spacer particles.

A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg alloy layer 32 which is formed of Mg and a metal selected from a group consisting of Pt, Mo, and Pd. The Mg alloy layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

A semiconductor device including a polysilicon plug with a reduced contact resistance and a manufacturing process therefor. The process includes the steps of forming a hole in an insulating layer on a semiconductor substrate; forming polysilicon over the whole surface of the insulating layer such that it fills the hole; forming a polysilicon plug in the hole by etching back a polysilicon; and heating the semiconductor substrate including the polysilicon plug within the insulating layer under a hydrogen atmosphere.

An organic TFT including a gate electrode, a source electrode and a drain electrode insulated from the gate electrode, and an organic semiconductor layer that is insulated from the gate electrode and contacts the source electrode and the drain electrode. The length of portions of edges of the source electrode, which contact the organic semiconductor layer and face the drain electrode, is greater than the length of portions of edges of the drain electrode, which contact the organic semiconductor layer and face the source electrode to reduce the contact resistance between the source electrode and the organic semiconductor layer.

The invention provides a surface treatment method of metal oxide semiconductor and a preparation method of a thin film transistor, wherein the surface treatment method of the metal oxide comprises the following steps that: plasmas are utilized for carrying out surface treatment on a device to be treated; and the plasmas comprise mixed gas of F-base gas and O2, and the device to be treated is a metal oxide semiconductor product or a product plated with the metal oxide semiconductor. In the embodiment provided by the invention, the plasmas obtained by using the mixed gas of F base gas and O2 are used for treating the metal oxide for enhancing the oxygen vacancy concentration in the metal oxide, reducing the contact resistance between the metal oxide and other electrodes and improving the ohm contact effect of the metal oxide.

The etching method includes etching the silicon oxide film by supplying a halogen-containing gas and a basic gas to the substrate so that the silicon oxide film is chemically reacted with the halogen-containing gas and the basic gas to generate a condensation layer; etching silicon by supplying a silicon etching gas, which includes at least one selected from the group consisting of an F₂ gas, an XeF₂ gas, and a ClF₃ gas, to the substrate; and after the etching of the silicon oxide film and the etching of the silicon, heating and removing the condensation layer from the substrate.

The invention discloses a cylindrical power battery module structure which comprises at least two battery modules connected in series with each other. Each battery module comprises a battery cell group, a battery cell bracket, an anode nickel piece, a cathode nickel piece and a circuit board; the battery module structure comprises a nickel piece connection rigid pressure plate, nickel piece connection bolt and nut, module connection bolt and nut and a support; the battery cell brackets, the battery cell groups, the anode nickel pieces and the cathode nickel pieces are assembled to form the battery modules; and the battery modules are connected into a battery module through the nickel piece connection rigid pressure plate, the nickel piece connection bolt, the nickel piece connection nut, the module connection bolt, the module connection nut and the support. According to the invention, the nickel pieces among the battery modules are connected by the multipoint bolts of the rigid pressure plate; the nickels of the module are in direct close pressure-equalizing connection, and the little total internal resistance, low self consumption and high reliability of electric connection of the module are guaranteed; the anode side structure and the cathode side structure of the battery module correspond to and are matched with each other; the capacity expansion of the battery module is facilitated, and the standard design of the battery module structure is easy to realize; and large-scale production is facilitated, and the manufacturing cost is lowered.

Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

The invention discloses an RFLDMOS (Radio Frequency Laterally Diffused Metal Oxide Semiconductor) based on a self-aligned silicide and tungsten plug structure and a manufacturing method thereof. By utilizing a double-diffusion method, a source high-doping area and a drain high-doping area which have lateral channel structures are manufactured on a silicon slice, and a multicrystal silicon grid ismanufactured; the manufacturing method of the RFLDMOS based on the self-aligned silicide and tungsten plug structure is characterized by further carrying out the following treatments: forming a silicon dioxide layer on the surface; etching off parts of the silicon dioxide layer at the tops of a source and a drain, and depositing a layer of metal on the whole surface of the silicon slice; carryingout high-temperature annealing treatment to form a metal silicide in a silicon-exposed area on the silicon slice surface; manufacturing a dummy faraday gate above the multicrystal silicon grid, manufacturing an oxide dielectric layer on the whole silicon slice surface, manufacturing through holes communicated to the metal silicide at parts corresponding to metal silicide contact holes, and filling tungsten in the through holes; and arranging metal layers respectively corresponding to the through holes of the source and the drain to form a contact electrode. According to the RFLDMOS based on the self-aligned silicide and tungsten plug structure and the manufacturing method thereof disclosed by the invention, the series impedance of a source end is reduced, and the power gain of devices is effectively increased.

The invention relates to a low threshold voltage static micro relay, which comprises a movable comb and a fixed comb, a foldable spring beam and a multi-level comb connecting beam. A flat-plate capacitance is formed between the fork tines on the corresponding movable comb and the fork tines of the fixed comb. When the electric excitation is implemented, the movable comb drives the multi-level comb connecting beam to generate a transverse displacement, so that a contact contacts the fixed electrode in the circuit. When the electric excitation is removed, the elastic recovery force of the foldable spring beam allows the multi-level comb connecting beam to drive the contact to reset. The invention reduces the threshold voltage of micro relay by connecting comb level number in parallel manner and increasing number of the fork tines, thus solving the high driving voltage of the static micro relay and difficult compatibility with working circuit voltage in the prior art. The threshold voltage can be reduced to 5V, so that the driving voltage of the static micro relay can be compatible with the working voltage of common electronic circuit, thereby realizing reliable switch action under the working voltage of common electronic circuit.

Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by a thermal annealing process, and performing a laser anneal process on the substrate. In another embodiment, the method includes providing a substrate having implanted dopants, performing a silicidation process on the substrate by a thermal annealing process, and activating the dopants by a laser anneal process.

The present invention provides a positive electrode for lithium ion battery reducing a contact resistance of a battery and achieving an excellent output property. The positive electrode for lithium ion battery comprising a mixed layer comprising:

• • metal forming a current collector, and
  • positive electrode active material dispersed in a state of layer in the metal forming the current collector.

The invention relates to an electroconductive paste composition and a method of producing the same. The electroconductive paste composition can form wiring patterns on electrodes, with high conductivity, good adhesion and low contact resistance to a transparent conductive firm, good moisture resistance, good weather resistance and high reliability. In particular, the electroconductive paste composition is characterized by including fluororesin, solvent and conductive powders mainly composed of silver or silver compound; wherein fluorine atom content in the fluororesin is higher than 40% by mass and lower than 75% by mass.