407 results about "Selective deposition" patented technology

Various embodiments described herein relate to methods, apparatuses, and systems for post-development treatment of a metal-containing photoresist mask to improve lithographic performance. After development, the metal-containing photoresist mask may be exposed to one or more of the following treatments: thermal anneal, plasma exposure, exposure to reactive gases, and selective deposition of a protective film. In some embodiments, the metal-containing photoresist mask is exposed to one or more reactive gases to compositionally change the photoresist mask and / or selectively deposit a protective film on top surfaces and sidewalls of the photoresist mask. The treated photoresist mask may exhibit increased line CD for reduced dose-to-size and improved etch resistance.

Provided are methods of filling patterned features with molybdenum (Mo). The methods involve selective deposition of Mo films on bottom metal-containing surfaces of a feature including dielectric sidewalls. The selective growth of Mo on the bottom surface allows bottom-up growth and high quality, void-free fill. Also provided are related apparatus.

Provided are methods of filling patterned features with molybdenum (Mo). The methods involve selective deposition of Mo films on bottom metal-containing surfaces of a feature including dielectric sidewalls. The selective growth of Mo on the bottom surface allows bottom-up growth and high quality, void-free fill. Also provided are related apparatus.

Method for area selective deposition (ASD) on a substrate containing a growth surface that is exposed and a non-growth surface that is exposed. The method includes cyclical exposures of a deposition gas containing a metal carbonyl precursor, the metal carbonyl precursor decomposing on the growth surface such that a metal film is deposited on the growth surface and carbon monoxide (CO) gas is released, and an inhibitor gas after stopping the flow of the deposition gas to the substrate. The cycling between flowing the deposition gas to the substrate and flowing the inhibitor gas to the substrate is repeated to selectively form the metal film on the growth surface relative to the non-growth surface, where the inhibitor gas increases the selectivity of the metal film formed on the growth surface when compared to the selectivity of the metal film formed on the growth surface without the inhibitor gas.

The current disclosure relates to methods and assemblies for selectively depositing metal-containing materials, such as metal oxides, on different surfaces of a semiconductor substrate by cyclic vapor deposition techniques, including atomic layer deposition. The metal-containing material is deposited using a metal precursor having a metal atom bound to an acetamidinato ligand, such as dialkylacetamidinato ligand. The metal-containing material may be deposited on a metal surface relative to a dielectric surface, or to a dielectric surface relative to a metal surface, depending on the process flow. The current disclosure further relates to layers, structures and semiconductor devices deposited according to the methods disclosed herein, as well as to semiconductor processing assemblies configured and arranged to perform said methods.

The present disclosure provides embodiments of processes and methods for stabilizing self-assembled monolayers (SAMs). In the present disclosure, a cyclic vapor deposition process is used to selectively deposit a polymer thin film on a SAM structure formed on a target material. The polymer thin film selectively deposited on the SAM structure stabilizes the SAM structure by: (a) healing defects in the SAM structure and providing blanket coverage over the target material surface, (b) preventing migration of SAM-forming molecules to neighboring non-target surfaces, and (c) increasing the thickness and rigidity of the SAM structure. In one embodiment, sequentially pulsed initiated chemical vapor deposition (spiCVD) is used to selectively deposit the polymer thin film on the SAM structure.

The invention provides a method for depositing silicon nitride on the side wall of a groove structure, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps of: depositing carbon-containing barrier layers on the top, the side wall and the bottom of a groove structure by utilizing inductively coupled plasma enhanced chemical vapor deposition, and then carrying out directional etching on the side wall of the groove by utilizing ammonia plasma bombardment, so that the carbon-containing barrier layers on the side wall of the groove are accurately removed, and the barrier layers in the top and bottom areas are kept complete; and finally, using inductively coupled plasma to enhance atomic layer deposition, and selectively depositing a silicon nitride film in the side wall area of the groove. The method does not need to depend on traditional photoetching and etching steps, non-target area deposition is avoided, the technological process is simplified, the deposition precision and the critical dimension control capability are improved, and the method has the dual control effects of precise directional etching and selective deposition.

The invention relates to a preparation method of heterostructure porous carbon, which comprises the following steps: (S1) dipping a porous carbon precursor in a solution of a graphitization catalyst, and after dipping, carrying out solid-liquid separation and drying to obtain solid powder; carrying out heat treatment on the solid powder in an inert atmosphere at 800-1100 DEG C to obtain surface-graphitized heterostructure carbon; (S2) chemically activating the heterostructure carbon by using a strong alkali activator to obtain a heterostructure porous carbon intermediate; and (S3) physically activating the heterostructure porous carbon intermediate by using a physical activator to obtain the heterostructure porous carbon. According to the method, the porous carbon precursor is firstly subjected to surface graphitization, and then activated by the strong alkali activating agent to open pores and activated by the physical activating agent to expand pores, so that the heterostructure porous carbon with a graphitized surface and high internal porosity and high activity is prepared, selective deposition is realized during vapor phase silicon deposition, and the problem of floating silicon is fundamentally solved; therefore, the electrochemical performance is excellent.

The invention relates to a novel silicon-carbon material and a preparation method and application thereof, the silicon-carbon material comprises a graphite substrate, a silicon layer coating the outer surface of the graphite substrate and a silicon carbide layer coating the outer surface of the silicon layer, and a graphite-silicon-silicon carbide three-layer composite structure is formed; wherein the silicon layer and the silicon carbide layer are formed by one-time continuous deposition through a chemical vapor deposition process; the silicon carbon material is applied to a negative electrode material of a lithium ion battery. According to the novel silicon-carbon material as well as the preparation method and the application thereof, a single chemical vapor deposition process is adopted, and selective deposition of a silicon material and a silicon carbide material is realized by accurately regulating and controlling the hydrogen content in a deposition atmosphere on the premise of not changing equipment and raw materials; according to the method, the novel silicon carbon material with the SiC coated silicon structure (SiC coated Si / G) is successfully prepared.

Methods and apparatus for selectively depositing a titanium material layer atop a substrate having a silicon surface and a dielectric surface are disclosed. In embodiments an apparatus is configured for forming a remote plasma reaction between titanium tetrachloride (TiCl4), hydrogen (H2) and argon (Ar) in a region between a lid heater and a showerhead of a process chamber at a first temperature of 200 to 800 degrees C.; and flowing reaction products into the process chamber to selectively form a titanium material layer upon the silicon surface of the substrate.

The invention relates to a selective deposition method and deposition equipment of a metal molybdenum film. The method comprises the following steps: a treatment piece is provided with an exposed active surface and an inert surface, and a deposition selection ratio exists between the active surface and the inert surface; the treated part is placed in a reaction chamber for multiple deposition treatment steps, and the deposition treatment steps comprise the steps that carrier gas carries a molybdenum halide precursor containing no oxygen element to enter the reaction chamber, and the carrier gas and the active surface are adsorbed; after the molybdenum halide precursor and the active surface are adsorbed, carrying out first purging treatment on the treated part; after carrying out the first purging treatment, introducing a reductive co-reactant into the reaction chamber, and reducing the molybdenum halide precursor adsorbed on the active surface into a metal molybdenum layer; after the metal molybdenum layer is reduced, carrying out second purging treatment on the reaction chamber and the treatment piece; and after the multiple deposition treatment steps are carried out, the multiple metal molybdenum layers formed in the multiple deposition treatment steps are used as metal molybdenum films. And the conductivity and the forming quality of the metal molybdenum film are improved.

Methods of using high-purity alkynes substantially free of residual alkyl halides, water and / or carboxylic acids and their use (e.g., in formulations) for enhanced passivation of metallic substrates.

Provided are methods for low temperature thermal deposition of silicon-containing films. The methods provide selective deposition on a variety of substrates with high deposition rates and short cycle times.

Area selective deposition of aluminum-based films using alkyl aluminum amidinate precursors and methods thereof are provided. Area selective deposition comprises depositing an alkyl aluminum amidinate precursor on a substrate with a first surface portion comprising a metal and a second surface portion comprising a non-metal to form an aluminum-based film on the substrate. The aluminum-based film will be located on the second surface portion of the substrate and when the aluminum-based film is located on the first surface portion, a ratio of an average thickness of the film on the first surface portion to an average thickness of the film on the second surface portion is less than 1.

The present inventive concept relates to area-selective deposition (ASD) area-selective atomic layer deposition (AS-ALD) processes, and applications thereof. Methods of selectively depositing metal oxides and metal oxynitrides, such as TiO2 and TiON, on nitride (SiN) as a growth area vs. oxide (SiO2) as a nongrowth area, and applications thereof in, for example, self-aligned block (SAB) patterning and self-aligned multiple patterning (SAMP) processes are described.

Methods of selectively depositing a passivation layer on a metal surface of a semiconductor substrate are described. Exemplary methods may include exposing the semiconductor substrate having a metal surface and a non-metal surface to a first precursor to form a first portion of the passivation layer on the metal surface, the first precursor including an isonitrile. The exemplary methods may further include exposing the semiconductor substrate comprising a metal surface and a non-metal surface to a second precursor to form the passivation layer on the metal surface. The second precursor may include an amine, an alcohol, or a thiol.

Embodiments of this disclosure relate to a method for selectively depositing polysilicon after forming a fluid polymer film to protect a substrate surface within a feature. A first silicon (Si) layer is deposited by physical vapor deposition (PVD). A fluid polymer film is formed on the first silicon (Si) layer on the bottom. A portion of the first silicon (Si) layer is selectively removed from the top surface and at least one side wall. The fluid polymer film is removed. In some embodiments, a second silicon (Si) layer is selectively deposited on the first silicon (Si) layer to fill the feature. In some embodiments, the remaining portion of the first silicon (Si) layer on the bottom is oxidized to form a first silicon oxide (SiO₂) on the bottom. x ) forms a layer, and a silicon (Si) layer or a second silicon oxide (SiO) layer x The ) layer is the first silicon oxide (SiO x It is deposited on top of layers.

A method (200) for selectively forming a low-k dielectric film (140) on an exposed dielectric position (130) in a substrate (10), the method (200) comprising: selectively depositing (210) a metal-containing film (110) on the exposed dielectric position (130) using an area selective deposition method using one or more deposition cycles; providing (220) at least one organic ligand vapor to the deposited metal-containing film (110) at least once to cause a gas phase chemical reaction, thereby obtaining a metal-organic framework (140), the metal-organic framework (140) being a low-k dielectric film (140), wherein the low-k dielectric film (140) has a gap (142) at a position where the metal-containing film is not deposited.

Described are methods of selectively depositing a cobalt or ruthenium seed layer onto a semiconductor substrate, methods of forming a conductive contact on the semiconductor substrate, and semiconductor substrates formed according to the methods.

The present application provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device adds a selective deposition process after removing the liner oxide layer by a first wet etching process in the manufacturing process of the shallow trench isolation structure, thereby forming a dielectric repair layer on the exposed surface of the formed shallow trench isolation structure by the selective deposition process, and the dielectric repair layer fills the side trench of the top edge of the shallow trench isolation structure, thereby solving the problem of weakening the isolation effect of the shallow trench isolation structure caused by the side trench formed at the top edge of the shallow trench isolation structure, and improving the electrical performance of the device. The semiconductor device of the present application can ensure the required isolation effect of the shallow trench isolation structure because the dielectric repair layer is filled in the side trench of the top edge of the shallow trench isolation structure by the selective deposition process, thereby improving the electrical performance and reliability of the device.

The present disclosure relates to methods and apparatuses for depositing metal-containing material on a substrate by a selective deposition process. The method comprises providing a substrate in a reaction chamber, providing a metal alkoxide precursor into the reaction chamber in a vapor phase; and providing a second precursor into the reaction chamber in a vapor phase to form metal-containing material on the substrate. The second precursor according to the disclosure comprises a borane compound and the substrate comprising a first surface and a second surface.

Provided is a plasma processing method and device capable of controlling the etching mask shape during a single-step process that etches a target material disposed below the etching mask. The plasma processing method includes performing selective deposition on the etching mask in separate phases, which are controlled via a periodic bias voltage signal. By tuning the bias voltage power, duration and timing, the mask height and width can be controlled and stabilized while etching on the substrate proceeds. Thus, the present method provides an etching process that allows fine control of the etching mask shape for small pattern sizes and provides high etching selectivity through deposition.

A method for selectively passivating a substrate, wherein the substrate includes at a first surface comprising a first metal and at least a second surface comprising a second metal, preferably a metal nitride, and a third surface comprising a dielectric material. The method includes the step of exposing the substrate to at least one silane wherein the silane selectively reacts with the first surface and the second surface to passivate the first surface and the second surface thereby leaving the third surface substantially unreacted.

A method of filling a via having a necking point includes performing a pre-cleaning process to remove a residue from an exposed surface of a metal layer at a bottom of the via formed within a dielectric layer and having a necking point protruding within the via and to restore an inner surface of the via; performing a selective deposition process to partially fill the via with a metal fill material from an exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on the exposed inner surface of the via; and performing a metal filling process to fill the through hole with a metal filling material.

The disclosed and claimed subject matter relates to formulations comprising a combination of (i) one or more alkynes and (ii) one or more tertiary alcohols and their use for enhancing passivation of metal substrates.

Methods of depositing a liner layer in a semiconductor device are described. In some embodiments, the method includes depositing a carbon layer including carbon on a substrate, the substrate having at least one feature including a sidewall surface and the carbon layer having a carbon surface; and selectively depositing the liner layer on the sidewall surface over the carbon surface. In other embodiments, the method includes depositing a carbon layer comprising carbon in a bottom second portion of a substrate feature selectively over a top first portion of the substrate feature, the top first portion having a sidewall surface, the carbon layer having a carbon surface; etching the carbon surface; and depositing the conformal layer on the sidewall surface of the top first portion, the conformal layer deposited on the sidewall surface selectively over the carbon surface.

Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.

A method for manufacturing a semiconductor structure includes: forming a patterned structure including an interfacial layer and two dielectric spacers, a first surface of the interfacial layer and two second surfaces of the two dielectric spacers being arranged to border a cavity, the first surface being formed with first functional groups, the two second surfaces being formed with second functional groups; selectively forming a first self-assembled monolayer on the first surface of the interfacial layer; selectively forming two dummy layers respectively on the two second surfaces of the two dielectric spacers; removing the first self-assembled monolayer to expose the first surface of the interfacial layer; selectively forming two second self-assembled monolayers respectively on the two dummy layers; and selectively forming a gate dielectric layer on the first surface of the interfacial layer.

In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region.

A patterned liquid crystal monolayer structure (100) on a patterned substrate (900) is described, wherein the patterned substrate comprises a surface region (500) grafted thereto by a liquid crystal compound (300) as a self-assembled monolayer (SAM) (200) and a surface region (400) on the patterned substrate that is not grafted thereto by the SAM. Also described are compositions of selected liquid crystals (200) having different types of polar anchoring groups in an organic spin casting solvent, and using the composition on a substrate containing both or one of a metallic surface region and a non-metallic inorganic silicon compound surface region (depending on the properties of a polar anchoring group on a liquid crystal compound) Methods of selectively depositing SAM and using the selective SAM deposition as a barrier layer to selectively deposit a metal oxide dielectric by ALD on regions that are not grafted by SAM.