178 results about "Selective deposition" patented technology

The invention relates to a preparation method of heterostructure porous carbon, which comprises the following steps: (S1) dipping a porous carbon precursor in a solution of a graphitization catalyst, and after dipping, carrying out solid-liquid separation and drying to obtain solid powder; carrying out heat treatment on the solid powder in an inert atmosphere at 800-1100 DEG C to obtain surface-graphitized heterostructure carbon; (S2) chemically activating the heterostructure carbon by using a strong alkali activator to obtain a heterostructure porous carbon intermediate; and (S3) physically activating the heterostructure porous carbon intermediate by using a physical activator to obtain the heterostructure porous carbon. According to the method, the porous carbon precursor is firstly subjected to surface graphitization, and then activated by the strong alkali activating agent to open pores and activated by the physical activating agent to expand pores, so that the heterostructure porous carbon with a graphitized surface and high internal porosity and high activity is prepared, selective deposition is realized during vapor phase silicon deposition, and the problem of floating silicon is fundamentally solved; therefore, the electrochemical performance is excellent.

The invention relates to a selective deposition method and deposition equipment of a metal molybdenum film. The method comprises the following steps: a treatment piece is provided with an exposed active surface and an inert surface, and a deposition selection ratio exists between the active surface and the inert surface; the treated part is placed in a reaction chamber for multiple deposition treatment steps, and the deposition treatment steps comprise the steps that carrier gas carries a molybdenum halide precursor containing no oxygen element to enter the reaction chamber, and the carrier gas and the active surface are adsorbed; after the molybdenum halide precursor and the active surface are adsorbed, carrying out first purging treatment on the treated part; after carrying out the first purging treatment, introducing a reductive co-reactant into the reaction chamber, and reducing the molybdenum halide precursor adsorbed on the active surface into a metal molybdenum layer; after the metal molybdenum layer is reduced, carrying out second purging treatment on the reaction chamber and the treatment piece; and after the multiple deposition treatment steps are carried out, the multiple metal molybdenum layers formed in the multiple deposition treatment steps are used as metal molybdenum films. And the conductivity and the forming quality of the metal molybdenum film are improved.

Embodiments of this disclosure relate to a method for selectively depositing polysilicon after forming a fluid polymer film to protect a substrate surface within a feature. A first silicon (Si) layer is deposited by physical vapor deposition (PVD). A fluid polymer film is formed on the first silicon (Si) layer on the bottom. A portion of the first silicon (Si) layer is selectively removed from the top surface and at least one side wall. The fluid polymer film is removed. In some embodiments, a second silicon (Si) layer is selectively deposited on the first silicon (Si) layer to fill the feature. In some embodiments, the remaining portion of the first silicon (Si) layer on the bottom is oxidized to form a first silicon oxide (SiO₂) on the bottom. x ) forms a layer, and a silicon (Si) layer or a second silicon oxide (SiO) layer x The ) layer is the first silicon oxide (SiO x It is deposited on top of layers.

The present application provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device adds a selective deposition process after removing the liner oxide layer by a first wet etching process in the manufacturing process of the shallow trench isolation structure, thereby forming a dielectric repair layer on the exposed surface of the formed shallow trench isolation structure by the selective deposition process, and the dielectric repair layer fills the side trench of the top edge of the shallow trench isolation structure, thereby solving the problem of weakening the isolation effect of the shallow trench isolation structure caused by the side trench formed at the top edge of the shallow trench isolation structure, and improving the electrical performance of the device. The semiconductor device of the present application can ensure the required isolation effect of the shallow trench isolation structure because the dielectric repair layer is filled in the side trench of the top edge of the shallow trench isolation structure by the selective deposition process, thereby improving the electrical performance and reliability of the device.

The present disclosure relates to methods and apparatuses for depositing metal-containing material on a substrate by a selective deposition process. The method comprises providing a substrate in a reaction chamber, providing a metal alkoxide precursor into the reaction chamber in a vapor phase; and providing a second precursor into the reaction chamber in a vapor phase to form metal-containing material on the substrate. The second precursor according to the disclosure comprises a borane compound and the substrate comprising a first surface and a second surface.

Provided is a plasma processing method and device capable of controlling the etching mask shape during a single-step process that etches a target material disposed below the etching mask. The plasma processing method includes performing selective deposition on the etching mask in separate phases, which are controlled via a periodic bias voltage signal. By tuning the bias voltage power, duration and timing, the mask height and width can be controlled and stabilized while etching on the substrate proceeds. Thus, the present method provides an etching process that allows fine control of the etching mask shape for small pattern sizes and provides high etching selectivity through deposition.

The disclosed and claimed subject matter relates to formulations comprising a combination of (i) one or more alkynes and (ii) one or more tertiary alcohols and their use for enhancing passivation of metal substrates.

Methods of depositing a liner layer in a semiconductor device are described. In some embodiments, the method includes depositing a carbon layer including carbon on a substrate, the substrate having at least one feature including a sidewall surface and the carbon layer having a carbon surface; and selectively depositing the liner layer on the sidewall surface over the carbon surface. In other embodiments, the method includes depositing a carbon layer comprising carbon in a bottom second portion of a substrate feature selectively over a top first portion of the substrate feature, the top first portion having a sidewall surface, the carbon layer having a carbon surface; etching the carbon surface; and depositing the conformal layer on the sidewall surface of the top first portion, the conformal layer deposited on the sidewall surface selectively over the carbon surface.

Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.

A processing method includes forming an interfacial layer on a surface of a channel comprising silicon (Si) located between a source and a drain on a semiconductor substrate including a IOW-K dielectric layer, and selectively depositing a high-K dielectric layer directly on the interfacial layer relative to the IOW-K dielectric layer by exposing the semiconductor substrate to a metal-containing precursor, a purge gas, an alcohol, and the purge gas.

The present application relates to the technical field of silver-coated copper powder, in particular to a silver-coated copper powder particle with uniform plating thickness and a preparation method thereof. The method comprises raw material pretreatment, plating solution preparation, plating, electroplating solution preparation, electroplating and post-treatment. First, the non-selective deposition characteristics of chemical plating are used to build a complete and non-porous thin silver layer on the surface of the copper powder, ensuring 100% conductive coverage. Then, the uniform conductive layer is used as a substrate to precisely thicken through a highly controllable electroplating process. The synergistic effect of electric field and fluid dynamics is used to achieve high uniformity and structural densification of the silver layer in the nanometer scale. Through the precise relay of "chemical plating bottoming" and "electroplating thickening", the inherent contradictions of traditional single methods in coverage, uniformity and plating quality are cooperatively overcome.

Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

A method provides a single-crystal diamond substrate having a growth surface. A diamond growth inhibitor (DGI) is positioned over a diamond inhibition area of the growth surface. A first diamond portion having a first dopant concentration is deposited using chemical vapor deposition over a growth area of the growth surface. The diamond growth inhibitor and non-diamond carbon thereon are removed.

A pretreatment method of facilitating deposition of a metal-containing film includes exposing a semiconductor substrate to a reducing agent and an inhibitor. Silicon-containing inhibitor and reducing agent pre-treatments may be used in conjunction with deposition of metal-containing barrier films, and optionally with post-treatments to remove the inhibitor. Selective deposition may be accomplished by utilizing a silicon-containing inhibitor having at least one Si-H group and an organic moiety.

In some embodiments, methods are provided for simultaneously and selectively depositing a first material on a first surface of a substrate and a second, different material on a second, different surface of the same substrate using the same reaction chemistries. For example, a first material may be selectively deposited on a metal surface while a second material is simultaneously and selectively deposited on an adjacent dielectric surface. The first material and the second material have different material properties, such as different etch rates.

A method for forming a doped layer is disclosed. The doped layer can be used in NMOS or silicon germanium applications. For example, a halide precursor can be used to create a doped layer in an n-type dopant application.

A method for vacuum gap formation on a dielectric substrate uses area selective deposition (ASD), such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), of a hardmask material on a substrate patterned with a self-assembled monolayer (SAM) and metal features. Due to the presence of the SAM, the hardmask material reaches, but does not touch the metal features leaving areas that will form gaps on the resultant hardmask when the SAM is removed from the substrate. Etching of the dielectric substrate forms trenches in the areas of the gaps. When a non-conformal coating is deposited on the dielectric substrate, vacuum gaps form in the trenches as the non-conformal coating enters into the trenches, but closes off at the surface of the substrate prior to the complete filling of the trench.

This invention provides a semiconductor structure and its manufacturing method. The semiconductor structure includes: a semiconductor substrate on which a gate structure with an internal top recess is formed; a bottom metal structure filling the top recess; an interlayer dielectric layer covering the semiconductor substrate and the surface of the gate structure, with a gate contact hole through which the bottom metal structure is exposed; and a contact metal layer filling the gate contact hole, with its outer sidewalls directly and physically bonded to the inner sidewalls of the interlayer dielectric layer. The manufacturing method includes forming a recess on top of the gate and filling it with the bottom metal structure, followed by forming the interlayer dielectric layer and the contact hole, and finally growing the contact metal layer from bottom to top using a selective deposition process. This invention eliminates the high-resistivity adhesive layer and barrier layer within the contact hole, increases the filling volume of the low-resistivity metal, significantly reduces the gate contact resistance, and improves device performance.

The present application relates to a kind of for CO2 hydrogenation methanol hydrophobic core-shell catalyst and its preparation method and application, belong to catalyst preparation technical field.Zirconium-based metal organic framework UiO-66 is core body, outer layer constructs hydrophobic mesoporous silica shell layer to form core-shell structure carrier.The carrier is pre-wetted with solvent before metal introduction, and copper, zinc nitrate precursor is introduced under the condition, and its wetting, penetration and migration process in channel are controlled, so that it can penetrate hydrophobic mesoporous shell layer and transport to core-shell interface and UiO-66 core surface.Subsequently, by adjusting metal deposition kinetics, copper zinc species is selectively deposited and forms active component enrichment at interface.Preferably, by controlling metal loading process, copper zinc active component is enriched and controllably distributed in hydrophobic core-shell structure, so as to improve the stability and catalytic performance of catalyst in CO2 hydrogenation methanol reaction.

A method for selectively passivating the surface of a substrate, wherein the substrate surface comprises at least one first surface comprising silicon nitride and at least one second surface comprising a material other than silicon nitride. The method includes the step of exposing the surface to at least one organic halide which selectively reacts with silicon nitride to passivate the first surface, thereby leaving the second surface substantially unreacted.

A method of selectively depositing silicon oxide on a substrate, a method of fabricating a semiconductor device, and a semiconductor device are provided. The method includes: providing a substrate that includes a first surface including silicon oxide and a second surface including silicon nitride in a deposition chamber; selectively depositing a metal oxide precursor on the first surface of the substrate; treating the substrate with an oxygen plasma; and treating the substrate with a silicon oxide precursor.

There is provided a substrate processing method. The method includes providing a substrate having a first surface area and a second surface area having a different surface state than that of the first surface area, exposing the substrate to a substrate surface treatment composition containing a deposition inhibitor, and exposing the substrate to a post-treatment composition containing HF.

Systems and methods of selectively depositing metal oxide on an exposed metal surface relative to a dielectric material on a substrate by pre-treatment with a hydroxy species-generating plasma prior to inhibition of the metal surface with an inhibitor, and subsequent metal oxide deposition on the dielectric material are disclosed. Exemplary inhibitors include low vapor pressure inhibitors. Exemplary systems include heated ampoules and gas lines for delivering inhibitors or other processing chemicals.

A method is disclosed for the selective formation of silicon-containing films on various substrates, comprising the use of a precursor containing at least one oxygen atom and at least one silicon-nitrogen bond, and a non-oxidizing plasma.

The invention provides a method for preparing a transparent antimony-based chalcogenide film and a photoelectric detector through selective deposition. The transparent photoelectric detector structure provided by the invention comprises a transparent glass substrate, a patterned substrate, a light absorption layer, a wide-band-gap oxide covering layer and a transparent conductive electrode. The transparent light absorption layer is an antimony-based chalcogenide film and is selectively deposited on the patterned substrate. The antimony-based chalcogenide film has different growth orientations and adhesion coefficients on different substrates, and regional selective deposition of the antimony-based chalcogenide film on the patterned substrate can be realized by regulating and controlling the temperature of the substrate. The method provided by the invention breaks through the limitation of the existing transparent photoelectric detector material, and avoids the pattern edge interface damage caused by the traditional patterning methods, such as a stripping method, an etching method and a laser ablation process. The prepared transparent photoelectric detector has the advantages of being simple in preparation, accurate in transparency regulation and control, wide in spectral response in the range of 405-980 nm and the like.

The invention relates to a patterning method for a semiconductor process. The method comprises the following steps of: (1) forming a carbonyl-containing photoresist layer on a substrate material; (2) patterning the photoresist layer through a photoetching technology; (3) introducing a carboxylic acid molecule source into the reaction cavity at the first pulse time; (4) purging the reaction cavity; (5) introducing an aluminum source into the reaction cavity at a second pulse time after the first pulse time; and (6) purging the reaction cavity, and selectively depositing an aluminum-based metal organic and inorganic compound on the carbonyl-containing photoresist layer by executing the steps (1) to (6).

The present invention relates to a UV-curing nanoimprint-based selective deposition process method for improving the metal transfer rate on a polymer pattern, wherein a chemical bond is formed between a UV-curing resin and a metal thin film using metal halogenation to efficiently perform selective deposition of a metal on a polymer structure. The method comprises the steps of: manufacturing an intaglio mold for fabricating a plasmonic device having a positive pattern; depositing a metal thin film on the mold; applying a chemical reaction control material on the metal thin film; supplying light energy greater than the atomic bond-dissociation energy to the chemical reaction control material through a UV exposure process; removing the metal thin film; and performing a UV-curing imprint for the formation of a polymer nano pattern and the selective deposition of a metal.

The invention relates to a method for selectively passivating a surface of a substrate, wherein the surface of the substrate comprises at least one first surface comprising a dielectric and at least one second surface comprising another material. The method comprises the step of exposing the first and second surfaces to at least one organoaminopolysiloxane or organoaminopolysilazane, wherein the organoaminopolysiloxane or organoaminopolysilazane selectively reacts with the dielectric to passivate the first surface while leaving the second surface substantially unreacted.

A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.