300 results about "Selective deposition" patented technology

Provided are methods of filling patterned features with molybdenum (Mo). The methods involve selective deposition of Mo films on bottom metal-containing surfaces of a feature including dielectric sidewalls. The selective growth of Mo on the bottom surface allows bottom-up growth and high quality, void-free fill. Also provided are related apparatus.

The invention provides a method for depositing silicon nitride on the side wall of a groove structure, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps of: depositing carbon-containing barrier layers on the top, the side wall and the bottom of a groove structure by utilizing inductively coupled plasma enhanced chemical vapor deposition, and then carrying out directional etching on the side wall of the groove by utilizing ammonia plasma bombardment, so that the carbon-containing barrier layers on the side wall of the groove are accurately removed, and the barrier layers in the top and bottom areas are kept complete; and finally, using inductively coupled plasma to enhance atomic layer deposition, and selectively depositing a silicon nitride film in the side wall area of the groove. The method does not need to depend on traditional photoetching and etching steps, non-target area deposition is avoided, the technological process is simplified, the deposition precision and the critical dimension control capability are improved, and the method has the dual control effects of precise directional etching and selective deposition.

The invention relates to a preparation method of heterostructure porous carbon, which comprises the following steps: (S1) dipping a porous carbon precursor in a solution of a graphitization catalyst, and after dipping, carrying out solid-liquid separation and drying to obtain solid powder; carrying out heat treatment on the solid powder in an inert atmosphere at 800-1100 DEG C to obtain surface-graphitized heterostructure carbon; (S2) chemically activating the heterostructure carbon by using a strong alkali activator to obtain a heterostructure porous carbon intermediate; and (S3) physically activating the heterostructure porous carbon intermediate by using a physical activator to obtain the heterostructure porous carbon. According to the method, the porous carbon precursor is firstly subjected to surface graphitization, and then activated by the strong alkali activating agent to open pores and activated by the physical activating agent to expand pores, so that the heterostructure porous carbon with a graphitized surface and high internal porosity and high activity is prepared, selective deposition is realized during vapor phase silicon deposition, and the problem of floating silicon is fundamentally solved; therefore, the electrochemical performance is excellent.

The invention relates to a novel silicon-carbon material and a preparation method and application thereof, the silicon-carbon material comprises a graphite substrate, a silicon layer coating the outer surface of the graphite substrate and a silicon carbide layer coating the outer surface of the silicon layer, and a graphite-silicon-silicon carbide three-layer composite structure is formed; wherein the silicon layer and the silicon carbide layer are formed by one-time continuous deposition through a chemical vapor deposition process; the silicon carbon material is applied to a negative electrode material of a lithium ion battery. According to the novel silicon-carbon material as well as the preparation method and the application thereof, a single chemical vapor deposition process is adopted, and selective deposition of a silicon material and a silicon carbide material is realized by accurately regulating and controlling the hydrogen content in a deposition atmosphere on the premise of not changing equipment and raw materials; according to the method, the novel silicon carbon material with the SiC coated silicon structure (SiC coated Si / G) is successfully prepared.

Methods and apparatus for selectively depositing a titanium material layer atop a substrate having a silicon surface and a dielectric surface are disclosed. In embodiments an apparatus is configured for forming a remote plasma reaction between titanium tetrachloride (TiCl4), hydrogen (H2) and argon (Ar) in a region between a lid heater and a showerhead of a process chamber at a first temperature of 200 to 800 degrees C.; and flowing reaction products into the process chamber to selectively form a titanium material layer upon the silicon surface of the substrate.

The invention relates to a selective deposition method and deposition equipment of a metal molybdenum film. The method comprises the following steps: a treatment piece is provided with an exposed active surface and an inert surface, and a deposition selection ratio exists between the active surface and the inert surface; the treated part is placed in a reaction chamber for multiple deposition treatment steps, and the deposition treatment steps comprise the steps that carrier gas carries a molybdenum halide precursor containing no oxygen element to enter the reaction chamber, and the carrier gas and the active surface are adsorbed; after the molybdenum halide precursor and the active surface are adsorbed, carrying out first purging treatment on the treated part; after carrying out the first purging treatment, introducing a reductive co-reactant into the reaction chamber, and reducing the molybdenum halide precursor adsorbed on the active surface into a metal molybdenum layer; after the metal molybdenum layer is reduced, carrying out second purging treatment on the reaction chamber and the treatment piece; and after the multiple deposition treatment steps are carried out, the multiple metal molybdenum layers formed in the multiple deposition treatment steps are used as metal molybdenum films. And the conductivity and the forming quality of the metal molybdenum film are improved.

Methods of using high-purity alkynes substantially free of residual alkyl halides, water and / or carboxylic acids and their use (e.g., in formulations) for enhanced passivation of metallic substrates.

Provided are methods for low temperature thermal deposition of silicon-containing films. The methods provide selective deposition on a variety of substrates with high deposition rates and short cycle times.

Methods of selectively depositing a passivation layer on a metal surface of a semiconductor substrate are described. Exemplary methods may include exposing the semiconductor substrate having a metal surface and a non-metal surface to a first precursor to form a first portion of the passivation layer on the metal surface, the first precursor including an isonitrile. The exemplary methods may further include exposing the semiconductor substrate comprising a metal surface and a non-metal surface to a second precursor to form the passivation layer on the metal surface. The second precursor may include an amine, an alcohol, or a thiol.

Embodiments of this disclosure relate to a method for selectively depositing polysilicon after forming a fluid polymer film to protect a substrate surface within a feature. A first silicon (Si) layer is deposited by physical vapor deposition (PVD). A fluid polymer film is formed on the first silicon (Si) layer on the bottom. A portion of the first silicon (Si) layer is selectively removed from the top surface and at least one side wall. The fluid polymer film is removed. In some embodiments, a second silicon (Si) layer is selectively deposited on the first silicon (Si) layer to fill the feature. In some embodiments, the remaining portion of the first silicon (Si) layer on the bottom is oxidized to form a first silicon oxide (SiO₂) on the bottom. x ) forms a layer, and a silicon (Si) layer or a second silicon oxide (SiO) layer x The ) layer is the first silicon oxide (SiO x It is deposited on top of layers.

Described are methods of selectively depositing a cobalt or ruthenium seed layer onto a semiconductor substrate, methods of forming a conductive contact on the semiconductor substrate, and semiconductor substrates formed according to the methods.

The present application provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device adds a selective deposition process after removing the liner oxide layer by a first wet etching process in the manufacturing process of the shallow trench isolation structure, thereby forming a dielectric repair layer on the exposed surface of the formed shallow trench isolation structure by the selective deposition process, and the dielectric repair layer fills the side trench of the top edge of the shallow trench isolation structure, thereby solving the problem of weakening the isolation effect of the shallow trench isolation structure caused by the side trench formed at the top edge of the shallow trench isolation structure, and improving the electrical performance of the device. The semiconductor device of the present application can ensure the required isolation effect of the shallow trench isolation structure because the dielectric repair layer is filled in the side trench of the top edge of the shallow trench isolation structure by the selective deposition process, thereby improving the electrical performance and reliability of the device.

The present disclosure relates to methods and apparatuses for depositing metal-containing material on a substrate by a selective deposition process. The method comprises providing a substrate in a reaction chamber, providing a metal alkoxide precursor into the reaction chamber in a vapor phase; and providing a second precursor into the reaction chamber in a vapor phase to form metal-containing material on the substrate. The second precursor according to the disclosure comprises a borane compound and the substrate comprising a first surface and a second surface.

Provided is a plasma processing method and device capable of controlling the etching mask shape during a single-step process that etches a target material disposed below the etching mask. The plasma processing method includes performing selective deposition on the etching mask in separate phases, which are controlled via a periodic bias voltage signal. By tuning the bias voltage power, duration and timing, the mask height and width can be controlled and stabilized while etching on the substrate proceeds. Thus, the present method provides an etching process that allows fine control of the etching mask shape for small pattern sizes and provides high etching selectivity through deposition.

A method of filling a via having a necking point includes performing a pre-cleaning process to remove a residue from an exposed surface of a metal layer at a bottom of the via formed within a dielectric layer and having a necking point protruding within the via and to restore an inner surface of the via; performing a selective deposition process to partially fill the via with a metal fill material from an exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on the exposed inner surface of the via; and performing a metal filling process to fill the through hole with a metal filling material.

The disclosed and claimed subject matter relates to formulations comprising a combination of (i) one or more alkynes and (ii) one or more tertiary alcohols and their use for enhancing passivation of metal substrates.

Methods of depositing a liner layer in a semiconductor device are described. In some embodiments, the method includes depositing a carbon layer including carbon on a substrate, the substrate having at least one feature including a sidewall surface and the carbon layer having a carbon surface; and selectively depositing the liner layer on the sidewall surface over the carbon surface. In other embodiments, the method includes depositing a carbon layer comprising carbon in a bottom second portion of a substrate feature selectively over a top first portion of the substrate feature, the top first portion having a sidewall surface, the carbon layer having a carbon surface; etching the carbon surface; and depositing the conformal layer on the sidewall surface of the top first portion, the conformal layer deposited on the sidewall surface selectively over the carbon surface.

Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.

In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region.

A processing method includes forming an interfacial layer on a surface of a channel comprising silicon (Si) located between a source and a drain on a semiconductor substrate including a IOW-K dielectric layer, and selectively depositing a high-K dielectric layer directly on the interfacial layer relative to the IOW-K dielectric layer by exposing the semiconductor substrate to a metal-containing precursor, a purge gas, an alcohol, and the purge gas.

The present application relates to the technical field of silver-coated copper powder, in particular to a silver-coated copper powder particle with uniform plating thickness and a preparation method thereof. The method comprises raw material pretreatment, plating solution preparation, plating, electroplating solution preparation, electroplating and post-treatment. First, the non-selective deposition characteristics of chemical plating are used to build a complete and non-porous thin silver layer on the surface of the copper powder, ensuring 100% conductive coverage. Then, the uniform conductive layer is used as a substrate to precisely thicken through a highly controllable electroplating process. The synergistic effect of electric field and fluid dynamics is used to achieve high uniformity and structural densification of the silver layer in the nanometer scale. Through the precise relay of "chemical plating bottoming" and "electroplating thickening", the inherent contradictions of traditional single methods in coverage, uniformity and plating quality are cooperatively overcome.

Methods of depositing iridium-containing films are described. Methods of manufacturing interconnect structures as part of a microelectronic device fabrication process are also described. The methods include forming a dielectric layer including at least one feature defining a gap having sidewalls and a bottom on a substrate. The methods further include forming a blocking layer on the bottom by exposing the substrate to a blocking compound; selectively depositing an iridium-containing film on the sidewalls; removing the blocking layer; and performing a gap fill process to fill the gap with a gapfill material.

Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

A method provides a single-crystal diamond substrate having a growth surface. A diamond growth inhibitor (DGI) is positioned over a diamond inhibition area of the growth surface. A first diamond portion having a first dopant concentration is deposited using chemical vapor deposition over a growth area of the growth surface. The diamond growth inhibitor and non-diamond carbon thereon are removed.

A pretreatment method of facilitating deposition of a metal-containing film includes exposing a semiconductor substrate to a reducing agent and an inhibitor. Silicon-containing inhibitor and reducing agent pre-treatments may be used in conjunction with deposition of metal-containing barrier films, and optionally with post-treatments to remove the inhibitor. Selective deposition may be accomplished by utilizing a silicon-containing inhibitor having at least one Si-H group and an organic moiety.

A method of forming a device includes forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the gap including sidewalls and a bottom. The method includes selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM comprises a hydrocarbon having the formula H-C = C-R, where R is an alkyl linear or aryl group comprising from 1 to 20 carbon atoms, or having the formula R 'C = CR ", where R' and R" independently comprise an alkyl linear or aryl group comprising from 1 to 20 carbon atoms. A barrier layer is formed on the SAM and then a metal liner is selectively deposited on the barrier layer. After selectively depositing a metal liner on the barrier layer, the SAM is removed.

In some embodiments, methods are provided for simultaneously and selectively depositing a first material on a first surface of a substrate and a second, different material on a second, different surface of the same substrate using the same reaction chemistries. For example, a first material may be selectively deposited on a metal surface while a second material is simultaneously and selectively deposited on an adjacent dielectric surface. The first material and the second material have different material properties, such as different etch rates.

A method for forming a doped layer is disclosed. The doped layer can be used in NMOS or silicon germanium applications. For example, a halide precursor can be used to create a doped layer in an n-type dopant application.

A method for vacuum gap formation on a dielectric substrate uses area selective deposition (ASD), such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), of a hardmask material on a substrate patterned with a self-assembled monolayer (SAM) and metal features. Due to the presence of the SAM, the hardmask material reaches, but does not touch the metal features leaving areas that will form gaps on the resultant hardmask when the SAM is removed from the substrate. Etching of the dielectric substrate forms trenches in the areas of the gaps. When a non-conformal coating is deposited on the dielectric substrate, vacuum gaps form in the trenches as the non-conformal coating enters into the trenches, but closes off at the surface of the substrate prior to the complete filling of the trench.