59 results about "Copper interconnect" patented technology

The invention discloses a method for controlling CMP (chemical mechanical polishing) dish-shaped pits, corrosion pits and interface corrosion of ruthenium barrier layer copper wiring, which is suitable for a manufacturing process of integrated circuits of 14 nanometers and below. According to the method, a specifically synthesized TTAK corrosion inhibitor is introduced into a polishing solution system, the oriented adsorption characteristic of the molecular structure of the TTAK corrosion inhibitor is utilized, the corrosion reaction of copper is selectively inhibited, meanwhile, the normal material removal efficiency of a ruthenium barrier layer and a TEOS dielectric layer is maintained, and cooperative regulation and control of the removal rate of the Cu / Ru / TEOS material are achieved. By means of the method, dished pits, corrosion pits and Fang type interface defects generated in the fine polishing and barrier layer polishing process can be effectively eliminated, and copper / ruthenium interface corrosion is improved. According to the method, the global planarization quality of the copper interconnection ruthenium barrier layer is remarkably improved, the interface bonding strength and the electrical reliability of an interconnection circuit are enhanced, and an effective solution is provided for performance optimization of an advanced process integrated circuit device.

The invention discloses a method for reducing back-end interconnection contact resistance, and relates to the technical field of semiconductor manufacturing. The method comprises the step of performing surface treatment on a substrate after an opening for exposing a lower-layer copper interconnection structure is formed. The surface treatment adopts a treatment gas containing a reducing gas (such as hydrogen), and copper oxide on the surface of the lower-layer copper interconnection structure is reduced into metal copper in a plasma environment. According to the method, the reducing gas is introduced for etching post-treatment, so that the interface oxide layer can be efficiently and mildly removed, the contact resistance between the through hole and the lower-layer copper interconnection structure is remarkably reduced, and the device cannot be damaged. The method is wide in process window and good in stability, RC delay of an integrated circuit is reduced, and the overall performance of a chip is improved.

This invention relates to the field of electroplating solution analysis technology, and in particular to a rapid analytical method for polyethylene glycol (PEG) additives in copper electrodeposition solutions. The method involves protonated PEG forming a macromolecular complex colloid with phosphomolybdate under acidic conditions of pH 1.0–2.0. This colloid exhibits maximum absorption at 372 nm, and the absorbance value is directly proportional to the PEG concentration in the formed complex colloid. This allows for quantitative analysis of PEG in the copper electrodeposition solution. Because the phosphomolybdate-PEG complex colloid selected in this invention has excellent selectivity, and no sample pretreatment is required, this invention offers advantages such as ease of operation, speed, high sensitivity, and good selectivity. It is particularly suitable for intermediate control analysis in production environments, such as for electroplated copper interconnects in chips and printed circuit boards, as well as electrolytic copper foil for negative electrode current collectors and copper-clad laminates in energy storage batteries.

The utility model discloses a conductive performance testing device for a copper interconnection nano film, which comprises a four-probe tester, a control panel is arranged at the front end of the four-probe tester, a testing mechanism is arranged at the top of the four-probe tester, a connecting mechanism is arranged on the testing mechanism, the testing mechanism comprises a testing table, and a testing device is arranged on the testing table. One side of the top of the detection table is fixedly connected with a vertical frame, and the vertical frame is fixedly connected with an electric push rod. According to the conductive performance test equipment for the copper-interconnected nano-film, the nano-film is placed on the placement table, an electromagnet generates attractive force on a magnet block after being electrified, so that a movable base can synchronously move with a second sliding seat, and then the nano-film is moved by a first motor and a second motor; the conductive performance of multiple positions on the nano-film can be tested, the nano-film can be conveniently replaced, the test range is expanded, and the test effect is effectively improved.

Additive manufacturing techniques are described. In one example, a method includes printing, using a printable copper ink, a layer of copper onto a substrate, applying a photonic sintering process to cure the layer of copper to produce a cured layer of copper, repeating, in an alternating manner, the printing and the photonic sintering process to individually print and cure a plurality of additional layers of copper over the cured layer of copper to produce a copper pillar having a selected height, and after forming the copper pillar to the selected height, depositing, onto the substrate, a dielectric material at least partially surrounding the copper pillar.

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a device based on hybrid bonding and a bonding method thereof. Comprising two substrates, namely a first substrate and a second substrate, a plurality of copper interconnection discs, namely a first copper interconnection disc and a second copper interconnection disc, are arranged on the end faces, close to each other, of the first substrate and the second substrate, and the space between the corresponding second copper interconnection disc and the first copper interconnection disc is filled with photosensitive conductive adhesive; a copper-photosensitive conductive adhesive-copper bonding interconnection structure is formed, so that the first substrate and the second substrate are electrically connected; and the dielectric layer is filled between the first substrate and the second substrate to form a protective barrier, and the mixed bonding between the first substrate and the second substrate is promoted by virtue of the erodibility of the dielectric layer. The bonding firmness between the two copper interconnection discs is remarkably enhanced by utilizing the viscosity and the conductivity of the photosensitive conductive disc, and the stability of circuit conduction interconnection between the two substrates is ensured.

The invention provides a chip copper interconnection layer deplating recovery method and system, electronic equipment and a medium, and the method comprises the steps: recognizing an active reaction boundary dissolved by a copper interconnection layer in real time, and dynamically dividing a microelectrode array into a core deplating region, an edge inhibition region and an isolation region according to the active reaction boundary; a forward dissolving electric field is applied to the core deplating area to efficiently remove a copper material, meanwhile, a reverse restraining electric field is applied to the edge restraining area to actively restrain transverse etching of the side wall, the isolation area avoids interference on a non-target area through a passive or high-resistance state, and therefore localized precise regulation and control of the deplating process are achieved. According to the invention, the uncontrollable erosion of the side wall of the micron-sized copper circuit is obviously reduced.

In one example, an integrated circuit (IC) (100) comprises a dielectric layer (122) over a semiconductor substrate (102), a resistive layer (124) over the dielectric layer (122), a metal interconnect trace (138A) over a header end (123A) of the resistive layer (124), a via (134A) extending from the metallic interconnect trace (138A) toward the resistive layer (124), and a metallic barrier layer (130) between the via (134A) and the resistive layer (124).

This invention relates to the field of integrated circuit packaging technology, and in particular to a system-in-package (SIP) method and packaging device. The SIP method involves first preparing a substrate carrier plate that includes both a base carrier plate and a temporary bonding material layer; then, batch exposure, development, and etching of copper plates, filling circuit gaps with passivation dry film to form a motherboard, and cutting independent thick copper interconnect units adapted to the first type of chip to be packaged; subsequently, the chip and the unit are mounted on the carrier plate, and a second type of chip is soldered using metal bumps, making the unit a customized thick copper redistribution layer; finally, through molding, disassembling the carrier plate, creating passivation layer openings and metal circuit terminals, the SIP is completed. By reconfiguring the process route to achieve pre-integration of thick copper units, the thick copper electroplating process on the front side of the chip is avoided, eliminating wafer warpage problems from the source, significantly simplifying the packaging process, and completely eliminating interface risks caused by adhesive-mediated connections, thus combining high reliability with design flexibility.

The present application discloses an integrated circuit structure and a method for fabricating the same. The integrated circuit structure includes a substrate having a circuit region formed thereon, a copper interconnect structure formed on the substrate, the copper interconnect structure including an uppermost copper layer covered by a dielectric layer, an aluminum pad layer formed on the dielectric layer, and a metal layer formed on the circuit region and between the uppermost copper layer and the aluminum pad layer.

The application provides a copper interconnection layer and a damascene process method of the copper interconnection layer. The side wall and bottom of a via and a trench for forming a copper interconnection line are formed with a barrier layer, which comprises a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer can be a crystal Co layer, a crystal Ru layer or a crystal Os layer. The metal crystal adhesion layer can enhance the adhesion with Cu, effectively inhibit the diffusion of Cu into a dielectric layer and be beneficial to improving the electron migration performance of Cu. The formation of the metal crystal adhesion layer can effectively reduce the total thickness of the barrier layer and a first barrier layer and effectively reduce the resistance of the via. The graphene layer is an amorphous carbon / graphene composite layer. Due to the formation of the graphene layer, the copper interconnection layer has a lower resistivity. The formation of the graphene layer can also effectively reduce the total thickness of the barrier layer or the barrier layer and the first barrier layer and effectively reduce the resistance of the via.

The invention relates to the technical field of semiconductor manufacturing and electronic materials, in particular to a copper interconnection electroplating solution and a copper interconnection electroplating method.The copper interconnection electroplating solution comprises an antioxidant, and the antioxidant comprises a benzotriazole amido derivative. According to the copper interconnection electroplating liquid, the number of nano holes generated in the electroplating process can be reduced, the reliability and the process yield of a plating layer are remarkably improved, and the copper interconnection electroplating liquid is suitable for the requirement of an advanced manufacturing process of a high-density integrated circuit; when the copper interconnection electroplating liquid is used for copper interconnection electroplating, existing hardware equipment does not need to be transformed on a large scale. The copper interconnection electroplating liquid contains the antioxidant, and the antioxidant can well cooperate with Cl <->, the inhibitor and other components in the system to jointly optimize the stability of the whole electroplating liquid system.

A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.

The invention relates to a copper pad metallization system and a related method. A particular implementation of a method of forming an interconnect may include forming a grain layer (10) over a plurality of pads (6); patterning the photoresist layer (12) having a plurality of openings (14) exposing the plurality of pads (6); forming a plurality of copper interconnectors (18) by electroplating each of the plurality of copper interconnectors (18) into each of the plurality of openings (14); removing the photoresist layer (12); etching the grain layer (10); forming one or more layers (24) on the plurality of copper interconnectors (18); and patterning the polyimide layer (26) over the plurality of copper interconnectors (18) to form at least one opening (28) over at least one of the plurality of copper interconnectors (18).

The invention discloses a method for synthesizing intercalated doped graphene at low temperature, which comprises the following steps: S1, providing a semiconductor substrate, forming a copper interconnection structure on the semiconductor substrate, and exposing the surface of the copper interconnection structure and the surface of an insulating medium surrounding the copper interconnection structure together; s2, annealing pretreatment is carried out on the semiconductor substrate, an oxide layer on the surface of the semiconductor substrate is removed, and a catalytic surface is exposed; s3, benzene / acetylene is used as mixed carbon source gas, Ar / H2 is used as auxiliary gas, reaction is carried out at the temperature of 300-400 DEG C, and a plurality of graphene layers selectively grow on the surface of the copper interconnection structure; and S4, performing post-intercalation doping treatment on the graphene layer to form an intercalation doping structure. Graphene selectively grows on the copper interconnection surface at low temperature through the benzene / acetylene mixed carbon source, photoetching or transferring is not needed, and damage to the device structure is avoided; the efficient and stable doping of the multilayer graphene is realized through the gas phase intercalation, the conductivity of the graphene layer is improved, and the reliability of the device is improved.

The invention provides a repair process for a selective atomic layer. The repair process comprises the following steps: placing a semiconductor structure in an ALD reaction cavity, firstly introducing a first precursor to perform selective adsorption on the surface of a metal interconnection line, then introducing a second precursor to react with the first precursor adsorbed on the surface of the metal interconnection line, and repeating the steps of selective adsorption and reaction to obtain a metal atomic layer; wherein the first precursor is selected from bis (hexafluoroacetylacetone) copper (II) or (trimethylsilane methyl) copper (I); the second precursor is a reducing gas. According to the method, the specific chemical reaction between the specific precursor substance and the copper metal surface is adopted, high selectivity in the repairing process is achieved, then through the reduction reaction, the deposition reaction only occurs on the exposed surface of the copper interconnection line and in pores and gaps in the copper interconnection line and does not deposit on the dielectric layer, and then precise repairing is achieved.

This invention proposes a semiconductor structure and its fabrication method, belonging to the field of semiconductor technology. The semiconductor structure includes at least: a substrate; a groove recessed from the surface of the substrate into the substrate; a barrier layer disposed on the surface of the substrate and within the groove; a first doped layer disposed on the barrier layer; a second doped layer disposed on the first doped layer; and a conductive layer disposed on the second doped layer. The semiconductor structure and its fabrication method proposed in this invention can effectively reduce void defects in copper interconnect structures while effectively preventing electromigration, thereby improving the reliability and yield of the semiconductor structure.

The application belongs to the field of integrated circuit manufacturing, and particularly relates to a single-layer diffusion barrier layer with low resistivity and high failure temperature for copper interconnection. The diffusion barrier layer is a copper interconnection diffusion barrier layer, which is located between copper and a silicon substrate, and contains M and N elements, wherein M is selected from one of Zr and Hf. The copper interconnection diffusion barrier layer is prepared by a magnetron sputtering process, and the nitrogen content accounts for 18% to 25% of the working gas content during the preparation of the copper interconnection diffusion barrier layer by magnetron sputtering. The single-layer nitride diffusion barrier layer prepared by magnetron sputtering has an ultra-thin thickness, a resistivity lower than 40 micro-ohm per centimeter (even lower than 10 micro-ohm per centimeter) at 600 degrees Celsius, and a failure temperature higher than 600 degrees Celsius. The application has reasonable component design, simple and controllable process, and is convenient for industrial application.

The invention provides a method for inhibiting generation of a copper cavity defect, which comprises the following steps of: 1, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a copper interconnection metal layer in the interlayer dielectric layer; 2, forming a protective layer on the interlayer dielectric layer, wherein the pressure stress of an intermediate film layer in the protective layer is increased; and step 3, forming a groove in the protection layer, and exposing a part of the copper interconnection metal layer. The residual stress on the surface of the copper interconnection metal layer is reduced by increasing the pressure stress of the middle film layer in the protection layer, so that the generation of copper cavity defects is inhibited.

The invention provides an electroplating liquid leveling agent and application thereof. The electroplating liquid leveling agent is obtained by sequentially reacting isocyanate halide or isothiocyanate halide with aliphatic diamine and aromatic compounds. The leveling agent provided by the invention is added into an electroplating solution to be used in copper interconnection electroplating, so that the diffusion migration capability can be improved, the adsorption and desorption activity can be balanced, the generation of in-hole filling morphology defects and subsequent reliability risks are avoided, and the electroplating quality and reliability of an electroplating solution composition in hole filling and pattern co-plating are comprehensively improved; the requirements of electroplating filling and pattern co-plating of the opening structure in a certain depth-to-width ratio span range on the wafer and the substrate can be met, and the method has the industrial application advantages of being wide in adaptive scene, easy and convenient to maintain and control, low in production cost and the like; the method can be applied to the fields of integrated circuit manufacturing, integrated circuit packaging, circuit board manufacturing and photovoltaic manufacturing which relate to hole structure copper interconnection electroplating.

Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner / film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and / or zinc silicon oxide (ZnSiOx) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance / capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.

Embodiments disclosed herein include an apparatus that includes a pad, and the pad includes aluminum. In an embodiment, the liner is on a sidewall of the pad, and the liner extends beyond a surface of the pad. In an embodiment, the first layer is over the pad, and the first layer includes copper. In an embodiment, the second layer is over the first layer, and the second layer is a dielectric material. In an embodiment, a via passes through the second layer and contacts the first layer.

The invention provides the copper interconnection structure for the integrated circuit chip, which is easy to form a welding spot with good electric connection performance with a large-size metal wire. The copper interconnection structure comprises a copper surface, a metal barrier layer and a weldable metal layer. The copper interconnection structure comprises a weldable metal layer formed on the metal barrier layer, wherein the thickness of the weldable metal layer ranges from 0.03 micrometer to 0.05 micrometer.

The invention relates to an interconnect structure of an integrated circuit. A method of manufacturing an interconnect structure of an integrated circuit, which interconnect structure is intended to be encapsulated in an encapsulation resin in contact with a first surface of a protective layer. The protective layer is located on a first surface of the interconnect structure. The interconnect structure comprises a copper interconnect element, which extends at least partially through an insulating layer and is flush with the first surface of the interconnect structure. The manufacturing method comprises a structuring step of the protective layer or a step of forming the protective layer by structuring. The structuring step or the forming step is adapted to structure the first surface of the protective layer in the form of ridges and grooves alternating with each other.

The invention discloses a method for improving copper interconnection defects in a semiconductor device and improving electromigration performance, and belongs to the technical field of semiconductor manufacturing. According to the method, in an integrated etching process, firstly, when a dielectric layer exposing a copper layer is etched, initial damage to the copper surface is reduced by reducing ion bombardment energy and reducing introduction of oxygen-containing gas; and then, in the post-etching treatment, a step of carrying out chemical repair on the copper surface by using reducing gases such as hydrogen and the like is added, so that possibly generated copper oxide is reduced into metal copper. According to the method, through a dual strategy of combining'damage reduction 'and'active repair', interface defects such as copper deficiency caused by copper surface oxidation are effectively inhibited, and the interface quality is remarkably improved, so that the electromigration resistance and long-term reliability of a device are greatly improved.

The application discloses a PVD equipment capable of realizing Cu in-situ reflow and redeposition and a control method thereof. The PVD equipment comprises a first transfer cavity and a second transfer cavity. The two sides of the first transfer cavity are sequentially arranged with an integrated cavity, a pre-cleaning cavity, a reprocessing process cavity and an in-situ reflow composite processing cavity. The periphery of the second transfer cavity is provided with a plurality of process cavities. The integrated cavity is provided with a first heating module, a cavity water cooling channel, a wafer support frame and a lifting and rotating mechanism. The integrated cavity is provided with three wafer placing positions. The lifting and rotating mechanism can move the wafer support frame between the three wafer placing positions. The in-situ reflow composite processing cavity comprises a cooling base plate, a supporting mechanism and a second heating module. The supporting mechanism is used for supporting the wafer and has rotating and up-down moving functions. The supporting mechanism is provided with three wafer placing positions in the up-down moving direction. The application can solve the problems of micro-hole and joint defects in the deposition of copper interconnection thin film in a high aspect ratio structure, uneven sidewall coverage and the like.

Copper-attached glass modules on glass panels are provided. An apparatus includes one or more dies, an interposer formed of a first material, the interposer coupled to the one or more silicon dies, the interposer including an interconnect layer formed on a side of the interposer, wherein the interconnect layer includes a plurality of copper interconnects, and a substrate including a top layer, a glass core, and a bottom layer, wherein the interconnect layer of the interposer is copper bonded with the top layer of the substrate.

The invention discloses a Damascus film layer structure and a preparation method thereof, and belongs to the technical field of semiconductor manufacturing. The method adopts a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and Si3N4 is deposited on a copper substrate at 350 DEG C to serve as SiO2 is deposited on the stop layer at the temperature of 180 DEG C to serve as a graphical layer; siOxNy is deposited at the temperature of 400 DEG C to serve as a dielectric anti-reflection layer. By regulating and controlling the deposition temperature difference between different layers, the SiO2 layer formed at a low temperature has relatively low density and shows a higher etching rate during etching, so that the selection ratio of photoresist to oxides is remarkably improved. The structure effectively inhibits excessive etching, realizes accurate etching termination and high-quality pattern transfer, and is suitable for high-performance copper interconnection process requirements.

The invention discloses PVD equipment capable of achieving in-situ backflow and redeposition of Cu and a control method thereof.The PVD equipment comprises a first transfer cavity and a second transfer cavity, the two sides of the first transfer cavity are each sequentially provided with an integrated cavity, a pre-cleaning cavity, a retreatment process cavity and an in-situ backflow composite treatment cavity, and the periphery of the second transfer cavity is provided with a plurality of process cavities; a first heating module, a cavity water cooling channel, a wafer supporting frame and a lifting rotating mechanism are arranged in the integrated cavity, and three wafer placing positions are arranged in the integrated cavity; the lifting rotating mechanism can drive the wafer supporting frame to move among the three wafer placing positions; the in-situ backflow composite processing cavity comprises a cooling chassis, a supporting mechanism and a second heating module, and the supporting mechanism is used for supporting a wafer, has rotating and up-and-down moving functions and is provided with three wafer placing positions in the up-and-down moving direction. According to the method, the problems of micro-hole and seam defects, non-uniform side wall coverage and the like in a copper interconnection film deposition high aspect ratio structure can be solved.