32 results about "Copper interconnect" patented technology

This invention relates to the field of electroplating solution analysis technology, and in particular to a rapid analytical method for polyethylene glycol (PEG) additives in copper electrodeposition solutions. The method involves protonated PEG forming a macromolecular complex colloid with phosphomolybdate under acidic conditions of pH 1.0–2.0. This colloid exhibits maximum absorption at 372 nm, and the absorbance value is directly proportional to the PEG concentration in the formed complex colloid. This allows for quantitative analysis of PEG in the copper electrodeposition solution. Because the phosphomolybdate-PEG complex colloid selected in this invention has excellent selectivity, and no sample pretreatment is required, this invention offers advantages such as ease of operation, speed, high sensitivity, and good selectivity. It is particularly suitable for intermediate control analysis in production environments, such as for electroplated copper interconnects in chips and printed circuit boards, as well as electrolytic copper foil for negative electrode current collectors and copper-clad laminates in energy storage batteries.

The utility model discloses a conductive performance testing device for a copper interconnection nano film, which comprises a four-probe tester, a control panel is arranged at the front end of the four-probe tester, a testing mechanism is arranged at the top of the four-probe tester, a connecting mechanism is arranged on the testing mechanism, the testing mechanism comprises a testing table, and a testing device is arranged on the testing table. One side of the top of the detection table is fixedly connected with a vertical frame, and the vertical frame is fixedly connected with an electric push rod. According to the conductive performance test equipment for the copper-interconnected nano-film, the nano-film is placed on the placement table, an electromagnet generates attractive force on a magnet block after being electrified, so that a movable base can synchronously move with a second sliding seat, and then the nano-film is moved by a first motor and a second motor; the conductive performance of multiple positions on the nano-film can be tested, the nano-film can be conveniently replaced, the test range is expanded, and the test effect is effectively improved.

Additive manufacturing techniques are described. In one example, a method includes printing, using a printable copper ink, a layer of copper onto a substrate, applying a photonic sintering process to cure the layer of copper to produce a cured layer of copper, repeating, in an alternating manner, the printing and the photonic sintering process to individually print and cure a plurality of additional layers of copper over the cured layer of copper to produce a copper pillar having a selected height, and after forming the copper pillar to the selected height, depositing, onto the substrate, a dielectric material at least partially surrounding the copper pillar.

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a device based on hybrid bonding and a bonding method thereof. Comprising two substrates, namely a first substrate and a second substrate, a plurality of copper interconnection discs, namely a first copper interconnection disc and a second copper interconnection disc, are arranged on the end faces, close to each other, of the first substrate and the second substrate, and the space between the corresponding second copper interconnection disc and the first copper interconnection disc is filled with photosensitive conductive adhesive; a copper-photosensitive conductive adhesive-copper bonding interconnection structure is formed, so that the first substrate and the second substrate are electrically connected; and the dielectric layer is filled between the first substrate and the second substrate to form a protective barrier, and the mixed bonding between the first substrate and the second substrate is promoted by virtue of the erodibility of the dielectric layer. The bonding firmness between the two copper interconnection discs is remarkably enhanced by utilizing the viscosity and the conductivity of the photosensitive conductive disc, and the stability of circuit conduction interconnection between the two substrates is ensured.

The invention provides a chip copper interconnection layer deplating recovery method and system, electronic equipment and a medium, and the method comprises the steps: recognizing an active reaction boundary dissolved by a copper interconnection layer in real time, and dynamically dividing a microelectrode array into a core deplating region, an edge inhibition region and an isolation region according to the active reaction boundary; a forward dissolving electric field is applied to the core deplating area to efficiently remove a copper material, meanwhile, a reverse restraining electric field is applied to the edge restraining area to actively restrain transverse etching of the side wall, the isolation area avoids interference on a non-target area through a passive or high-resistance state, and therefore localized precise regulation and control of the deplating process are achieved. According to the invention, the uncontrollable erosion of the side wall of the micron-sized copper circuit is obviously reduced.

The application provides a copper interconnection layer and a damascene process method of the copper interconnection layer. The side wall and bottom of a via and a trench for forming a copper interconnection line are formed with a barrier layer, which comprises a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer can be a crystal Co layer, a crystal Ru layer or a crystal Os layer. The metal crystal adhesion layer can enhance the adhesion with Cu, effectively inhibit the diffusion of Cu into a dielectric layer and be beneficial to improving the electron migration performance of Cu. The formation of the metal crystal adhesion layer can effectively reduce the total thickness of the barrier layer and a first barrier layer and effectively reduce the resistance of the via. The graphene layer is an amorphous carbon / graphene composite layer. Due to the formation of the graphene layer, the copper interconnection layer has a lower resistivity. The formation of the graphene layer can also effectively reduce the total thickness of the barrier layer or the barrier layer and the first barrier layer and effectively reduce the resistance of the via.

The invention relates to the technical field of semiconductor manufacturing and electronic materials, in particular to a copper interconnection electroplating solution and a copper interconnection electroplating method.The copper interconnection electroplating solution comprises an antioxidant, and the antioxidant comprises a benzotriazole amido derivative. According to the copper interconnection electroplating liquid, the number of nano holes generated in the electroplating process can be reduced, the reliability and the process yield of a plating layer are remarkably improved, and the copper interconnection electroplating liquid is suitable for the requirement of an advanced manufacturing process of a high-density integrated circuit; when the copper interconnection electroplating liquid is used for copper interconnection electroplating, existing hardware equipment does not need to be transformed on a large scale. The copper interconnection electroplating liquid contains the antioxidant, and the antioxidant can well cooperate with Cl <->, the inhibitor and other components in the system to jointly optimize the stability of the whole electroplating liquid system.

The invention discloses a method for synthesizing intercalated doped graphene at low temperature, which comprises the following steps: S1, providing a semiconductor substrate, forming a copper interconnection structure on the semiconductor substrate, and exposing the surface of the copper interconnection structure and the surface of an insulating medium surrounding the copper interconnection structure together; s2, annealing pretreatment is carried out on the semiconductor substrate, an oxide layer on the surface of the semiconductor substrate is removed, and a catalytic surface is exposed; s3, benzene / acetylene is used as mixed carbon source gas, Ar / H2 is used as auxiliary gas, reaction is carried out at the temperature of 300-400 DEG C, and a plurality of graphene layers selectively grow on the surface of the copper interconnection structure; and S4, performing post-intercalation doping treatment on the graphene layer to form an intercalation doping structure. Graphene selectively grows on the copper interconnection surface at low temperature through the benzene / acetylene mixed carbon source, photoetching or transferring is not needed, and damage to the device structure is avoided; the efficient and stable doping of the multilayer graphene is realized through the gas phase intercalation, the conductivity of the graphene layer is improved, and the reliability of the device is improved.

The invention provides a repair process for a selective atomic layer. The repair process comprises the following steps: placing a semiconductor structure in an ALD reaction cavity, firstly introducing a first precursor to perform selective adsorption on the surface of a metal interconnection line, then introducing a second precursor to react with the first precursor adsorbed on the surface of the metal interconnection line, and repeating the steps of selective adsorption and reaction to obtain a metal atomic layer; wherein the first precursor is selected from bis (hexafluoroacetylacetone) copper (II) or (trimethylsilane methyl) copper (I); the second precursor is a reducing gas. According to the method, the specific chemical reaction between the specific precursor substance and the copper metal surface is adopted, high selectivity in the repairing process is achieved, then through the reduction reaction, the deposition reaction only occurs on the exposed surface of the copper interconnection line and in pores and gaps in the copper interconnection line and does not deposit on the dielectric layer, and then precise repairing is achieved.

This invention proposes a semiconductor structure and its fabrication method, belonging to the field of semiconductor technology. The semiconductor structure includes at least: a substrate; a groove recessed from the surface of the substrate into the substrate; a barrier layer disposed on the surface of the substrate and within the groove; a first doped layer disposed on the barrier layer; a second doped layer disposed on the first doped layer; and a conductive layer disposed on the second doped layer. The semiconductor structure and its fabrication method proposed in this invention can effectively reduce void defects in copper interconnect structures while effectively preventing electromigration, thereby improving the reliability and yield of the semiconductor structure.

The application belongs to the field of integrated circuit manufacturing, and particularly relates to a single-layer diffusion barrier layer with low resistivity and high failure temperature for copper interconnection. The diffusion barrier layer is a copper interconnection diffusion barrier layer, which is located between copper and a silicon substrate, and contains M and N elements, wherein M is selected from one of Zr and Hf. The copper interconnection diffusion barrier layer is prepared by a magnetron sputtering process, and the nitrogen content accounts for 18% to 25% of the working gas content during the preparation of the copper interconnection diffusion barrier layer by magnetron sputtering. The single-layer nitride diffusion barrier layer prepared by magnetron sputtering has an ultra-thin thickness, a resistivity lower than 40 micro-ohm per centimeter (even lower than 10 micro-ohm per centimeter) at 600 degrees Celsius, and a failure temperature higher than 600 degrees Celsius. The application has reasonable component design, simple and controllable process, and is convenient for industrial application.

The invention provides an electroplating liquid leveling agent and application thereof. The electroplating liquid leveling agent is obtained by sequentially reacting isocyanate halide or isothiocyanate halide with aliphatic diamine and aromatic compounds. The leveling agent provided by the invention is added into an electroplating solution to be used in copper interconnection electroplating, so that the diffusion migration capability can be improved, the adsorption and desorption activity can be balanced, the generation of in-hole filling morphology defects and subsequent reliability risks are avoided, and the electroplating quality and reliability of an electroplating solution composition in hole filling and pattern co-plating are comprehensively improved; the requirements of electroplating filling and pattern co-plating of the opening structure in a certain depth-to-width ratio span range on the wafer and the substrate can be met, and the method has the industrial application advantages of being wide in adaptive scene, easy and convenient to maintain and control, low in production cost and the like; the method can be applied to the fields of integrated circuit manufacturing, integrated circuit packaging, circuit board manufacturing and photovoltaic manufacturing which relate to hole structure copper interconnection electroplating.

Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner / film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and / or zinc silicon oxide (ZnSiOx) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance / capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.

The invention provides the copper interconnection structure for the integrated circuit chip, which is easy to form a welding spot with good electric connection performance with a large-size metal wire. The copper interconnection structure comprises a copper surface, a metal barrier layer and a weldable metal layer. The copper interconnection structure comprises a weldable metal layer formed on the metal barrier layer, wherein the thickness of the weldable metal layer ranges from 0.03 micrometer to 0.05 micrometer.

The invention relates to an interconnect structure of an integrated circuit. A method of manufacturing an interconnect structure of an integrated circuit, which interconnect structure is intended to be encapsulated in an encapsulation resin in contact with a first surface of a protective layer. The protective layer is located on a first surface of the interconnect structure. The interconnect structure comprises a copper interconnect element, which extends at least partially through an insulating layer and is flush with the first surface of the interconnect structure. The manufacturing method comprises a structuring step of the protective layer or a step of forming the protective layer by structuring. The structuring step or the forming step is adapted to structure the first surface of the protective layer in the form of ridges and grooves alternating with each other.

The invention discloses a Damascus film layer structure and a preparation method thereof, and belongs to the technical field of semiconductor manufacturing. The method adopts a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and Si3N4 is deposited on a copper substrate at 350 DEG C to serve as SiO2 is deposited on the stop layer at the temperature of 180 DEG C to serve as a graphical layer; siOxNy is deposited at the temperature of 400 DEG C to serve as a dielectric anti-reflection layer. By regulating and controlling the deposition temperature difference between different layers, the SiO2 layer formed at a low temperature has relatively low density and shows a higher etching rate during etching, so that the selection ratio of photoresist to oxides is remarkably improved. The structure effectively inhibits excessive etching, realizes accurate etching termination and high-quality pattern transfer, and is suitable for high-performance copper interconnection process requirements.

A capacitor structure embedded in copper interconnection and a forming method thereof, a substrate, the substrate comprising a substrate and a device layer, the device layer having an Nth copper metal interconnection layer; a first insulating layer and a first top electrode on the Nth copper metal interconnection layer; an N+1th dielectric structure on the device layer and having a first height dimension and covering the first insulating layer and the first top electrode; a second bottom electrode, a second insulating layer and a second top electrode on the N+1th dielectric structure, the second bottom electrode on a surface of the Nth copper metal interconnection layer; an N+2th dielectric structure on the N+1th dielectric structure and having a second height dimension and covering the second bottom electrode, the second insulating layer and the second top electrode, the second height dimension being greater than the first height dimension. According to the height dimensions of the N+1th dielectric structure and the N+2th dielectric structure, the number of layers of the capacitor structure can be flexibly designed, that is, the integration of the capacitor structure can be improved, and meanwhile, the electrical contact of the capacitor structure can also be considered.

Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner / film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and / or zinc silicon oxide (ZnSiOx) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance / capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.

The present invention relates to a method for manufacturing a glass substrate having copper interconnects and, more particularly, to a method for manufacturing a glass substrate which can be used in semiconductor 2.5D and 3D PCB packaging and has copper interconnects by forming copper interconnects and horizontal copper lines having a high aspect ratio (1:4 or more) on a silicon-based substrate.

The invention discloses a cross-photoetching-field copper interconnection process mask plate structure. A light-transmitting area of a left side cross-photoetching-field splicing area mask plate and a light-transmitting area of a right side cross-photoetching-field splicing area mask plate are not intersected; the light-transmitting area of the mask template crossing the photoetching field splicing area on the upper side and the light-transmitting area of the mask template crossing the photoetching field splicing area on the lower side are not intersected; the union set of the light-transmitting area of the mask template crossing the photoetching field splicing area on the left side and the light-transmitting area of the mask template crossing the photoetching field splicing area on the right side is a target shape of the photoetching field-crossing copper interconnection wire; and the union set of the light-transmitting area of the mask template crossing the photoetching field splicing area on the upper side and the light-transmitting area of the mask template crossing the photoetching field splicing area on the lower side is a target shape of the copper interconnection line crossing the photoetching field. In the two exposure processes, the photoresist corresponding to the exposure area of the cross-photoetching field metal interconnection area is exposed only once, the problems that the width of a copper metal interconnection line is increased and the distance between interconnection lines is narrowed due to secondary exposure are solved, and the method has important significance on realizing cross-photoetching field metal interconnection by using a copper interconnection process.

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

This invention relates to the field of integrated circuit packaging technology, and in particular to a system-in-package (SIP) method and packaging device. The SIP method involves first preparing a substrate carrier plate that includes both a base carrier plate and a temporary bonding material layer; then, batch exposure, development, and etching of copper plates, filling circuit gaps with passivation dry film to form a motherboard, and cutting independent thick copper interconnect units adapted to the first type of chip to be packaged; subsequently, the chip and the unit are mounted on the carrier plate, and a second type of chip is soldered using metal bumps, making the unit a customized thick copper redistribution layer; finally, through molding, disassembling the carrier plate, creating passivation layer openings and metal circuit terminals, the SIP is completed. By reconfiguring the process route to achieve pre-integration of thick copper units, the thick copper electroplating process on the front side of the chip is avoided, eliminating wafer warpage problems from the source, significantly simplifying the packaging process, and completely eliminating interface risks caused by adhesive-mediated connections, thus combining high reliability with design flexibility.

The invention discloses a radio frequency passive device thermal management structure manufacturing method based on an RDL technology, and relates to the technical field of radio frequency passive devices, and the manufacturing method comprises the following steps: S1, packaging a multifunctional chip and a power divider chip through epoxy resin for a radio frequency circuit, and then carrying out the inverted welding of a welding ball on a radio frequency substrate, and the heating power amplifier chip, the low noise amplifier chip and the switch chip are all arranged on the radio frequency substrate. A power divider chip and a multifunctional chip are packaged through resin by adopting an integration technology, each port is led out through an RDL and micro bump technology, the ports are connected with a radio frequency substrate by adopting an inverted welding technology, and finally the upper radio frequency substrate and a lower power supply control substrate are connected through a middle metal adapter plate and a cavity. And micro-channels or heat conduction columns are embedded in the copper interconnection layer, so that the uniformity of heat distribution is optimized.

The present disclosure relates to methods of forming interconnects to bond package assemblies together. In one embodiment, copper interconnects are used to bond a package assembly having an organic substrate core to other package assemblies or electronic devices having substrate cores which may include organic cores or inorganic cores, such as silicon, glass, or silicon carbide. In another embodiment, copper interconnects are used to bond a package assembly having an organic substrate core to other package assemblies having organic substrate cores. In another embodiment, a semiconductor package assembly comprising copper or copper alloy interconnects, as herein described.

According to the diffusion barrier layer for the copper interconnection structure and the preparation method of the diffusion barrier layer, the metal copper is integrated in the high-entropy alloy target material, the high-entropy alloy thin film is synchronously formed through the magnetron sputtering technology, the high-entropy alloy diffusion barrier layer and the copper seed layer can be formed at the same time by conducting the one-step annealing technology on the high-entropy alloy thin film, and therefore the high-entropy alloy diffusion barrier layer and the copper seed layer can be formed at the same time. Compared with the prior art, the preparation process is simple, the generation cost is reduced, the formed N-doped high-entropy alloy diffusion barrier layer is of a double-phase structure composed of an FCC phase and an amorphous phase, generation of microstructure defects is reduced, the compactness of the diffusion barrier layer is better, the diffusion difficulty of copper atoms is increased, and the performance of the diffusion barrier layer is improved. Therefore, the diffusion barrier performance of the diffusion barrier layer is improved, and in addition, the resistivity of the diffusion barrier layer can be further reduced by adding the amorphous phase.

This invention relates to the analysis and detection of additives in acid copper electrodeposition solutions, specifically to the analysis and detection of PEG, an additive used in the production of electrolytic copper foil and in the electroplating copper interconnect process for chips and printed circuit boards. The method involves: under acidic conditions, protonated, positively charged PEG electrostatically binds with phosphotungstenate ions to form a macromolecular colloidal complex, phosphotungstenate-PEG. This colloidal complex exhibits sensitive absorption at 300 nm. The absorbance of the phosphotungstenate-PEG colloid is measured spectrophotometrically, and the absorbance value shows a linear relationship with the PEG concentration in the acidic copper solution. This invention enables rapid and accurate quantitative analysis of the additive PEG in copper electrodeposition solutions, greatly aiding in the effective monitoring and management of acid copper electrodeposition solutions and stabilizing the quality of electrolytic copper foil and the copper plating layer.

Interconnect structure of a multilayer interconnect feature of an integrated circuit device, wherein the interconnect structure comprises the following: a first interlayer dielectric layer, ILD layer (210); a second ILD layer (270) arranged above the first ILD layer (210); a first copper interconnect (230) located in the first ILD layer (210); a second copper interconnect (290) arranged in the second ILD layer (270); and an aluminum nitride contact etch stop layer, aluminum nitride-CESL (250), arranged between a section of the first copper interconnect (230) and the second ILD layer (270) and between the first ILD layer (210) and the second ILD layer (270), wherein the second copper interconnect (290) extends through the aluminum nitride-CESL (250) to physically contact the first copper interconnect (230), and wherein a surface nitrogen concentration at an interface between the aluminum nitride-CESL (250) and the first copper interconnect (230) is approximately 20 at% or higher, which further exhibits the following: an oxygen-doped silicon carbide CESL (260) arranged above the aluminum nitride CESL (250); and an aluminum oxide CESL (262) arranged above the oxygen-doped silicon carbide CESL (260), wherein the second copper interconnect (290) extends through the oxygen-doped silicon carbide CESL (260) and the aluminum oxide CESL (262).

The invention relates to a copper interconnection process cleaning solution for protecting a low-k material and a preparation method and application of the copper interconnection process cleaning solution for protecting the low-k material, and the copper interconnection process cleaning solution for protecting the low-k material comprises the following components in parts by weight: 10-30 parts of a composite functional agent; 1-10 parts of a stabilizer; 1-10 parts of a corrosion inhibitor; 0.1 to 1 part of a surfactant; and 40-80 parts of a solvent. The compound functional agent is adopted, the aromatic amino acid derivative and the organic sulfonium salt derivative are combined, the compound functional agent is compounded to form a net-shaped supramolecular structure, and the cleaning agent has good material compatibility to metal and non-metal materials while efficient cleaning is achieved.

The invention relates to the technical field of semiconductor manufacturing, and particularly discloses a method for processing a groove and a through hole after etching, which comprises the following steps of: providing a substrate, forming an interlayer dielectric layer on the surface of the substrate, forming the through hole and the groove which are obtained by etching in the interlayer dielectric layer, and exposing the surface of a copper interconnection structure at the bottom of the through hole; and performing first plasma treatment on the substrate to remove etching byproducts on the surfaces of the through hole, the groove and the copper interconnection structure, and forming a first carbon-based film on the surfaces of the through hole, the groove and the copper interconnection structure. According to the processing method after etching of the groove and the through hole, the second carbon-based film is formed on the surfaces of the groove and the through hole and serves as a protection structure before wet cleaning, even if the second carbon-based film is stored in the atmosphere for a long time, the oxygen content of the copper surface is almost not increased, and the effects of protection and water vapor isolation are really achieved; the problems that in the prior art, after etching, a low-dielectric-constant material is damaged, and front-layer metal is oxidized are solved.