82 results about "Copper interconnect" patented technology

A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

In order to enable applications such as artificial intelligence (AI) and machine learning in a large scale, a large amount of information needs to be processed very fast. To improve the speed of the computation, not only faster graphical and central processors are required, but also the communication between processors and high bandwidth memories should be fast enough to reduce the latency. Optical interconnect can be a replacement for copper interconnect which is providing larger bandwidth and lower latency. As an efficient light source, micro-LEDs can be used as light source for chip-to-chip optical interconnect. Using a massively parallel memory-processor interconnect using low-power micro-LED, the computation speed will increase dramatically, and less amount of energy will be wasted through copper self-heating.

The invention discloses a method for controlling CMP (chemical mechanical polishing) dish-shaped pits, corrosion pits and interface corrosion of ruthenium barrier layer copper wiring, which is suitable for a manufacturing process of integrated circuits of 14 nanometers and below. According to the method, a specifically synthesized TTAK corrosion inhibitor is introduced into a polishing solution system, the oriented adsorption characteristic of the molecular structure of the TTAK corrosion inhibitor is utilized, the corrosion reaction of copper is selectively inhibited, meanwhile, the normal material removal efficiency of a ruthenium barrier layer and a TEOS dielectric layer is maintained, and cooperative regulation and control of the removal rate of the Cu / Ru / TEOS material are achieved. By means of the method, dished pits, corrosion pits and Fang type interface defects generated in the fine polishing and barrier layer polishing process can be effectively eliminated, and copper / ruthenium interface corrosion is improved. According to the method, the global planarization quality of the copper interconnection ruthenium barrier layer is remarkably improved, the interface bonding strength and the electrical reliability of an interconnection circuit are enhanced, and an effective solution is provided for performance optimization of an advanced process integrated circuit device.

The invention provides an electroplating solution for Damascus copper interconnection and an electroplating process of the electroplating solution. The plating solution comprises copper sulfate, sulfuric acid, chloride ions and an organic additive. The organic additives comprise an accelerator, an inhibitor and a leveling agent. By adopting the electrocoppering solution disclosed by the invention, the effects of no cavity, compact structure, small surface roughness and smoothness can be realized at advanced nodes, and the electrocoppering solution has a good application prospect in semiconductor wafer manufacturing.

The invention relates to the technical field of semiconductor copper interconnection, in particular to a hole filling method of a copper interconnection semiconductor cooler, which comprises the following steps of: performing multi-stage chemical cleaning treatment on a semiconductor substrate after laser drilling, removing dirt on the surface of the substrate, coarsening the surface of the substrate to increase binding force and removing residual slag at a hole after drilling; the influence on seed layer sputtering in subsequent holes caused by slag accumulation at the hole opening is avoided; and meanwhile, three-step electroplating of the initial copper layer, through hole filling and orifice and surface leveling are adopted, so that cavity-free hole filling and surface nanoscale leveling are realized, and the final product yield is improved.

The invention relates to the technical field of wafer packaging, and particularly discloses wafer-level packaging copper interconnection electroplating liquid and a wafer-level packaging interconnection electroplating process. According to the application, the growth of copper at an orifice is inhibited by utilizing the synergistic effect among the components such as the ammonium pyrrolidine dithiocarbamate, the chloride ions, the copper salt and the polyethylene glycol, and the thickness of a copper plating layer on the surface of the cathode is reduced by adding the anthraquinone sulfonate; and the thickness of the plating layer in the center of the through hole is increased through the synergistic effect of anthraquinone sulfonate, the leveling agent, the accelerator, the brightening agent and the inhibitor, so that the through hole can be effectively filled under the high current density, the good deep plating capacity is achieved, and the product quality can be fully improved.

The invention discloses a method for reducing back-end interconnection contact resistance, and relates to the technical field of semiconductor manufacturing. The method comprises the step of performing surface treatment on a substrate after an opening for exposing a lower-layer copper interconnection structure is formed. The surface treatment adopts a treatment gas containing a reducing gas (such as hydrogen), and copper oxide on the surface of the lower-layer copper interconnection structure is reduced into metal copper in a plasma environment. According to the method, the reducing gas is introduced for etching post-treatment, so that the interface oxide layer can be efficiently and mildly removed, the contact resistance between the through hole and the lower-layer copper interconnection structure is remarkably reduced, and the device cannot be damaged. The method is wide in process window and good in stability, RC delay of an integrated circuit is reduced, and the overall performance of a chip is improved.

The invention discloses a copper interconnection structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a dielectric layer on the substrate; forming a copper conductive structure in the dielectric layer; forming a covering layer on the dielectric layer; and performing first ultraviolet curing treatment on the covering layer and the dielectric layer. Heat assistance of the first ultraviolet curing treatment can help copper ions remaining on the surface of the dielectric layer to diffuse towards the interior of the dielectric layer so as to reduce the concentration of the copper ions on the surface of the dielectric layer. In addition, the first ultraviolet curing treatment can repair the damage of the surface of the dielectric layer in the planarization treatment process, so that the compactness of the top area of the dielectric layer is increased, and diffusion or drift of copper ions is hindered. In addition, the bonding strength between the dielectric layer and the covering layer can be enhanced through the first ultraviolet curing treatment, so that diffusion or drifting of copper ions is hindered. Therefore, after the covering layer is formed, the first ultraviolet curing treatment is favorable for weakening copper diffusion in the dielectric layer, so that the dielectric breakdown resistance of copper interconnection is enhanced.

This invention relates to the field of electroplating solution analysis technology, and in particular to a rapid analytical method for polyethylene glycol (PEG) additives in copper electrodeposition solutions. The method involves protonated PEG forming a macromolecular complex colloid with phosphomolybdate under acidic conditions of pH 1.0–2.0. This colloid exhibits maximum absorption at 372 nm, and the absorbance value is directly proportional to the PEG concentration in the formed complex colloid. This allows for quantitative analysis of PEG in the copper electrodeposition solution. Because the phosphomolybdate-PEG complex colloid selected in this invention has excellent selectivity, and no sample pretreatment is required, this invention offers advantages such as ease of operation, speed, high sensitivity, and good selectivity. It is particularly suitable for intermediate control analysis in production environments, such as for electroplated copper interconnects in chips and printed circuit boards, as well as electrolytic copper foil for negative electrode current collectors and copper-clad laminates in energy storage batteries.

The utility model discloses a conductive performance testing device for a copper interconnection nano film, which comprises a four-probe tester, a control panel is arranged at the front end of the four-probe tester, a testing mechanism is arranged at the top of the four-probe tester, a connecting mechanism is arranged on the testing mechanism, the testing mechanism comprises a testing table, and a testing device is arranged on the testing table. One side of the top of the detection table is fixedly connected with a vertical frame, and the vertical frame is fixedly connected with an electric push rod. According to the conductive performance test equipment for the copper-interconnected nano-film, the nano-film is placed on the placement table, an electromagnet generates attractive force on a magnet block after being electrified, so that a movable base can synchronously move with a second sliding seat, and then the nano-film is moved by a first motor and a second motor; the conductive performance of multiple positions on the nano-film can be tested, the nano-film can be conveniently replaced, the test range is expanded, and the test effect is effectively improved.

Additive manufacturing techniques are described. In one example, a method includes printing, using a printable copper ink, a layer of copper onto a substrate, applying a photonic sintering process to cure the layer of copper to produce a cured layer of copper, repeating, in an alternating manner, the printing and the photonic sintering process to individually print and cure a plurality of additional layers of copper over the cured layer of copper to produce a copper pillar having a selected height, and after forming the copper pillar to the selected height, depositing, onto the substrate, a dielectric material at least partially surrounding the copper pillar.

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a device based on hybrid bonding and a bonding method thereof. Comprising two substrates, namely a first substrate and a second substrate, a plurality of copper interconnection discs, namely a first copper interconnection disc and a second copper interconnection disc, are arranged on the end faces, close to each other, of the first substrate and the second substrate, and the space between the corresponding second copper interconnection disc and the first copper interconnection disc is filled with photosensitive conductive adhesive; a copper-photosensitive conductive adhesive-copper bonding interconnection structure is formed, so that the first substrate and the second substrate are electrically connected; and the dielectric layer is filled between the first substrate and the second substrate to form a protective barrier, and the mixed bonding between the first substrate and the second substrate is promoted by virtue of the erodibility of the dielectric layer. The bonding firmness between the two copper interconnection discs is remarkably enhanced by utilizing the viscosity and the conductivity of the photosensitive conductive disc, and the stability of circuit conduction interconnection between the two substrates is ensured.

The invention provides a chip copper interconnection layer deplating recovery method and system, electronic equipment and a medium, and the method comprises the steps: recognizing an active reaction boundary dissolved by a copper interconnection layer in real time, and dynamically dividing a microelectrode array into a core deplating region, an edge inhibition region and an isolation region according to the active reaction boundary; a forward dissolving electric field is applied to the core deplating area to efficiently remove a copper material, meanwhile, a reverse restraining electric field is applied to the edge restraining area to actively restrain transverse etching of the side wall, the isolation area avoids interference on a non-target area through a passive or high-resistance state, and therefore localized precise regulation and control of the deplating process are achieved. According to the invention, the uncontrollable erosion of the side wall of the micron-sized copper circuit is obviously reduced.

In one example, an integrated circuit (IC) (100) comprises a dielectric layer (122) over a semiconductor substrate (102), a resistive layer (124) over the dielectric layer (122), a metal interconnect trace (138A) over a header end (123A) of the resistive layer (124), a via (134A) extending from the metallic interconnect trace (138A) toward the resistive layer (124), and a metallic barrier layer (130) between the via (134A) and the resistive layer (124).

This invention relates to the field of integrated circuit packaging technology, and in particular to a system-in-package (SIP) method and packaging device. The SIP method involves first preparing a substrate carrier plate that includes both a base carrier plate and a temporary bonding material layer; then, batch exposure, development, and etching of copper plates, filling circuit gaps with passivation dry film to form a motherboard, and cutting independent thick copper interconnect units adapted to the first type of chip to be packaged; subsequently, the chip and the unit are mounted on the carrier plate, and a second type of chip is soldered using metal bumps, making the unit a customized thick copper redistribution layer; finally, through molding, disassembling the carrier plate, creating passivation layer openings and metal circuit terminals, the SIP is completed. By reconfiguring the process route to achieve pre-integration of thick copper units, the thick copper electroplating process on the front side of the chip is avoided, eliminating wafer warpage problems from the source, significantly simplifying the packaging process, and completely eliminating interface risks caused by adhesive-mediated connections, thus combining high reliability with design flexibility.

The present application discloses an integrated circuit structure and a method for fabricating the same. The integrated circuit structure includes a substrate having a circuit region formed thereon, a copper interconnect structure formed on the substrate, the copper interconnect structure including an uppermost copper layer covered by a dielectric layer, an aluminum pad layer formed on the dielectric layer, and a metal layer formed on the circuit region and between the uppermost copper layer and the aluminum pad layer.

The application provides a copper interconnection layer and a damascene process method of the copper interconnection layer. The side wall and bottom of a via and a trench for forming a copper interconnection line are formed with a barrier layer, which comprises a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer can be a crystal Co layer, a crystal Ru layer or a crystal Os layer. The metal crystal adhesion layer can enhance the adhesion with Cu, effectively inhibit the diffusion of Cu into a dielectric layer and be beneficial to improving the electron migration performance of Cu. The formation of the metal crystal adhesion layer can effectively reduce the total thickness of the barrier layer and a first barrier layer and effectively reduce the resistance of the via. The graphene layer is an amorphous carbon / graphene composite layer. Due to the formation of the graphene layer, the copper interconnection layer has a lower resistivity. The formation of the graphene layer can also effectively reduce the total thickness of the barrier layer or the barrier layer and the first barrier layer and effectively reduce the resistance of the via.

The invention relates to the technical field of semiconductor manufacturing and electronic materials, in particular to a copper interconnection electroplating solution and a copper interconnection electroplating method.The copper interconnection electroplating solution comprises an antioxidant, and the antioxidant comprises a benzotriazole amido derivative. According to the copper interconnection electroplating liquid, the number of nano holes generated in the electroplating process can be reduced, the reliability and the process yield of a plating layer are remarkably improved, and the copper interconnection electroplating liquid is suitable for the requirement of an advanced manufacturing process of a high-density integrated circuit; when the copper interconnection electroplating liquid is used for copper interconnection electroplating, existing hardware equipment does not need to be transformed on a large scale. The copper interconnection electroplating liquid contains the antioxidant, and the antioxidant can well cooperate with Cl <->, the inhibitor and other components in the system to jointly optimize the stability of the whole electroplating liquid system.

A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.

The invention relates to a copper pad metallization system and a related method. A particular implementation of a method of forming an interconnect may include forming a grain layer (10) over a plurality of pads (6); patterning the photoresist layer (12) having a plurality of openings (14) exposing the plurality of pads (6); forming a plurality of copper interconnectors (18) by electroplating each of the plurality of copper interconnectors (18) into each of the plurality of openings (14); removing the photoresist layer (12); etching the grain layer (10); forming one or more layers (24) on the plurality of copper interconnectors (18); and patterning the polyimide layer (26) over the plurality of copper interconnectors (18) to form at least one opening (28) over at least one of the plurality of copper interconnectors (18).

The invention discloses a method for synthesizing intercalated doped graphene at low temperature, which comprises the following steps: S1, providing a semiconductor substrate, forming a copper interconnection structure on the semiconductor substrate, and exposing the surface of the copper interconnection structure and the surface of an insulating medium surrounding the copper interconnection structure together; s2, annealing pretreatment is carried out on the semiconductor substrate, an oxide layer on the surface of the semiconductor substrate is removed, and a catalytic surface is exposed; s3, benzene / acetylene is used as mixed carbon source gas, Ar / H2 is used as auxiliary gas, reaction is carried out at the temperature of 300-400 DEG C, and a plurality of graphene layers selectively grow on the surface of the copper interconnection structure; and S4, performing post-intercalation doping treatment on the graphene layer to form an intercalation doping structure. Graphene selectively grows on the copper interconnection surface at low temperature through the benzene / acetylene mixed carbon source, photoetching or transferring is not needed, and damage to the device structure is avoided; the efficient and stable doping of the multilayer graphene is realized through the gas phase intercalation, the conductivity of the graphene layer is improved, and the reliability of the device is improved.

The invention provides a repair process for a selective atomic layer. The repair process comprises the following steps: placing a semiconductor structure in an ALD reaction cavity, firstly introducing a first precursor to perform selective adsorption on the surface of a metal interconnection line, then introducing a second precursor to react with the first precursor adsorbed on the surface of the metal interconnection line, and repeating the steps of selective adsorption and reaction to obtain a metal atomic layer; wherein the first precursor is selected from bis (hexafluoroacetylacetone) copper (II) or (trimethylsilane methyl) copper (I); the second precursor is a reducing gas. According to the method, the specific chemical reaction between the specific precursor substance and the copper metal surface is adopted, high selectivity in the repairing process is achieved, then through the reduction reaction, the deposition reaction only occurs on the exposed surface of the copper interconnection line and in pores and gaps in the copper interconnection line and does not deposit on the dielectric layer, and then precise repairing is achieved.

This invention proposes a semiconductor structure and its fabrication method, belonging to the field of semiconductor technology. The semiconductor structure includes at least: a substrate; a groove recessed from the surface of the substrate into the substrate; a barrier layer disposed on the surface of the substrate and within the groove; a first doped layer disposed on the barrier layer; a second doped layer disposed on the first doped layer; and a conductive layer disposed on the second doped layer. The semiconductor structure and its fabrication method proposed in this invention can effectively reduce void defects in copper interconnect structures while effectively preventing electromigration, thereby improving the reliability and yield of the semiconductor structure.

Implementations of a method of forming an interconnect may include providing a semiconductor substrate including a plurality of aluminum pads thereon, each pad surrounded by a passivation material; forming a barrier layer over the pads and the passivation material; and forming a seed layer over the barrier layer. The method may include patterning a layer of photoresist with a plurality of openings exposing the pads; forming a copper layer at least 18 microns thick over each of the pads by electroplating into each opening of the plurality of openings; and forming a nickel layer at least 5 microns thick over the copper layer. The method may include forming one of a gold layer or a palladium layer over the nickel layer; removing the layer of photoresist; etching the barrier layer and the seed layer to form a copper-containing interconnects; and bonding one of a ribbon bond or a bond wire.

The application belongs to the field of integrated circuit manufacturing, and particularly relates to a single-layer diffusion barrier layer with low resistivity and high failure temperature for copper interconnection. The diffusion barrier layer is a copper interconnection diffusion barrier layer, which is located between copper and a silicon substrate, and contains M and N elements, wherein M is selected from one of Zr and Hf. The copper interconnection diffusion barrier layer is prepared by a magnetron sputtering process, and the nitrogen content accounts for 18% to 25% of the working gas content during the preparation of the copper interconnection diffusion barrier layer by magnetron sputtering. The single-layer nitride diffusion barrier layer prepared by magnetron sputtering has an ultra-thin thickness, a resistivity lower than 40 micro-ohm per centimeter (even lower than 10 micro-ohm per centimeter) at 600 degrees Celsius, and a failure temperature higher than 600 degrees Celsius. The application has reasonable component design, simple and controllable process, and is convenient for industrial application.

The invention provides a method for inhibiting generation of a copper cavity defect, which comprises the following steps of: 1, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a copper interconnection metal layer in the interlayer dielectric layer; 2, forming a protective layer on the interlayer dielectric layer, wherein the pressure stress of an intermediate film layer in the protective layer is increased; and step 3, forming a groove in the protection layer, and exposing a part of the copper interconnection metal layer. The residual stress on the surface of the copper interconnection metal layer is reduced by increasing the pressure stress of the middle film layer in the protection layer, so that the generation of copper cavity defects is inhibited.

The invention provides an electroplating liquid leveling agent and application thereof. The electroplating liquid leveling agent is obtained by sequentially reacting isocyanate halide or isothiocyanate halide with aliphatic diamine and aromatic compounds. The leveling agent provided by the invention is added into an electroplating solution to be used in copper interconnection electroplating, so that the diffusion migration capability can be improved, the adsorption and desorption activity can be balanced, the generation of in-hole filling morphology defects and subsequent reliability risks are avoided, and the electroplating quality and reliability of an electroplating solution composition in hole filling and pattern co-plating are comprehensively improved; the requirements of electroplating filling and pattern co-plating of the opening structure in a certain depth-to-width ratio span range on the wafer and the substrate can be met, and the method has the industrial application advantages of being wide in adaptive scene, easy and convenient to maintain and control, low in production cost and the like; the method can be applied to the fields of integrated circuit manufacturing, integrated circuit packaging, circuit board manufacturing and photovoltaic manufacturing which relate to hole structure copper interconnection electroplating.

Large-grain metal bitlines are formed above the magnetic tunnel barrier pillars that serve as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel barrier. Copper or copper alloy bitlines with relatively small grains are formed on the pillars. Laser annealing is used to melt the bitlines. Subsequent cooling and recrystallization results in a reduction in the number of grain boundaries in the bitline and a reduction in the effective resistivity of the bitline. Multiple melting / cooling cycles can be used. The bitline grains are vertically aligned with the pillars in the resulting structure.