85results about How to "Improved resistance to electromigration" patented technology

The invention discloses a full-carbon coaxial line and a manufacturing method of the full-carbon coaxial line, and belongs to the technical field of integrated circuits. Graphene serves as a monatomic layer thickness, is coiled into a cylinder and form an inner conductor of the coaxial line with a small radius (can be as small as the nm level), and the inner conductor of the coaxial line transfers currents. Meanwhile, a signal layer or multiple layers of graphene serve(s) as an outer conductor of the coaxial line to form a boundary of electromagnetic waves in a space, and graphite oxide serves as medium materials between the inner conductor and the outer conductor to limit and guide oriented transmission of electromagnetic wave energy. The coaxial line is quite small in size and applicable to radio-frequency and microwave integrated circuits.

A method of fabricating a semiconductor device, having an interim reduced-oxygen Cu-Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu-Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35); and a semiconductor device thereby formed. The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu-Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.

A structure and method of fabricating a “Lego”-like interlocking contact for high wiring density semiconductors is characterized in that the barrier liner formed in the contact via extends only partially upwards into the adjacent wire level. As a consequence, current crowding and related reliability problems associated with conventional prior art interconnect structures is avoided and structural integrity of the contact via (metal stud) structure is enhanced. The novel “crown” shape of the Lego-like interlocking contact structure that is fabricated to extend in an upward direction may be employed for other integrated circuit applications including forming capacitor (e.g., MIMCAP) and heat sink structures due to its increased surface area.

An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

A circuit board with twinned Cu circuit layer and a method for manufacturing the same are disclosed, wherein the method comprises the following steps: (A) providing a substrate with a first circuit layer formed thereon, wherein the first circuit layer comprises a conductive pad; (B) forming a first dielectric layer on the surface of the substrate; (C) forming plural openings in the first dielectric layer, wherein each opening penetrates through the first dielectric layer and communicates with the conductive pad to expose the conductive pad; (D) forming a Cu seeding layer in the openings; (E) forming a nano-twinned Cu layer in the openings with an electroplating process; and (F) annealing the substrate to transfer the material of the Cu seeding layer into nano-twinned Cu, wherein the nano-twinned Cu layer and the transferred Cu seeding layer are formed into a second circuit layer.

A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of copper or alloy mainly consisting of copper is filled in the via hole. A second interlayer insulating film made of insulating material is formed over the first interlayer insulating film. A wiring groove is formed in the second interlayer insulating film, passing over the conductive plug and exposing the upper surface of the conductive plug. A wiring made of copper or alloy mainly consisting of copper is filled in the wiring groove. The total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the conductive plug is lower than the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the wiring.

A method of reducing electromigration in a dual-inlaid copper interconnect line (3) by filling a via (6) with a Cu-rich Cu-Zn alloy (30) electroplated on a Cu surface (200 from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a reduced-oxygen Cu-Zn alloy as fill (30) for the via (6) in forming the dual-inlaid interconnect structure (35). The alloy fill (30) is formed by electroplating the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the fill (30) on the Cu surface (20); and annealing the electroplated Cu-Zn alloy fill (30); and planarizing the Cu-Zn alloy fill (30), thereby forming the dual-inlaid copper interconnect line (35).

A technique is disclosed which enables the formation of a metallization layer being substantially comprised of a low-k dielectric material, wherein a compressive stress layer provides enhanced electromigration behavior of the metallization layer. In particular embodiments, a compressive silicon dioxide layer may be formed on or in the vicinity of a dielectric barrier layer and a metallization layer based on SiCOH.

The present invention provides a circuit carrier for connecting to at least a bump. The circuit carrier comprises a substrate, at least a contact pad on a surface of the substrate and a solder mask layer covering the substrate. The solder mask has at least a stepped opening that exposes a portion of the contact pad. The stepped opening includes at least a first opening and a second opening and the size of the first opening is larger than that of the second opening. The stepped opening of the solder mask layer can contain more pre-solder paste, thus increasing the bonding strength between the bump and the contact pad.

A thin film forming method in which a thin film is formed on a surface of a target object to be processed to fill a recess formed in the surface of the target object includes the steps of forming a metal layer for filling on the surface of the target object to fill the recess formed in the surface of the target object and forming a metal film for preventing diffusion on an entire surface of the target object to cover the metal layer for filling. The thin film forming method further includes the step of annealing the target object having the metal film for preventing diffusion formed thereon.

By providing a barrier layer stack including a thin SiCN layer for enhanced adhesion, a silicon nitride layer for confining a copper-based metal region (thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region), and a SiCN layer, the total relative permittivity may still be maintained at a low level, since the thickness of the first SiCN layer and of the silicon nitride layer may be moderately thin, while the relatively thick silicon carbide nitride layer provides the required high etch selectivity during a subsequent patterning process of the low-k dielectric layer.

A metal filled damascene structure with improved electromigration resistance and method for forming the same, the method including providing a semiconductor process wafer comprising damascene openings; and, depositing metal and at least one metal dopant according to an ECD process to from a metal filled damascene comprising a doped metal alloy portion.

A shield electrode is formed above a floating p region in a semiconductor layer and connected to a gate electrode in a trench. The shield electrode is composed of a material having an electrical resistivity lower than that of the gate electrode.

The invention provides a semiconductor light emitting diode (LED) device and a formation method thereof. The semiconductor LED device comprises an active layer, a P-type semiconductor layer, an N-type semiconductor layer, a positive electrode welding layer and a negative electrode welding layer, wherein the P-type semiconductor layer and the N-type semiconductor layer are respectively positioned on two sides of the active layer; the positive electrode welding layer is electrically connected with the P-type semiconductor layer; the negative electrode welding layer is electrically connected with the N-type semiconductor layer; and the positive electrode welding layer and/or the negative electrode welding layer are/is made of an aluminum alloy material. Requirements of the LED device for the electrode welding layers can be well met, electro-migration resistance under large current can be improved, and the thermal stability of the device is improved. Compared with the conventional aluminum material, the aluminum alloy material has the advantages that the service life of the device is prolonged, and control over industrialization cost is facilitated.

A wire structure, comprising: a first insulating layer having a lower layer trench formed in an outer surface thereof; a first diffusion preventing film formed on an inner surface of the lower layer trench; a lower layer wire filled in the lower layer trench through the first diffusion preventing film; an interlayer diffusion preventing film formed on the lower layer wire, the interlayer diffusion preventing film made of a high melt point metal or a high melt point metal compound; a second insulating layer formed over the first insulating layer and the interlayer diffusion preventing film, a second insulating layer having a via hole that penetrates through the second insulating layer and the interlayer diffusion preventing film so as to reach the lower layer wire; a conductive second diffusion preventing film formed on an inner surface of the via hall; a conductor filled in the via hole through the second diffusion preventing film, and an adhering film made of the material that forms the interlayer diffusion preventing film, wherein the adhering film is formed so as to extend from an upper surface of the lower layer wire to a side surface of the second insulating layer within the via hall.

Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

A submicron contact opening fill using a chemical vapor deposition (CVD) TiN liner/barrier and a high temperature, e.g., greater than about 385° C., physical vapor deposition (PVD) aluminum alloy layer that substantially fills the submicron contact.

A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls and the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a top surface of the dielectric layer and planarized to form a metal line in the line trench. The metal line is recessed by a recess etch below the top surface of the dielectric layer. A dielectric line cap or a metallic line cap is formed by deposition of a dielectric cap layer or a metallic cap layer, followed by planarization of the dielectric or metallic cap layer. The dielectric line cap or the metallic line cap applies a highly compressive stress on the underlying metal line, which increases electromigration resistance of the metal line.

The invention relates to a lead-free solder for electronic packaging. The invention solves the technical problems that: the cost of the conventional high-silver solder is higher, and the mechanical property of the conventional low-silver solder is poor. According to percentage by weightmass, the lead-free solder for electronic packaging is composed of Ag, Cu, Ni, Bi, Sb, Ti and the balance of Sn. By designing and optimizing the solder ingredients, the lead-free solder for electronic packaging, which has excellent properties and is low in cost, is obtained. The addition of a variety of elements takes the complementation between the elements into consideration, consequently, while the properties of a certain element are improved, the other adverse affection is reduced, and thereby therefore the comprehensive properties of the solder are effectively enhanced.

An embedded electroconductive layer is disclosed which comprises an opening part or a depressed part 3 formed in an insulating film 2 on a substrate 1, a barrier layer for covering the opening part or the depressed part, a metal growth promoting layer 5 on the barrier layer, and an electroconductive layer 6 embedded in the opening part or the depressed part via the barrier layer 4 and the metal growth promoting layer 5.