7results about How to "Improve electrical characteristics" patented technology

The invention discloses a shielding material for a thermoplastic polyvinyl direct-current power cable as well as a preparation method and application of the shielding material, and relates to the technical field of composite materials. The invention relates to a shielding material for a thermoplastic polyvinyl direct-current power cable. The shielding material comprises the following components in parts by weight: 70-74 parts of polyethylene resin; 22 to 28 parts of filler; 2-6 parts of an auxiliary agent; the filler comprises first conductive carbon black and second conductive carbon black, the particle size of the first conductive carbon black is not less than 30nm, and the particle size of the second conductive carbon black is not more than 15nm. The shielding material is adaptive to an existing thermoplastic polyethylene insulating material, the electric field distortion degree of an insulating / shielding interface is effectively reduced, charge injection into an insulating layer is inhibited, the electric field distortion degree in the insulating layer is effectively reduced, and therefore the electrical characteristics of the insulating material are improved.

A semiconductor device and a semiconductor memory device are provided. The semiconductor device includes: a substrate; a plurality of lower electrodes located on the substrate and spaced apart from each other in a second direction; and a first support member disposed on an upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes, wherein the first support member includes a first support portion and a second support portion, the first support portion overlapping the plurality of lower electrodes in a first direction perpendicular to the second direction, the second support portion being located between the plurality of lower electrodes, each of the plurality of lower electrodes including a protrusion and a recessed portion, the protrusion being located above the lower surface of the second support portion, the recessed portion being located below the lower surface of the second support portion, and the upper surface of the protrusion being a flat surface extending in the second direction.

According to one embodiment of the present invention, a method for forming a thin film using a surface protective substance includes: a surface protective layer forming step, supplying a surface protective substance into a cavity where a substrate is placed to form a surface protective layer on the surface of the substrate; a step of purifying the interior of the cavity once; a metal precursor supplying step, supplying a metal precursor into the cavity; a step of purifying the interior of the cavity twice; and a thin film forming step, supplying a reaction substance into the cavity to react with the metal precursor to form a thin film.

The invention discloses lead-free powder glass for surface stabilization of a mesa type semiconductor device and application of the lead-free powder glass, the lead-free powder glass comprises base material powder and zinc oxide-containing crystal powder, the base material powder comprises the following components in percentage by weight: 50-70% of ZnO, 35-22% of B2O3, 15-25% of SiO2, 0.01-5% of RxOy and 20-15% of Y2O3 and / or GeO, and RxOy is at least one of SnO2 and the like; the zinc oxide-containing crystal powder is at least one of Zn4B6O13 and the like, and the D50 particle size of the powder glass is 1-10 [mu] m. According to the glass powder provided by the invention, various components in the base material powder of the zinc series glass powder are properly proportioned, Y2O3 and GeO2 are introduced to homogenize the glass, and Zn4B6O13 and other crystal powder containing zinc oxide are introduced to enable the crystal granularity of the glass powder to be small, so that the glass powder can be sintered and crystallized at the relative low temperature of 700-750 DEG C, and the glass powder has the advantages of high temperature resistance, high temperature resistance, high temperature resistance and the like. And the coefficient of thermal expansion after crystallization is close to that of a semiconductor material silicon wafer, so that the silicon wafer cannot be warped and cracked, and the reverse withstand voltage is improved.

The invention provides a capacitor assembly packaging structure, a capacitor structure packaging method and an electronic device. The capacitor assembly packaging structure comprises a capacitor assembly, a plurality of first insulation packaging bodies, a second insulation packaging body and an electrode assembly. The capacitor assembly includes a plurality of capacitor structures. The capacitor assembly has a plurality of stack gaps. The plurality of first insulating packaging bodies are configured to be accommodated in the plurality of stacking gaps of the capacitor assembly respectively. The second insulating package is configured to cover the plurality of first insulating packages and the plurality of capacitor structures. The electrode assembly includes a first electrode structure and a second electrode structure electrically connected to the capacitor assembly. The solid content of each first insulation packaging body is smaller than that of the second insulation packaging body, so that the percentage of a plurality of air holes formed in each stacking gap of the capacitor assembly is reduced, and the structural stability of the capacitor assembly packaging structure is improved.

A semiconductor device is provided, the semiconductor device comprising: a lower insulating layer; a lower channel pattern on the lower insulating layer; an upper channel pattern; a lower gate structure surrounding the lower channel pattern; an upper gate structure surrounding the upper channel pattern; a first lower source / drain pattern on the lower gate structure; a first upper source / drain pattern on the upper gate structure; a first spacer on the first upper source / drain pattern; a first source / drain contact extending through the first spacer and the first upper source / drain pattern and connected to the first upper source / drain pattern and the first lower source / drain pattern; a second lower source / drain pattern on the lower gate structure; a second upper source / drain pattern on the upper gate structure; a first interlayer dielectric on the second upper source / drain pattern; and a second source / drain contact extending through the first interlayer dielectric and connected to the second upper source / drain pattern.

A semiconductor device includes a bit line, a channel, a first capping pattern, a gate insulating pattern, a gate electrode, and a capacitor. The bit lines are on the substrate, and each of the bit lines extends in a first direction. The bit lines are spaced apart from each other in the second direction. The channels are spaced apart from each other in the first direction. A first capping pattern is on sidewalls of each of the channels. The gate insulating pattern is on a sidewall of the first capping pattern. The gate electrode is on a sidewall of the gate insulating pattern. The capacitors are electrically connected to respective ones of the channels.