2results about How to "Improve electrical characteristics" patented technology

A semiconductor device and a semiconductor memory device are provided. The semiconductor device includes: a substrate; a plurality of lower electrodes located on the substrate and spaced apart from each other in a second direction; and a first support member disposed on an upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes, wherein the first support member includes a first support portion and a second support portion, the first support portion overlapping the plurality of lower electrodes in a first direction perpendicular to the second direction, the second support portion being located between the plurality of lower electrodes, each of the plurality of lower electrodes including a protrusion and a recessed portion, the protrusion being located above the lower surface of the second support portion, the recessed portion being located below the lower surface of the second support portion, and the upper surface of the protrusion being a flat surface extending in the second direction.

A semiconductor device is provided, the semiconductor device comprising: a lower insulating layer; a lower channel pattern on the lower insulating layer; an upper channel pattern; a lower gate structure surrounding the lower channel pattern; an upper gate structure surrounding the upper channel pattern; a first lower source / drain pattern on the lower gate structure; a first upper source / drain pattern on the upper gate structure; a first spacer on the first upper source / drain pattern; a first source / drain contact extending through the first spacer and the first upper source / drain pattern and connected to the first upper source / drain pattern and the first lower source / drain pattern; a second lower source / drain pattern on the lower gate structure; a second upper source / drain pattern on the upper gate structure; a first interlayer dielectric on the second upper source / drain pattern; and a second source / drain contact extending through the first interlayer dielectric and connected to the second upper source / drain pattern.