19results about How to "Improve electrical characteristics" patented technology

The invention relates to the technical field of semiconductors, particularly provides an IGBT and silicon carbide MOSFET hybrid parallel power module, a motor controller and a vehicle, and aims to solve the problems of high cost and low yield of a power module manufactured by a full silicon carbide MOSFET chip. In order to achieve the purpose, the IGBT and silicon carbide MOSFET hybrid parallel power module comprises a mounting base, semiconductor modules distributed in an array mode are arranged on the mounting base, each semiconductor module comprises an upper bridge arm mechanism, a lower bridge arm mechanism and a substrate, and the upper bridge arm mechanisms and the lower bridge arm mechanisms are connected in series to form a half-bridge structure; the upper bridge arm mechanism comprises an IGBT chipset, a silicon carbide MOSFET chipset and an upper bridge gate signal terminal; a gate of the silicon carbide MOSFET chip of the upper bridge arm mechanism and a gate of the IGBT chip are connected with the upper bridge gate signal terminal; the lower bridge arm mechanism comprises an IGBT chip set, a silicon carbide MOSFET chip set and a lower bridge grid signal terminal. A grid of the silicon carbide MOSFET chip of the lower bridge arm mechanism and a grid of the IGBT chip are connected with the lower bridge grid signal terminal.

The composite component has an interposer structure and an electronic component. The interposer structure has: a silicon-based layer having a first main surface and a second main surface facing each other; a rewiring layer formed on the first main surface; a through-silicon via electrically connected to the rewiring layer and penetrating the silicon-based layer; an interposer electrode facing the second main surface; and an adhesive layer. The electronic component has a component electrode connected to the through-silicon via, which is arranged between the interposer electrode and the silicon-based layer. The electronic component adheres the component electrode and the surface on which the component electrode is formed to the second main surface of the silicon-based layer via the adhesive layer. The through-silicon via has a through-silicon via main body and an extended protrusion, which extends from the second main surface, penetrates the adhesive layer and is electrically connected to the component electrode.

The present invention discloses a semiconductor laser manufacturing method and a semiconductor laser, and relates to the field of semiconductor technology. The semiconductor laser manufacturing method comprises: providing a substrate with a ridge strip, the ridge strip comprises a plurality of strip segments with different widths; depositing a dielectric film on the substrate; forming a photoresist material layer on the dielectric film; providing a mask and placing it above the photoresist material layer, the light-transmitting area of ​​the mask comprises a plurality of light-transmitting segments respectively corresponding to the plurality of strip segments; exposing the photoresist material layer through the mask; developing the exposed photoresist material layer to form a reflow groove, the reflow groove comprises a plurality of groove segments corresponding to each strip segment, and the groove sidewalls of the plurality of groove segments have the same gap width as the corresponding strip segments. The semiconductor laser manufacturing method provided by the present invention can prepare a semiconductor laser with higher electrical characteristics and reliability.

The present invention aims to provide an elastic fiber treatment agent capable of achieving both improvement of the electrical properties of elastic fibers and improvement of the stability of the elastic fiber treatment agent, and an elastic fiber to which the elastic fiber treatment agent is attached. The elastic fiber treatment agent of the present invention contains polyether-modified silicone, a smoothing agent other than the polyether-modified silicone, and water, and is characterized in that the content of the polyether-modified silicone in the elastic fiber treatment agent is 0.01 mass % or more and 10 mass % or less, and the HLB of the polyether-modified silicone is 1 or more and 7 or less.

The invention discloses a shielding material for a thermoplastic polyvinyl direct-current power cable as well as a preparation method and application of the shielding material, and relates to the technical field of composite materials. The invention relates to a shielding material for a thermoplastic polyvinyl direct-current power cable. The shielding material comprises the following components in parts by weight: 70-74 parts of polyethylene resin; 22 to 28 parts of filler; 2-6 parts of an auxiliary agent; the filler comprises first conductive carbon black and second conductive carbon black, the particle size of the first conductive carbon black is not less than 30nm, and the particle size of the second conductive carbon black is not more than 15nm. The shielding material is adaptive to an existing thermoplastic polyethylene insulating material, the electric field distortion degree of an insulating / shielding interface is effectively reduced, charge injection into an insulating layer is inhibited, the electric field distortion degree in the insulating layer is effectively reduced, and therefore the electrical characteristics of the insulating material are improved.

The utility model discloses an anti-twisting loosening type anti-interference audio cable which comprises two insulating wire cores and two nylon fiber filling cores which are symmetrically arranged in a cross shape and are jointly twisted to form a cable core, and the cable core is sequentially coated with a PTFE semi-directional belt wrapping antifriction layer, an aluminum foil shielding layer and an irradiation crosslinking high-density polyethylene outer sheath layer. A tinned oxygen-free copper bar streamline is arranged between the antifriction layer and the shielding layer, the insulating wire core comprises a tinned oxygen-free copper conductor and an irradiation crosslinking low-density polyethylene insulating layer, the insulating wire core is back-twisted and twisted, the twisting pitch is 8-15 times of the outer diameter, the twisting direction of the insulating wire core is opposite to the twisting direction of the cable core, the sectional area of the insulating wire core is 0.2 mm2 to 1.5 mm2, and the outer diameter of the outer sheath layer does not exceed 9mm. According to the cable, the cable core structure is balanced, the double cores are twisted tightly and are not easy to loosen, the influence of interference generated between the double-core wire pairs is reduced, the external electromagnetic wave interference resistance is enhanced, and the stable signal transmission characteristic is ensured.

A semiconductor device and a semiconductor memory device are provided. The semiconductor device includes: a substrate; a plurality of lower electrodes located on the substrate and spaced apart from each other in a second direction; and a first support member disposed on an upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes, wherein the first support member includes a first support portion and a second support portion, the first support portion overlapping the plurality of lower electrodes in a first direction perpendicular to the second direction, the second support portion being located between the plurality of lower electrodes, each of the plurality of lower electrodes including a protrusion and a recessed portion, the protrusion being located above the lower surface of the second support portion, the recessed portion being located below the lower surface of the second support portion, and the upper surface of the protrusion being a flat surface extending in the second direction.

According to one embodiment of the present invention, a method for forming a thin film using a surface protective substance includes: a surface protective layer forming step, supplying a surface protective substance into a cavity where a substrate is placed to form a surface protective layer on the surface of the substrate; a step of purifying the interior of the cavity once; a metal precursor supplying step, supplying a metal precursor into the cavity; a step of purifying the interior of the cavity twice; and a thin film forming step, supplying a reaction substance into the cavity to react with the metal precursor to form a thin film.

The invention discloses lead-free powder glass for surface stabilization of a mesa type semiconductor device and application of the lead-free powder glass, the lead-free powder glass comprises base material powder and zinc oxide-containing crystal powder, the base material powder comprises the following components in percentage by weight: 50-70% of ZnO, 35-22% of B2O3, 15-25% of SiO2, 0.01-5% of RxOy and 20-15% of Y2O3 and / or GeO, and RxOy is at least one of SnO2 and the like; the zinc oxide-containing crystal powder is at least one of Zn4B6O13 and the like, and the D50 particle size of the powder glass is 1-10 [mu] m. According to the glass powder provided by the invention, various components in the base material powder of the zinc series glass powder are properly proportioned, Y2O3 and GeO2 are introduced to homogenize the glass, and Zn4B6O13 and other crystal powder containing zinc oxide are introduced to enable the crystal granularity of the glass powder to be small, so that the glass powder can be sintered and crystallized at the relative low temperature of 700-750 DEG C, and the glass powder has the advantages of high temperature resistance, high temperature resistance, high temperature resistance and the like. And the coefficient of thermal expansion after crystallization is close to that of a semiconductor material silicon wafer, so that the silicon wafer cannot be warped and cracked, and the reverse withstand voltage is improved.

The semiconductor package may include: a base semiconductor chip; a connection semiconductor chip on the base semiconductor chip; an upper semiconductor chip on the connection semiconductor chip; a filling layer in the trench in the upper semiconductor chip; and a molding layer extending around the upper semiconductor chip.

According to the embodiment, the optical path control component includes: a first substrate; a first electrode, which is arranged on the first substrate; a light conversion part, which is arranged on the first electrode; a second substrate, which is arranged on the first substrate; a second electrode, which is arranged below the second substrate; and an adhesive layer, which is arranged between the light conversion part and the second electrode, wherein the light conversion part includes alternately arranged partition wall parts and receiving parts, the light transmittance of the receiving part changes according to the application of voltage, the upper surface of the partition wall part is in contact with the adhesive layer, and the light conversion part is formed by a photocurable resin, the photocurable resin contains oligomers, monomers, photopolymerization initiators and additives, and the additives contain 1.5wt% to 3.0wt% of an antistatic agent.

Disclosed is a semiconductor package including: an interposer; a first semiconductor die under the interposer; and a first dummy die, a second dummy die, and a second semiconductor die over the interposer. The first semiconductor die, the second semiconductor die, the first dummy die, and the second dummy die overlap the interposer. The first semiconductor die overlaps the second semiconductor die. The second semiconductor die is between the first dummy die and the second dummy die.

The invention provides a capacitor assembly packaging structure, a capacitor structure packaging method and an electronic device. The capacitor assembly packaging structure comprises a capacitor assembly, a plurality of first insulation packaging bodies, a second insulation packaging body and an electrode assembly. The capacitor assembly includes a plurality of capacitor structures. The capacitor assembly has a plurality of stack gaps. The plurality of first insulating packaging bodies are configured to be accommodated in the plurality of stacking gaps of the capacitor assembly respectively. The second insulating package is configured to cover the plurality of first insulating packages and the plurality of capacitor structures. The electrode assembly includes a first electrode structure and a second electrode structure electrically connected to the capacitor assembly. The solid content of each first insulation packaging body is smaller than that of the second insulation packaging body, so that the percentage of a plurality of air holes formed in each stacking gap of the capacitor assembly is reduced, and the structural stability of the capacitor assembly packaging structure is improved.

A semiconductor device is provided, the semiconductor device comprising: a lower insulating layer; a lower channel pattern on the lower insulating layer; an upper channel pattern; a lower gate structure surrounding the lower channel pattern; an upper gate structure surrounding the upper channel pattern; a first lower source / drain pattern on the lower gate structure; a first upper source / drain pattern on the upper gate structure; a first spacer on the first upper source / drain pattern; a first source / drain contact extending through the first spacer and the first upper source / drain pattern and connected to the first upper source / drain pattern and the first lower source / drain pattern; a second lower source / drain pattern on the lower gate structure; a second upper source / drain pattern on the upper gate structure; a first interlayer dielectric on the second upper source / drain pattern; and a second source / drain contact extending through the first interlayer dielectric and connected to the second upper source / drain pattern.

The utility model discloses a flattened film capacitor core arrangement and copper bar structure, which comprises a small copper bar, two welding areas are arranged on the small copper bar, a plurality of grooves are arranged on the small copper bar, the small copper bar which can be subjected to electric resistance welding with a capacitor core is added, and after the small copper bar is subjected to electric resistance welding with a capacitor, the small copper bar can be subjected to electric resistance welding with the capacitor core. According to the utility model, the capacitor is welded with the large laminated copper bar, so that the flexibility of capacitor placement can be improved, the size flattening can be realized, the ESL (equivalent series inductance) can be reduced, the thin-film capacitor core can be flatly laid on the structure of the surface of the copper bar, the positive and negative copper bars adopt the laminated structure, the electrical characteristics of the controller can be improved, and the overall thickness can be reduced.

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A method of manufacturing a semiconductor device according to an embodiment of the present invention may comprise the steps of: growing a stack layer by alternately stacking sacrificial layers and channel regions on a substrate; forming a sacrificial polycrystalline silicon gate on the stack layer; forming an inner spacer and a side spacer on a side surface of the sacrificial layer and a side surface of the sacrificial polysilicon gate; and performing heat treatment on the inner spacer or the side spacer in a chamber set to a preset process pressure and a preset process temperature.

The invention provides a memory device. The memory device comprises a plurality of first peripheral circuits, a laminated memory cell array and a first addressing circuit, the first peripheral circuit is arranged on a first chip, wherein the first chip is provided with a plurality of first welding pads. The laminated memory cell array is arranged on the second chip, wherein the second chip is provided with a plurality of second welding pads. The second pads are coupled to the stacked memory cell array and are respectively coupled to the corresponding first pads. The first addressing circuit is disposed on the second chip, coupled to the stacked memory cell array, and disposed below the stacked memory cell array.

A semiconductor device includes a bit line, a channel, a first capping pattern, a gate insulating pattern, a gate electrode, and a capacitor. The bit lines are on the substrate, and each of the bit lines extends in a first direction. The bit lines are spaced apart from each other in the second direction. The channels are spaced apart from each other in the first direction. A first capping pattern is on sidewalls of each of the channels. The gate insulating pattern is on a sidewall of the first capping pattern. The gate electrode is on a sidewall of the gate insulating pattern. The capacitors are electrically connected to respective ones of the channels.

The invention relates to a method for preparing lithium difluorophosphate with high yield by using low-monovalent raw materials. More particularly, the present invention relates to a method for preparing a high-purity and high-yield lithium difluorophosphate salt without using a lithium hexafluorophosphate salt. Therefore, the lithium difluorophosphate salt prepared according to the present invention can be used in an electrolyte for a lithium secondary battery, and has the effects of electrochemical characteristics, output power, gas reduction, and the like when used in an electrolyte for a lithium secondary battery.