188results about How to "Excellent electrical properties" patented technology

The invention discloses a perovskite solar cell based on 1, 2PDADI (1, 2-propane diamine hydriodic acid) interface modification and a preparation method thereof, and belongs to the technical field of perovskite solar photovoltaics. The device structure of the cell sequentially comprises ITO conductive glass, a SnO2 electron transport layer, a 1, 2PDADI modification layer, a perovskite light absorption layer, a hole transport layer and an Ag counter electrode from bottom to top, the preparation method specifically comprises the following steps: (1) cleaning and blow-drying the ITO conductive glass; (2) spin-coating SnO2 nano dispersion liquid, and carrying out annealing treatment; (3) spin coating of a 1, 2PDADI / IPA solution is carried out, and annealing treatment is carried out; (4) spin-coating a perovskite precursor solution, and performing annealing treatment; (5) spin coating of a Spiro-OMeTAD precursor solution is carried out, and oxidation treatment is carried out; and (6) carrying out vacuum evaporation on an Ag counter electrode to obtain the 1, 2PDADI interface modified perovskite solar cell. The preparation process is simple and convenient, the cost is low, the prepared perovskite solar cell is small in hysteresis effect and high in photoelectric conversion efficiency, and a feasible thought and method are provided for commercialization of the perovskite solar cell.

The invention discloses high-density ultra-thin electronic-grade glass fiber cloth, and relates to the technical field of glass fiber cloth preparation, the high-density ultra-thin electronic-grade glass fiber cloth is formed by weaving warp yarns and weft yarns with the monofilament diameter of 4.0 microns, the warp and weft density is 90-100 pieces / inch, an air jet loom is combined with an auxiliary air jet mechanism for plain weaving, and it is guaranteed that fibers are tightly arranged; the preparation method comprises the steps of low-speed warping, weaving, desizing, deep splitting, cleaning and surface treatment. During weaving, through low-tension control and low-pressure airflow assistance, the fabric structure is more compact and uniform; a three-step method is adopted to gradually eliminate most slurry, and the slurry is further removed through liquefaction desizing; splitting and cleaning adopt a water flow and air flow combined mode, so that fiber opening is ensured, and the slurry residue rate is reduced to the minimum; finally, the strength of the high-density ultrathin electronic-grade glass fiber cloth is improved through treatment of a silane coupling agent; and low-tension and extremely low-slurry-residue-rate weaving of the high-density ultrathin electronic-grade glass fiber cloth is realized.

A method of forming a layer of material on one or more substrates by ALD is disclosed. Embodiments of the presently described methods include performing a plurality of deposition cycles including at least two precursor pulses and an intervening purge pulse to form a layer of material on one or more substrates. During each deposition cycle, a ratio of the process chamber pressure during each of the at least two precursor pulses to the process chamber pressure during the intervening purge pulse is equal to or different from each other.

The invention discloses a double-gate enhanced gallium nitride radio frequency power transistor, which relates to the field of transistors and comprises a substrate, a buffer layer, a GaN channel layer and an AlGaN barrier layer which are sequentially stacked, a p-GaN cap layer is arranged on the upper surface of the AlGaN barrier layer; a direct current grid electrode is arranged on the upper surface of the p-GaN cap layer; two ends of the upper surface of the AlGaN barrier layer are respectively provided with a source electrode and a drain electrode; a radio frequency grid electrode is arranged on the upper surface of the AlGaN barrier layer and located between the source electrode and the p-GaN cap layer. The transistor structure designed by the invention relates to the double-gate combination of the radio frequency gate and the direct current gate, so that the transistor device can simultaneously obtain a plurality of excellent electrical characteristics such as high cut-off frequency, positive threshold voltage, large breakdown voltage and low switch ratio.

The invention relates to an electrode grid line preparation method and a photovoltaic cell, and relates to the field of photovoltaic technology, and the method comprises the following steps: S1, providing a substrate, and forming a polymer layer on the substrate; s2, providing a first mold, and pressing a first groove on the polymer layer; s3, first conductive slurry is smeared on the polymer layer; s4, providing a second mold, and pressing a second groove on the first conductive slurry; s5, smearing second conductive slurry on the first conductive slurry; s6, providing a base material, and transferring the first conductive slurry and the second conductive slurry onto the base material; s7, stripping the substrate, dissolving the polymer layer, and enabling the first conductive slurry and the second conductive slurry to be adhered to the base material; and S8, sintering the first conductive slurry and the second conductive slurry to form the electrode grid line. By adopting a combined structure of the first conductive slurry and the second conductive slurry, the cost can be reduced while the conductive effect of the electrode grid line is improved.

Aqueous acidic binary silver-bismuth alloy electroplating compositions and methods enabling electroplating of silver-rich binary silver-bismuth deposits are disclosed. The aqueous acidic binary silver-bismuth alloy electroplating compositions include a 5-membered heterocyclic nitrogen compound having mercapto functionality, which enables deposition of a silver-rich binary silver-bismuth alloy. The silver-rich silver-bismuth deposit is matte to semi-bright, uniform, and has a low coefficient of friction.

The invention relates to the technical field of copper alloy strips, and discloses a vehicle-mounted connector copper alloy strip which comprises the following components in percentage by mass: 0.04 to 0.1 weight percent of Y, 1.5 to 3.5 weight percent of Sn, 0.02 to 0.08 weight percent of P, 0.5 to 2.5 weight percent of carbon nanostructure X and the balance of copper and inevitable impurities, wherein the carbon nano structure X is a compound of a carbon nano tube and fullerene, and the mass ratio of the carbon nano tube to the fullerene is (2-4): 1; the invention also discloses a preparation method. According to the invention, through the comprehensive advantages in the aspects of conductivity and corrosion resistance, the electrical connection function can be stably and reliably realized in a vehicle-mounted connector, powerful hardware support is provided for the intelligent and electric development of an automobile, and the adaptability and safety of the automobile under different working conditions are enhanced; and the maintenance cost of the automobile is reduced, and the downtime caused by faults is shortened.

The present invention relates to a composite electrolyte exhibiting improved mechanical properties and ion conductivity while preventing liquid leakage, a method for preparing the same, and a lithium secondary battery comprising the same. The composite electrolyte may include: a liquid electrolyte; a cross-linked polymer of monomers having curable functional groups; and oxide-based solid electrolyte particles dispersed on the cross-linked polymer and having a particle diameter of greater than 300 nm.

The invention relates to the technical field of solar cells, and mainly provides a solar cell and a preparation method thereof. The preparation method of the solar cell comprises the following steps: providing an N-type silicon wafer, and respectively forming a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on two opposite surfaces of the N-type silicon wafer; forming an N-type doped microcrystalline silicon layer on the first intrinsic amorphous silicon layer and forming a P-type doped microcrystalline silicon layer on the second intrinsic amorphous silicon layer by using an intermittent CO2 plasma treatment process; and forming a first transparent conductive layer and a first electrode on the N-type doped microcrystalline silicon layer, and forming a second transparent conductive layer and a second electrode on the P-type doped microcrystalline silicon layer. The preparation method of the solar cell in the technical scheme of the invention can promote the crystallization of the oxygen-doped microcrystalline silicon, enhance the electrical properties of the microcrystalline silicon, properly reduce the thickness of the doped microcrystalline silicon layer, reduce the process time and reduce the production cost.

The present invention discloses a thin covering film with EMI function, which comprises a carrier layer, a first insulating layer, a metal layer, a second insulating layer, a second adhesive layer and a release layer which are stacked. The covering film has the function of insulating the covering film from an electronic circuit surface and shielding the transmission signal. In terms of manufacturing process, the covering film and the shielding film are combined into one, and the process difficulties of the two are combined to achieve a thickness thinner than the covering film, and the thickness can even reach 9-10 μm, which does not affect the product function and reduces the process steps and the production cost. In terms of product physical properties, the surface has high hardness, extremely low gloss, good mechanical properties, and good shielding effect. In terms of later storage, since the present invention contains EMI in the covering film, the storage method can be stored in the same way as the conventional covering film.

The invention discloses a low-cost all-vertical gallium nitride Schottky barrier diode and a preparation method thereof. The diode comprises a transmission layer; the drift layer is located on the lower surface of the transmission layer; the positive electrode is located in the middle of the lower surface of the drift layer; the negative electrode is located in the middle of the transmission layer; the first dielectric layer is located on the lower surface of the remaining drift layer and the side wall and part of the lower surface of the positive electrode; the second dielectric layer is located on the upper surface of the remaining transmission layer and the side wall and part of the upper surface of the negative electrode; the positive electrode thickening layer is located on the lower surface of the first dielectric layer and the lower surfaces of the remaining negative electrodes; the conductive substrate is positioned on the lower surface of the positive electrode thickening layer; the additional positive electrode is positioned in the middle of the lower surface of the conductive substrate; the negative electrode thickening layer is located on the upper surface of a part of the second dielectric layer and the upper surface of the remaining negative electrode. According to the invention, a completely longitudinal conductive vertical device structure is realized, the forward current density of the device is improved, and the on-resistance is reduced.

A flexible circuit board includes a substrate, a plurality of circuit patterns disposed on the substrate, and a protective layer disposed on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness greater than 8 µm and less than or equal to 25 µm, and wherein a thickness deviation between the plurality of circuit patterns is 0.5 µm to 3 µm. When the flexible circuit board is connected with a display panel, the display panel can have high performance and high current can flow through the display panel. The circuit pattern having the features according to the present invention is prevented from being damaged by high current.

The present invention discloses a high-voltage and high-current diamond lateral Schottky diode and a preparation method thereof, belonging to the technical field of semiconductor materials and devices; a high-voltage and high-current diamond lateral Schottky diode is prepared by opening a trapezoidal through hole on a hydrogen-terminated diamond, depositing a Schottky contact layer and an ohmic contact layer on the front of the hydrogen-terminated diamond, and growing polycrystalline diamond on the back of the hydrogen-terminated diamond. The trapezoidal through hole structure in the present invention increases the voltage resistance of the lateral Schottky diode, so that the lateral Schottky diode has good electrical characteristics. At the same time, the present invention prepares a Schottky contact layer and an ohmic contact layer on a thinner hydrogen-terminated diamond, reducing the use cost of the hydrogen-terminated diamond, and then growing polycrystalline diamond on the back as a substrate can play a supporting role. The addition of polycrystalline diamond can further improve the performance of the device while reducing the cost of manufacturing the device.

A series of palladium compounds described in the specification are excellent vinyl addition polymerization catalysts. Specifically, compounds represented by general formulae (I) and (II) described in the specification unexpectedly exhibit much higher reactivity than compounds known in the art in the vinyl addition polymerization of various cycloolefin monomers, and thus can form a polymer having an extremely high molecular weight. The present specification also discloses methods of forming various solid three-dimensional articles, such as solution extrusion of a polymer solution formed by vinyl addition polymerization of various cycloolefin monomers using very low amounts of a palladium compound of general formula (I) or (II) as described in the specification. Polymer films formed from the polymerizable composition exhibit unprecedented properties, such as excellent transparency properties, higher thermal and mechanical properties, and other improved properties. Thus, the films so formed can be used in a variety of optoelectronic applications. # imgabs0 #

The invention provides a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of poor performance of the semiconductor device. The semiconductor device includes: a substrate; a gate trench located in the substrate; the gate dielectric layer is located in the substrate and covers the inner surface of the gate trench; the gate structure is located on the gate dielectric layer and fills the gate groove, and the gate structure comprises a metal layer and a conductive layer; the metal layer comprises a plurality of first crystal grains; the second crystal grains are located on the first crystal grains, the first crystal grains and the second crystal grains contain the same metal element, and the crystal grain size of the second crystal grains is smaller than that of at least part of the first crystal grains; a conductive layer on the second die; the conductive layer is isolated from the second die by oxygen, and a side of oxygen away from the first die is in contact with the conductive layer. In the gate structure of the semiconductor device, the second crystal grain is not in direct contact with the conductive layer, so that drain leakage current induced by the gate can be reduced, and the performance of the semiconductor device is improved.

Provided are: an anion exchange resin with which it is possible to produce an electrolyte membrane, a binder for forming an electrode catalyst layer, and a battery electrode catalyst layer, each of which has excellent electrical characteristics (anionic conductivity) and chemical characteristics (air permeability and water-containing properties); and an electrolyte membrane and a binder for forming an electrode catalyst layer, each of which is formed from the anion exchange resin. And a battery electrode catalyst layer formed from the binder for forming an electrode catalyst layer. For example, an anion exchange resin is used that contains: a hydrophobic unit in which a divalent hydrophobic group containing a bisphenol residue having an alicyclic structure is repeated via a carbon-carbon bond; a hydrophobic unit in which a divalent hydrophobic group comprising a plurality of aromatic rings bonded to each other via a divalent fluorine-containing hydrocarbon group is repeated via a carbon-carbon bond; and a hydrophilic unit having a fluorene ring bonded to a group containing an anion exchange group, the three units being bonded via a carbon-carbon bond.

The exemplary embodiments of the present disclosure provide a display substrate and a method for preparing the same, and a display device. The display substrate includes a first conductive layer, a first metal layer, a metal oxide layer, and a second metal layer stacked on a substrate, the metal oxide layer includes a first active layer, the first active layer includes a channel region, a source transition region, and a drain transition region, the source transition region and the drain transition region both include a first region and a second region, the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region. The exemplary embodiments of the present disclosure reduce the number of patterning processes, improve the alignment accuracy of the gate electrode and the channel region, and improve the electrical characteristics of the thin film transistor.

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of relatively high threshold voltage. The semiconductor structure comprises a semiconductor substrate with an NMOS (N-channel Metal Oxide Semiconductor) region and a PMOS (P-channel Metal Oxide Semiconductor) region, a first gate stack structure positioned on the semiconductor substrate in the NMOS region, and a second gate stack structure positioned on the semiconductor substrate in the PMOS region, and both the first gate stack structure and the second gate stack structure comprise high-K dielectric layers; the first isolation layer is located on the side wall of the first gate stack structure to cover the corresponding high-K dielectric layer, protect the oxygen vacancy and reduce the threshold voltage of the first gate stack structure; the second isolation layer is located on the side wall of the second gate stack structure, the second isolation layer at least comprises an oxide isolation layer, the oxide isolation layer at least covers at least part of the side face of the high-K dielectric layer in the second gate stack structure, the oxygen vacancy of the high-K dielectric layer in contact with the oxide isolation layer is repaired, and the threshold voltage of the second gate stack structure is reduced.

The present specification discloses an electrode assembly and a secondary battery. The electrode assembly can exhibit low resistance and excellent electrical characteristics in a normal state, and ensure stability by rapidly transitioning to an insulator in an abnormal state. The present specification also discloses a secondary battery including the electrode assembly.

A semiconductor device and a method for manufacturing the same are disclosed. According to an embodiment, the semiconductor device may include: an SOI substrate; a channel portion on the SOI substrate, the channel portion including a two-dimensional semiconductor material layer; a gate stack on the channel portion; and source / drain portions on the SOI substrate, located on opposite sides of the gate stack and disposed at opposite ends of the channel portion, wherein the two-dimensional semiconductor material layer is on the bottom surface and side surface of the gate stack, and extends on the side surface of the source / drain portion thereby being located between the side surface of the source / drain portion and the side surface of the gate stack.

An example of a semiconductor device includes a substrate; a channel layer on the substrate; a first barrier layer on the channel layer; a second barrier layer on the first barrier layer; a third barrier layer on the second barrier layer and extending into a portion of the first barrier layer and a portion of the second barrier layer; a gate electrode on the third barrier layer; and a source electrode and a drain electrode on either side of the gate electrode, wherein each of the source electrode and the drain electrode extends into a first portion of the third barrier layer and is connected to the second barrier layer, and wherein the second barrier layer is doped with silicon.

The invention discloses a manufacturing method of a terminal module and a connector assembly comprising the terminal module, the terminal module comprises first differential terminals and conductive terminals which are formed separately, each first differential terminal comprises a first main body part, a first welding part and a tail part, each conductive terminal comprises a second main body part, a contact part and a second welding part, the plurality of conductive terminals comprise second differential terminals, the first welding parts of the first differential terminals and the second welding parts of the second differential terminals which are formed separately are arranged at intervals, and electronic elements are arranged at the corresponding intervals. Therefore, the middle part of the whole signal terminal does not need to be cut by a shearing knife to form a fracture, so that the manufacturing of the terminal module can be facilitated, and the electrical characteristics of the terminal module can be improved.

The invention discloses an anti-UV screen protection film and a preparation method thereof, and relates to the technical field of protection films, and the anti-UV screen protection film comprises a release film layer, a pressure-sensitive adhesive layer, a tempered glass film layer, a titanium dioxide reflective film layer, a UV absorption film layer and a PET synthetic film layer which are stacked in sequence; wherein the titanium dioxide reflecting film layer comprises modified zinc sulfide, and the modified zinc sulfide comprises zinc sulfide nanoparticles and an S-P-N type additive in a mass ratio of 1: (0.5-0.8); the preparation method of the modified zinc sulfide comprises the following steps: mixing zinc sulfide nanoparticles with an S-P-N type additive, and then carrying out ultrasonic stirring, so that the zinc sulfide nanoparticles are fully and uniformly mixed in the S-P-N type additive, thereby obtaining the modified zinc sulfide, the modified zinc sulfide is introduced on the titanium dioxide reflecting film layer, and the uniformly distributed salient points are arranged on the titanium dioxide reflecting film layer, so that the reflectivity of the titanium dioxide reflecting film layer to UV is improved, and the anti-UV performance of the protective film is further improved.

The application relates to a crimping IGBT three-level power unit structure based on phase change cooling, wherein a phase change cooling power assembly and a supporting capacitor assembly are arranged in sequence from front to back, a three-level valve string is horizontally placed, power devices are arranged between adjacent phase change cooling radiators, the phase change cooling radiators are vertically placed, phase change working medium connecting pipes are arranged at the upper part and the lower part of the three-level valve string, a valve string direct current connection row is arranged at the rear end of the three-level valve string, the connection terminals of the valve string direct current connection row are located above the three-level valve string and are in a leading direction, an output row is arranged at the front end of the three-level valve string, and the connection terminals of the output row are located on the side of the three-level valve string. The application has the advantages that the valve string direct current connection row and the valve string capacitor connection row of the supporting capacitor assembly are overlapped on the top between the phase change cooling power assembly and the supporting capacitor assembly, the connection terminals of the valve string capacitor connection row are in a leading direction, the phase change cooling power assembly can be disassembled on the front side of a cabinet body, and maintenance is easy.

The invention discloses a monolithic integrated diode amplitude limiting unit based on quasi-vertical MPSs and a preparation method thereof. The amplitude limiting unit comprises two silicon-based GaN quasi-vertical MPSs located on a silicon substrate, and a forward amplitude limiting diode and a reverse amplitude limiting diode are formed; the passivation layer covers the two MPSs and the silicon substrate; the thin film protection resistor is located in the passivation layer; the first interconnection metal connects the first end of the resistor with the cathode of the reverse amplitude limiting diode; the second interconnection metal forms a voltage input end, a voltage output end, a first reference voltage end and a second reference voltage end, the cathode of the forward amplitude limiting diode is connected with the first reference voltage end, and the anode of the forward amplitude limiting diode, the cathode of the reverse amplitude limiting diode and the first end of the thin film protection resistor are connected with the voltage output end. And the anode of the reverse amplitude limiting diode is connected with a second reference voltage end, and the second end of the resistor is connected with the voltage input end 1. The diode amplitude limiting unit provided by the invention has relatively high voltage resistance and can be applied to a high-power condition.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first conductor, a metal oxide over the first conductor, a second conductor over the metal oxide, a first insulator, a second insulator over the first insulator, and a third conductor over the second insulator. The first conductor includes a region overlapping with the metal oxide. The metal oxide has a first opening. The second conductor has a second opening. The first opening and the second opening overlap with each other. The first insulator is placed on the inner side of each of the first opening and the second opening. The second insulator is placed in a depressed portion of the first insulator. The third conductor is placed in a depressed portion of the second insulator.

Provided is a semiconductor device capable of high integration. The semiconductor device includes first to third conductive layers, a semiconductor layer, first to third insulating layers, and a capacitor. The first insulating layer is positioned above the first conductive layer. The semiconductor layer has a vertical portion in contact with a side surface of the first insulating layer and a horizontal portion in contact with a top surface. The second conductive layer is positioned above the first insulating layer and in contact with the vertical portion. The second insulating layer, the third conductive layer, and the third insulating layer cover the vertical portion and the horizontal portion. The capacitor is positioned below the horizontal portion and includes a portion of the first conductive layer, a fourth conductive layer, and a fourth insulating layer therebetween. The first conductive layer includes a first conductive film and a second conductive film on the first conductive film. The semiconductor layer contains a first metal oxide and is in contact with the second conductive film. The second conductive film contains a second metal oxide, and the first conductive film contains a metal.

The utility model discloses a double-layer twisted type shielding layer breaking prevention combination cable, which comprises an inner-layer cable core body formed by twisting two coaxial cable cores and two nylon resin filling cores, wherein the outer part of the inner-layer cable core body is coated with a PTFE (Polytetrafluoroethylene) semi-directional belt inner wrapping antifriction layer; the four power wire cores, the two control wire cores and the four nylon resin filling cores are twisted around the outer portion of the PTFE semi-directional belt inner wrapping antifriction layer to form an outer layer wire core body, and the outer portion of the outer layer wire core body is sequentially coated with a PTFE semi-directional belt outer wrapping antifriction layer, a metal wire mixed weaving total shielding layer, a TPU extruded inner sheath layer, a galvanized steel wire armor layer and a TPU extruded outer sheath layer. According to the combination cable, the assembly structure of the power wire cores, the control wire cores and the coaxial wire cores in the cable core is optimized in a double-layer mode, double-layer twisting is carried out, the bending resistance is better, wire breaking and core breaking are avoided, the structure of the branch shielding layer and the structure of the total shielding layer are optimized, shielding layer wire breaking can be restrained, the stable shielding performance is guaranteed, and the durability is better.

A transistor with good electric characteristics, a transistor with a large on-state current, or a transistor with small parasitic capacitance is provided. The present invention is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer over the first conductive layer, a second insulating layer over the oxide semiconductor layer and the first insulating layer, and the third conductive layer over the second insulating layer, wherein the first insulating layer and the second conductive layer include a first opening portion at a position overlapping with the first conductive layer, the second conductive layer includes a first layer and a second layer covering a top surface and side surfaces of the first layer, the oxide semiconductor layer has a portion over the second layer, a portion over the first conductive layer in the first opening portion, a portion covering a side wall of the first insulating layer in the first opening portion, and a portion facing a side surface of the first layer with the second layer interposed therebetween in the first opening portion, and the third conductive layer faces the oxide semiconductor layer with the second insulating layer interposed therebetween in the first opening portion.

The invention discloses a novel silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The novel silicon carbide MOSFET device comprises an N + type heavily-doped silicon carbide substrate, a P type buried layer, an N-type lightly-doped primary epitaxy, a silicon dioxide buried layer, a P-type lightly-doped secondary epitaxy, a polycrystalline silicon deep groove, an N + type heavily-doped source region, a gate oxide layer, a polycrystalline silicon gate, a dielectric layer, front metal and back metal, different from the structure and the technological process of a traditional silicon carbide power MOSFET device, the factor that the channel length is unstable due to the fact that the P-type well region is subjected to long-time high-temperature transverse diffusion is avoided, and the gate oxide quality and reliability are improved; meanwhile, the area of a single device is reduced, the integration level is improved, more devices can be manufactured on the same wafer, the manufacturing cost is reduced, and the new structure can also reduce the on resistance of the devices, improve the switching speed and reduce the power consumption.