61results about How to "Excellent electrical properties" patented technology

The invention discloses high-density ultra-thin electronic-grade glass fiber cloth, and relates to the technical field of glass fiber cloth preparation, the high-density ultra-thin electronic-grade glass fiber cloth is formed by weaving warp yarns and weft yarns with the monofilament diameter of 4.0 microns, the warp and weft density is 90-100 pieces / inch, an air jet loom is combined with an auxiliary air jet mechanism for plain weaving, and it is guaranteed that fibers are tightly arranged; the preparation method comprises the steps of low-speed warping, weaving, desizing, deep splitting, cleaning and surface treatment. During weaving, through low-tension control and low-pressure airflow assistance, the fabric structure is more compact and uniform; a three-step method is adopted to gradually eliminate most slurry, and the slurry is further removed through liquefaction desizing; splitting and cleaning adopt a water flow and air flow combined mode, so that fiber opening is ensured, and the slurry residue rate is reduced to the minimum; finally, the strength of the high-density ultrathin electronic-grade glass fiber cloth is improved through treatment of a silane coupling agent; and low-tension and extremely low-slurry-residue-rate weaving of the high-density ultrathin electronic-grade glass fiber cloth is realized.

The invention relates to the technical field of copper alloy strips, and discloses a vehicle-mounted connector copper alloy strip which comprises the following components in percentage by mass: 0.04 to 0.1 weight percent of Y, 1.5 to 3.5 weight percent of Sn, 0.02 to 0.08 weight percent of P, 0.5 to 2.5 weight percent of carbon nanostructure X and the balance of copper and inevitable impurities, wherein the carbon nano structure X is a compound of a carbon nano tube and fullerene, and the mass ratio of the carbon nano tube to the fullerene is (2-4): 1; the invention also discloses a preparation method. According to the invention, through the comprehensive advantages in the aspects of conductivity and corrosion resistance, the electrical connection function can be stably and reliably realized in a vehicle-mounted connector, powerful hardware support is provided for the intelligent and electric development of an automobile, and the adaptability and safety of the automobile under different working conditions are enhanced; and the maintenance cost of the automobile is reduced, and the downtime caused by faults is shortened.

The invention discloses a low-cost all-vertical gallium nitride Schottky barrier diode and a preparation method thereof. The diode comprises a transmission layer; the drift layer is located on the lower surface of the transmission layer; the positive electrode is located in the middle of the lower surface of the drift layer; the negative electrode is located in the middle of the transmission layer; the first dielectric layer is located on the lower surface of the remaining drift layer and the side wall and part of the lower surface of the positive electrode; the second dielectric layer is located on the upper surface of the remaining transmission layer and the side wall and part of the upper surface of the negative electrode; the positive electrode thickening layer is located on the lower surface of the first dielectric layer and the lower surfaces of the remaining negative electrodes; the conductive substrate is positioned on the lower surface of the positive electrode thickening layer; the additional positive electrode is positioned in the middle of the lower surface of the conductive substrate; the negative electrode thickening layer is located on the upper surface of a part of the second dielectric layer and the upper surface of the remaining negative electrode. According to the invention, a completely longitudinal conductive vertical device structure is realized, the forward current density of the device is improved, and the on-resistance is reduced.

A flexible circuit board includes a substrate, a plurality of circuit patterns disposed on the substrate, and a protective layer disposed on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness greater than 8 µm and less than or equal to 25 µm, and wherein a thickness deviation between the plurality of circuit patterns is 0.5 µm to 3 µm. When the flexible circuit board is connected with a display panel, the display panel can have high performance and high current can flow through the display panel. The circuit pattern having the features according to the present invention is prevented from being damaged by high current.

Provided are: an anion exchange resin with which it is possible to produce an electrolyte membrane, a binder for forming an electrode catalyst layer, and a battery electrode catalyst layer, each of which has excellent electrical characteristics (anionic conductivity) and chemical characteristics (air permeability and water-containing properties); and an electrolyte membrane and a binder for forming an electrode catalyst layer, each of which is formed from the anion exchange resin. And a battery electrode catalyst layer formed from the binder for forming an electrode catalyst layer. For example, an anion exchange resin is used that contains: a hydrophobic unit in which a divalent hydrophobic group containing a bisphenol residue having an alicyclic structure is repeated via a carbon-carbon bond; a hydrophobic unit in which a divalent hydrophobic group comprising a plurality of aromatic rings bonded to each other via a divalent fluorine-containing hydrocarbon group is repeated via a carbon-carbon bond; and a hydrophilic unit having a fluorene ring bonded to a group containing an anion exchange group, the three units being bonded via a carbon-carbon bond.

The present specification discloses an electrode assembly and a secondary battery. The electrode assembly can exhibit low resistance and excellent electrical characteristics in a normal state, and ensure stability by rapidly transitioning to an insulator in an abnormal state. The present specification also discloses a secondary battery including the electrode assembly.

A semiconductor device and a method for manufacturing the same are disclosed. According to an embodiment, the semiconductor device may include: an SOI substrate; a channel portion on the SOI substrate, the channel portion including a two-dimensional semiconductor material layer; a gate stack on the channel portion; and source / drain portions on the SOI substrate, located on opposite sides of the gate stack and disposed at opposite ends of the channel portion, wherein the two-dimensional semiconductor material layer is on the bottom surface and side surface of the gate stack, and extends on the side surface of the source / drain portion thereby being located between the side surface of the source / drain portion and the side surface of the gate stack.

An example of a semiconductor device includes a substrate; a channel layer on the substrate; a first barrier layer on the channel layer; a second barrier layer on the first barrier layer; a third barrier layer on the second barrier layer and extending into a portion of the first barrier layer and a portion of the second barrier layer; a gate electrode on the third barrier layer; and a source electrode and a drain electrode on either side of the gate electrode, wherein each of the source electrode and the drain electrode extends into a first portion of the third barrier layer and is connected to the second barrier layer, and wherein the second barrier layer is doped with silicon.

The application relates to a crimping IGBT three-level power unit structure based on phase change cooling, wherein a phase change cooling power assembly and a supporting capacitor assembly are arranged in sequence from front to back, a three-level valve string is horizontally placed, power devices are arranged between adjacent phase change cooling radiators, the phase change cooling radiators are vertically placed, phase change working medium connecting pipes are arranged at the upper part and the lower part of the three-level valve string, a valve string direct current connection row is arranged at the rear end of the three-level valve string, the connection terminals of the valve string direct current connection row are located above the three-level valve string and are in a leading direction, an output row is arranged at the front end of the three-level valve string, and the connection terminals of the output row are located on the side of the three-level valve string. The application has the advantages that the valve string direct current connection row and the valve string capacitor connection row of the supporting capacitor assembly are overlapped on the top between the phase change cooling power assembly and the supporting capacitor assembly, the connection terminals of the valve string capacitor connection row are in a leading direction, the phase change cooling power assembly can be disassembled on the front side of a cabinet body, and maintenance is easy.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first conductor, a metal oxide over the first conductor, a second conductor over the metal oxide, a first insulator, a second insulator over the first insulator, and a third conductor over the second insulator. The first conductor includes a region overlapping with the metal oxide. The metal oxide has a first opening. The second conductor has a second opening. The first opening and the second opening overlap with each other. The first insulator is placed on the inner side of each of the first opening and the second opening. The second insulator is placed in a depressed portion of the first insulator. The third conductor is placed in a depressed portion of the second insulator.

Provided is a semiconductor device capable of high integration. The semiconductor device includes first to third conductive layers, a semiconductor layer, first to third insulating layers, and a capacitor. The first insulating layer is positioned above the first conductive layer. The semiconductor layer has a vertical portion in contact with a side surface of the first insulating layer and a horizontal portion in contact with a top surface. The second conductive layer is positioned above the first insulating layer and in contact with the vertical portion. The second insulating layer, the third conductive layer, and the third insulating layer cover the vertical portion and the horizontal portion. The capacitor is positioned below the horizontal portion and includes a portion of the first conductive layer, a fourth conductive layer, and a fourth insulating layer therebetween. The first conductive layer includes a first conductive film and a second conductive film on the first conductive film. The semiconductor layer contains a first metal oxide and is in contact with the second conductive film. The second conductive film contains a second metal oxide, and the first conductive film contains a metal.

A transistor with good electric characteristics, a transistor with a large on-state current, or a transistor with small parasitic capacitance is provided. The present invention is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer over the first conductive layer, a second insulating layer over the oxide semiconductor layer and the first insulating layer, and the third conductive layer over the second insulating layer, wherein the first insulating layer and the second conductive layer include a first opening portion at a position overlapping with the first conductive layer, the second conductive layer includes a first layer and a second layer covering a top surface and side surfaces of the first layer, the oxide semiconductor layer has a portion over the second layer, a portion over the first conductive layer in the first opening portion, a portion covering a side wall of the first insulating layer in the first opening portion, and a portion facing a side surface of the first layer with the second layer interposed therebetween in the first opening portion, and the third conductive layer faces the oxide semiconductor layer with the second insulating layer interposed therebetween in the first opening portion.

This heating member comprises: a first substrate; a second substrate disposed on the first substrate; and a heating layer disposed between the first substrate and the second substrate, in which the heating layer includes conductive particles, a polymer covering the conductive particles, and a plurality of electrodes, and the first substrate and the second substrate have different thicknesses.

The present application relates to a kind of new near hemispherical probe and its preparation method, the near hemispherical probe can retain the excellent electrical characteristics of three-dimensional spherical structure, the area of collection electrode is small under the same electrode spacing, and the capacitance is low, and charge collection efficiency is almost independent of θ.Hemispherical electrode has good sealing, completely isolates detection sensitive area from substrate, dark current is not affected by wafer thickness, and extremely low noise is conducive to low-energy X-ray or low-energy particle detection.

Provided is a semiconductor device capable of achieving miniaturization or high integration. The semiconductor device includes a first conductor and a second conductor spaced apart from each other on an oxide, a third conductor in contact with a portion of a top surface of the first conductor, and a fourth conductor in contact with a portion of a top surface of the second conductor, the first insulator is arranged on the third conductor and the fourth conductor and is provided with an opening between the third conductor and the fourth conductor; the first insulator is arranged in the opening of the first insulator and is connected with the other part of the top surface of the first conductor and the other part of the top surface of the second conductor; a second insulator in contact with a side surface of the third conductor and a side surface of the fourth conductor; a third insulator in contact with a top surface of the oxide and side surfaces of the first conductor, the second conductor, and the second insulator; and a fifth conductor disposed on the third insulator. A distance between the first conductor and the second conductor is smaller than a distance between the third conductor and the fourth conductor, the second insulator includes a first layer and a second layer on the first layer, the first layer includes a nitride insulator, and the second layer includes an oxide insulator.

A semiconductor device capable of miniaturization or high integration is provided. The semiconductor device includes a capacitor and a transistor over the capacitor. The transistor includes a lower electrode and an upper electrode. A first interlayer film is provided between the lower electrode and the upper electrode. The first interlayer film includes a groove portion reaching the lower electrode. A metal oxide layer serving as a semiconductor layer of the transistor, a gate insulating layer, and a gate electrode have regions in the groove portion. A second interlayer film is provided over the gate electrode and the gate insulating layer, and a bit line is provided over the second interlayer film. The bit line is connected to the upper electrode. The groove portion and the gate electrode extend in a first direction. The bit line extends in a second direction perpendicular or substantially perpendicular to the first direction.

The invention belongs to the technical field of nano material preparation, discloses a zero-dimensional perovskite nanocrystalline large-scale preparation method based on a room-temperature self-assembly strategy, and aims to solve the technical problems that in the prior art, the uniformity of a product is poor, high luminous efficiency and conductivity are difficult to achieve at the same time, and the wavelength cannot be accurately regulated and controlled. According to the method, a water-in-oil microemulsion system is adopted as a nanoreactor, and the high uniformity of nanocrystal growth is fundamentally guaranteed through a confinement reaction. The composition creatively comprises two ligands: one ligand is a pi-conjugated conductive main functional ligand with surface passivation and charge transfer functions, which solves the problem of poor conductivity caused by the traditional insulating ligand while ensuring high photoluminescence efficiency, and the other ligand is a competitive tuning ligand which forms dynamic competitive balance with the main ligand. The key problems of product uniformity, conductivity, wavelength controllability and the like are synergistically solved, and the prepared nanocrystal has high optical purity, high quantum yield and excellent conductivity.

The utility model relates to the technical field of modules, in particular to a core module bonding pad for electronic component integration. Comprising a module main board, the module main board is provided with external expansion interface assemblies packaged by stamp holes, the external expansion assemblies are arranged on the periphery of the module main board, and the module main board is provided with a processor and an antenna interface assembly used for being connected with an antenna; according to the utility model, the external expansion interface assembly packaged by the stamp hole is adopted, the production difficulty and the production cost are reduced, the common communication function is integrated, charging, backlight, an indicating lamp, a flash lamp and a display screen high-low voltage circuit are integrated in one IC, the design without the IC at the periphery can be realized, only required functional devices are added, the integration level is high, and the design is simple. The module mainboard adopting the ten-layer HDI gold immersion technology can have good electrical characteristics and anti-interference characteristics, and work is stable and reliable.

The invention provides a current collector and application thereof. The present application can provide a current collector capable of forming an electrode which does not affect the performance and operation of a secondary battery by exhibiting excellent electrical characteristics including low resistance in a normal state, and which can secure stability by blocking energization of an electrode assembly by increasing resistance in an abnormal state, and a use thereof. The present application can also provide a current collector capable of ensuring excellent adhesive force between layers forming an electrode, and a use thereof.

A semiconductor device that is easily miniaturized is provided. A semiconductor device capable of achieving high integration is provided. The semiconductor device includes first to third conductive layers, a semiconductor layer, and first and second insulating layers. The first insulating layer is disposed on the first conductive layer and has a side surface on the first conductive layer. The semiconductor layer has a vertical portion that contacts the side surface of the first insulating layer and a horizontal portion that contacts the top surface of the first conductive layer. The second conductive layer is located above the first insulating layer and contacts the vertical portion. The second insulating layer covers the vertical and horizontal portions. The third conductive layer covers the vertical and horizontal portions through the second insulating layer. The first conductive layer includes a first conductive film and a second conductive film on the first conductive film. The semiconductor layer contains a first metal oxide and is in contact with the second conductive film. The second conductive film contains a second metal oxide, and the first conductive layer contains a metal.

A semiconductor device includes: a substrate; a plurality of semiconductor patterns on the substrate; a bit line in contact with a first end portion of each semiconductor pattern in the first direction and extending in a third direction perpendicular to an upper surface of the substrate; a plurality of word lines overlapping the plurality of semiconductor patterns in the third direction, respectively, and extending in a second direction intersecting the first direction; and a plurality of capacitors in contact with a second end portion of a corresponding semiconductor pattern of the plurality of semiconductor patterns along the first direction. Each word line includes a first conductive liner layer, a second conductive liner layer, and a conductive layer sequentially located on a corresponding semiconductor pattern of the plurality of semiconductor patterns, and the first conductive liner layer and the second conductive liner layer include materials different from each other or include the same material having a composition ratio different from each other.

A semiconductor device including a micro transistor and a method of manufacturing the same are provided. The semiconductor device includes first to third insulating layers, a transistor including a semiconductor layer, first to fourth conductive layers, and fourth to sixth insulating layers. The first conductive layer, the first insulating layer, the third conductive layer, the fifth insulating layer, the second insulating layer, the third insulating layer and the second conductive layer are sequentially overlapped. The first to third insulating layers, the second and third conductive layers having openings to the first conductive layer. The first insulating layer has a protruding portion within the opening, and the fourth insulating layer is in contact with a top surface of the first insulating layer, a side surface of the fifth insulating layer, and a side surface of the second insulating layer. A fifth insulating layer of an oxide of the third conductive layer is in contact with a top surface and a side surface of the third conductive layer. The semiconductor layer is in contact with the top surfaces of the first and second conductive layers and the side surface of the fourth insulating layer. The sixth insulating layer is in contact with a top surface of the semiconductor layer. The fourth conductive layer is in contact with the sixth insulating layer in a manner of overlapping with the opening.

The application discloses a PZT piezoelectric ceramic electrode and a preparation method of the electrode, and belongs to the technical field of piezoelectric ceramics. The method comprises the following steps: step one, taking a ceramic sheet with printed electrodes, passing air and heating to 450-550 DEG C, and keeping the temperature for 45-90 min; step two, increasing the air flow and continuously heating to 750-850 DEG C, and keeping the temperature for 10-30 min; step three, after the temperature keeping, cooling to 550-650 DEG C, passing nitrogen, and keeping the temperature for 3-5 min; and step four, reducing the nitrogen flow, cooling to normal temperature with the furnace, and taking out. The PZT piezoelectric ceramic electrode is prepared by using air and nitrogen, the number of oxygen vacancies in the ceramic crystal is increased by using nitrogen, the defects caused by the oxidation of the electrode surface and the micro defects in the glass phase are reduced, the dielectric loss of the ceramic is reduced, the electromechanical coupling coefficient of the ceramic is increased, the electrical characteristics of the piezoelectric ceramic sheet are improved, and the high-temperature stability and the silver layer adhesion of the piezoelectric ceramic are improved.

A magnetic wedge according to an embodiment of the present invention is a magnetic wedge for a rotary electric machine, the magnetic wedge comprising a plurality of flat magnetic metal particles and an inclusion phase, in a cross-section perpendicular to the longitudinal direction of the magnetic wedge and at the center in the longitudinal direction, the magnetic wedge includes flat magnetic metal surface particles having 10% or more of the length thereof arranged further outward than the average contour line in the width direction of the magnetic wedge.

Provided are a motherboard power supply module, a power supply method, a power supply device, and an electronic device. The motherboard power supply module includes a preset number of driving MOSs, the driving MOSs are divided into preset groups, each group includes two driving MOSs, and the two driving MOSs in each group share a first input capacitor; the two driving MOSs in each group are connected to a power supply through the shared first input capacitor; the output end of each driving MOS is connected to an inductor, and the output end of the inductor is connected to a load via at least one output capacitor. In this way, a larger first input capacitor can be used to reduce the price of the motherboard.

The invention discloses high-flash-point mineral insulating oil and a preparation method thereof, and belongs to the technical field of electric insulating oil. The high-flash-point mineral insulating oil comprises the following components in percentage by weight: 94-95% of mineral transformer oil, 2% of cresyl diphenyl phosphate, 1-2% of triphenyl phosphate, 1-2% of triphenyl phosphate and 1-2% of tributyl phosphate. The high-flash-point mineral insulating oil provided by the invention has the beneficial effects that the selected flame retardant is a harmless liquid substance, halogen compounds harmful to the environment are completely avoided, and the final high-flash-point mineral insulating oil can be quickly formed by directly mixing the flame retardant and the mineral oil without the help of any solubilizer and by utilizing a mechanical stirring mode.

The invention relates to a manufacturing method of a semiconductor device. Provided is a semiconductor device having a high operating speed. A method of manufacturing a semiconductor device includes: forming a first coating film on a first insulator and a second coating film on the first coating film; removing a part of the second coating film to form a first layer; forming a second layer by removing a portion of the first coating film using the first layer as a mask; performing a heat treatment process; forming a first oxide semiconductor so as to cover the top surface of the first insulator, the side surfaces of the second layer, and the side surfaces and the top surface of the first layer; processing the first oxide semiconductor by anisotropic etching to form a second oxide semiconductor in contact with a side surface of the second layer; removing the first layer; the second layer is removed to expose a side surface of the second oxide semiconductor covered by the second layer.

The invention discloses an enhanced multi-core connector and a manufacturing process thereof, and relates to the technical field of electronic connectors, and the enhanced multi-core connector comprises a connector insulation body which is internally provided with a plurality of conductive terminals; each conductive terminal comprises a contact part and a welding part; the reinforcing structure is integrated on the connector insulating body; the reinforcing structure comprises a plurality of metal reinforcing members, and the metal reinforcing members are embedded into key positions of the connector insulating body through a precision forming technology and are used for providing extra support and optimizing signal transmission efficiency; according to the technical scheme provided by the invention, the metal reinforcing members are embedded in the key positions of the connector insulating body, so that the tensile strength and the bending resistance of the connector are remarkably enhanced. The metal reinforcing member is prepared through a selective laser sintering technology, and a complex geometrical shape can be realized, so that a signal transmission path is optimized, and the mechanical stability of the connector is improved.

A data driver and a display device having the same are disclosed. The display device includes: a display panel configured to display an image and including pixels and data lines connected to the pixels; a timing controller configured to provide image data corresponding to the image; and a data driver including at least one output buffer configured to output an analog data voltage corresponding to the image data to a channel electrically connected to the data line. The output buffer includes: one or more transistors for applying a preset rising current or falling current to an output node connected to the channel to output a data voltage; and a capacitance adjustment circuit configured to adjust a capacitance of the output node based on a magnitude or rate of a data voltage change between adjacent pixel rows.