33results about How to "Excellent electrical properties" patented technology

A flexible circuit board includes a substrate, a plurality of circuit patterns disposed on the substrate, and a protective layer disposed on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness greater than 8 µm and less than or equal to 25 µm, and wherein a thickness deviation between the plurality of circuit patterns is 0.5 µm to 3 µm. When the flexible circuit board is connected with a display panel, the display panel can have high performance and high current can flow through the display panel. The circuit pattern having the features according to the present invention is prevented from being damaged by high current.

The present specification discloses an electrode assembly and a secondary battery. The electrode assembly can exhibit low resistance and excellent electrical characteristics in a normal state, and ensure stability by rapidly transitioning to an insulator in an abnormal state. The present specification also discloses a secondary battery including the electrode assembly.

A semiconductor device and a method for manufacturing the same are disclosed. According to an embodiment, the semiconductor device may include: an SOI substrate; a channel portion on the SOI substrate, the channel portion including a two-dimensional semiconductor material layer; a gate stack on the channel portion; and source / drain portions on the SOI substrate, located on opposite sides of the gate stack and disposed at opposite ends of the channel portion, wherein the two-dimensional semiconductor material layer is on the bottom surface and side surface of the gate stack, and extends on the side surface of the source / drain portion thereby being located between the side surface of the source / drain portion and the side surface of the gate stack.

An example of a semiconductor device includes a substrate; a channel layer on the substrate; a first barrier layer on the channel layer; a second barrier layer on the first barrier layer; a third barrier layer on the second barrier layer and extending into a portion of the first barrier layer and a portion of the second barrier layer; a gate electrode on the third barrier layer; and a source electrode and a drain electrode on either side of the gate electrode, wherein each of the source electrode and the drain electrode extends into a first portion of the third barrier layer and is connected to the second barrier layer, and wherein the second barrier layer is doped with silicon.

The application relates to a crimping IGBT three-level power unit structure based on phase change cooling, wherein a phase change cooling power assembly and a supporting capacitor assembly are arranged in sequence from front to back, a three-level valve string is horizontally placed, power devices are arranged between adjacent phase change cooling radiators, the phase change cooling radiators are vertically placed, phase change working medium connecting pipes are arranged at the upper part and the lower part of the three-level valve string, a valve string direct current connection row is arranged at the rear end of the three-level valve string, the connection terminals of the valve string direct current connection row are located above the three-level valve string and are in a leading direction, an output row is arranged at the front end of the three-level valve string, and the connection terminals of the output row are located on the side of the three-level valve string. The application has the advantages that the valve string direct current connection row and the valve string capacitor connection row of the supporting capacitor assembly are overlapped on the top between the phase change cooling power assembly and the supporting capacitor assembly, the connection terminals of the valve string capacitor connection row are in a leading direction, the phase change cooling power assembly can be disassembled on the front side of a cabinet body, and maintenance is easy.

Provided is a semiconductor device capable of high integration. The semiconductor device includes first to third conductive layers, a semiconductor layer, first to third insulating layers, and a capacitor. The first insulating layer is positioned above the first conductive layer. The semiconductor layer has a vertical portion in contact with a side surface of the first insulating layer and a horizontal portion in contact with a top surface. The second conductive layer is positioned above the first insulating layer and in contact with the vertical portion. The second insulating layer, the third conductive layer, and the third insulating layer cover the vertical portion and the horizontal portion. The capacitor is positioned below the horizontal portion and includes a portion of the first conductive layer, a fourth conductive layer, and a fourth insulating layer therebetween. The first conductive layer includes a first conductive film and a second conductive film on the first conductive film. The semiconductor layer contains a first metal oxide and is in contact with the second conductive film. The second conductive film contains a second metal oxide, and the first conductive film contains a metal.

A transistor with good electric characteristics, a transistor with a large on-state current, or a transistor with small parasitic capacitance is provided. The present invention is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer over the first conductive layer, a second insulating layer over the oxide semiconductor layer and the first insulating layer, and the third conductive layer over the second insulating layer, wherein the first insulating layer and the second conductive layer include a first opening portion at a position overlapping with the first conductive layer, the second conductive layer includes a first layer and a second layer covering a top surface and side surfaces of the first layer, the oxide semiconductor layer has a portion over the second layer, a portion over the first conductive layer in the first opening portion, a portion covering a side wall of the first insulating layer in the first opening portion, and a portion facing a side surface of the first layer with the second layer interposed therebetween in the first opening portion, and the third conductive layer faces the oxide semiconductor layer with the second insulating layer interposed therebetween in the first opening portion.

This heating member comprises: a first substrate; a second substrate disposed on the first substrate; and a heating layer disposed between the first substrate and the second substrate, in which the heating layer includes conductive particles, a polymer covering the conductive particles, and a plurality of electrodes, and the first substrate and the second substrate have different thicknesses.

The present application relates to a kind of new near hemispherical probe and its preparation method, the near hemispherical probe can retain the excellent electrical characteristics of three-dimensional spherical structure, the area of collection electrode is small under the same electrode spacing, and the capacitance is low, and charge collection efficiency is almost independent of θ.Hemispherical electrode has good sealing, completely isolates detection sensitive area from substrate, dark current is not affected by wafer thickness, and extremely low noise is conducive to low-energy X-ray or low-energy particle detection.

A semiconductor device capable of miniaturization or high integration is provided. The semiconductor device includes a capacitor and a transistor over the capacitor. The transistor includes a lower electrode and an upper electrode. A first interlayer film is provided between the lower electrode and the upper electrode. The first interlayer film includes a groove portion reaching the lower electrode. A metal oxide layer serving as a semiconductor layer of the transistor, a gate insulating layer, and a gate electrode have regions in the groove portion. A second interlayer film is provided over the gate electrode and the gate insulating layer, and a bit line is provided over the second interlayer film. The bit line is connected to the upper electrode. The groove portion and the gate electrode extend in a first direction. The bit line extends in a second direction perpendicular or substantially perpendicular to the first direction.

The invention belongs to the technical field of nano material preparation, discloses a zero-dimensional perovskite nanocrystalline large-scale preparation method based on a room-temperature self-assembly strategy, and aims to solve the technical problems that in the prior art, the uniformity of a product is poor, high luminous efficiency and conductivity are difficult to achieve at the same time, and the wavelength cannot be accurately regulated and controlled. According to the method, a water-in-oil microemulsion system is adopted as a nanoreactor, and the high uniformity of nanocrystal growth is fundamentally guaranteed through a confinement reaction. The composition creatively comprises two ligands: one ligand is a pi-conjugated conductive main functional ligand with surface passivation and charge transfer functions, which solves the problem of poor conductivity caused by the traditional insulating ligand while ensuring high photoluminescence efficiency, and the other ligand is a competitive tuning ligand which forms dynamic competitive balance with the main ligand. The key problems of product uniformity, conductivity, wavelength controllability and the like are synergistically solved, and the prepared nanocrystal has high optical purity, high quantum yield and excellent conductivity.

The utility model relates to the technical field of modules, in particular to a core module bonding pad for electronic component integration. Comprising a module main board, the module main board is provided with external expansion interface assemblies packaged by stamp holes, the external expansion assemblies are arranged on the periphery of the module main board, and the module main board is provided with a processor and an antenna interface assembly used for being connected with an antenna; according to the utility model, the external expansion interface assembly packaged by the stamp hole is adopted, the production difficulty and the production cost are reduced, the common communication function is integrated, charging, backlight, an indicating lamp, a flash lamp and a display screen high-low voltage circuit are integrated in one IC, the design without the IC at the periphery can be realized, only required functional devices are added, the integration level is high, and the design is simple. The module mainboard adopting the ten-layer HDI gold immersion technology can have good electrical characteristics and anti-interference characteristics, and work is stable and reliable.

A semiconductor device that is easily miniaturized is provided. A semiconductor device capable of achieving high integration is provided. The semiconductor device includes first to third conductive layers, a semiconductor layer, and first and second insulating layers. The first insulating layer is disposed on the first conductive layer and has a side surface on the first conductive layer. The semiconductor layer has a vertical portion that contacts the side surface of the first insulating layer and a horizontal portion that contacts the top surface of the first conductive layer. The second conductive layer is located above the first insulating layer and contacts the vertical portion. The second insulating layer covers the vertical and horizontal portions. The third conductive layer covers the vertical and horizontal portions through the second insulating layer. The first conductive layer includes a first conductive film and a second conductive film on the first conductive film. The semiconductor layer contains a first metal oxide and is in contact with the second conductive film. The second conductive film contains a second metal oxide, and the first conductive layer contains a metal.

A semiconductor device includes: a substrate; a plurality of semiconductor patterns on the substrate; a bit line in contact with a first end portion of each semiconductor pattern in the first direction and extending in a third direction perpendicular to an upper surface of the substrate; a plurality of word lines overlapping the plurality of semiconductor patterns in the third direction, respectively, and extending in a second direction intersecting the first direction; and a plurality of capacitors in contact with a second end portion of a corresponding semiconductor pattern of the plurality of semiconductor patterns along the first direction. Each word line includes a first conductive liner layer, a second conductive liner layer, and a conductive layer sequentially located on a corresponding semiconductor pattern of the plurality of semiconductor patterns, and the first conductive liner layer and the second conductive liner layer include materials different from each other or include the same material having a composition ratio different from each other.

The application discloses a PZT piezoelectric ceramic electrode and a preparation method of the electrode, and belongs to the technical field of piezoelectric ceramics. The method comprises the following steps: step one, taking a ceramic sheet with printed electrodes, passing air and heating to 450-550 DEG C, and keeping the temperature for 45-90 min; step two, increasing the air flow and continuously heating to 750-850 DEG C, and keeping the temperature for 10-30 min; step three, after the temperature keeping, cooling to 550-650 DEG C, passing nitrogen, and keeping the temperature for 3-5 min; and step four, reducing the nitrogen flow, cooling to normal temperature with the furnace, and taking out. The PZT piezoelectric ceramic electrode is prepared by using air and nitrogen, the number of oxygen vacancies in the ceramic crystal is increased by using nitrogen, the defects caused by the oxidation of the electrode surface and the micro defects in the glass phase are reduced, the dielectric loss of the ceramic is reduced, the electromechanical coupling coefficient of the ceramic is increased, the electrical characteristics of the piezoelectric ceramic sheet are improved, and the high-temperature stability and the silver layer adhesion of the piezoelectric ceramic are improved.

A data driver and a display device having the same are disclosed. The display device includes: a display panel configured to display an image and including pixels and data lines connected to the pixels; a timing controller configured to provide image data corresponding to the image; and a data driver including at least one output buffer configured to output an analog data voltage corresponding to the image data to a channel electrically connected to the data line. The output buffer includes: one or more transistors for applying a preset rising current or falling current to an output node connected to the channel to output a data voltage; and a capacitance adjustment circuit configured to adjust a capacitance of the output node based on a magnitude or rate of a data voltage change between adjacent pixel rows.

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a conductive column, a capacitor structure and a plurality of dummy columnar structures. The conductive pillar is disposed in the substrate. The capacitor structure is disposed in the substrate and is separated from the conductive pillar. The dummy pillar structures are randomly distributed between the conductive pillars and the capacitor structures.

A chip resistor capable of achieving both high specific resistance, a low TCR is provided. A chip resistor includes: an insulating substrate; a resistive layer formed of an alloy containing Cr, Si, and N, the resistive layer being provided on the insulating substrate; and a first high-nitrogen-containing layer provided on the resistive layer, the first high-nitrogen-containing layer being made of an alloy having a N atomic percentage higher than a N atomic percentage of the resistive layer.

A semiconductor memory device includes a bit line (BL) extending in a first direction (Dl), a channel pattern (CP) on the bit line, the channel pattern including first and second vertical portions (VP1, VP2) facing each other and a horizontal portion (HP) connecting the first and second vertical portions, first and second word lines (WL1, WL2) provided on the horizontal portion and between the first and second vertical portions and extended in a second direction (D2) crossing the bit line, and a gate insulating pattern (Gox) provided between the first word line and the channel pattern and between the second word line and the channel pattern.

This invention discloses a method for element doping of a thin-film solar cell and its absorber layer, relating to the field of thin-film solar cell technology. By immersing the activated absorber layer in a salt solution of a predetermined dopant element and simultaneously applying an exogenous inducing variable, the predetermined element is doped. During the doping process, the diffusion of dopant ions into the grain boundaries and lattice interior of the absorber layer is promoted, ensuring that the element is not affected by the surface morphology, hydrophilicity / hydrophobicity, internal or edge structure of the absorber layer. This solves the problems of difficult-to-control element doping uniformity, poor process stability, and low effective doping activation rate in existing technologies. It achieves the goal of diffusive doping of p-type elements in the absorber layer with high doping uniformity, high doping activation rate, controllable doping process, and compatibility with existing processes.

A high-frequency module (1) includes: a module substrate (91) having main surfaces (91a, 91b); one or more module components disposed on the main surface (91a); a resin member (92) covering the main surface (91a); and a metal shielding layer (95) covering top surfaces of the resin member (92) and the one or more module components and set to a ground potential. A sub-module component (190) as one of the one or more module components includes: a sub-module substrate (191) having main surfaces (191a, 191b); a first circuit component disposed on the main surface (191a); one or more second circuit components disposed on the main surface (191a or 191b); a resin member (192) covering the main surface (191a); and a side surface shielding layer (194) covering side surfaces of the resin member (192) and the sub-module substrate (191) and set to the ground potential. An end surface of the side surface shielding layer (194) on a top surface side is in contact with the metal shielding layer (95).

The invention relates to the field of integrated circuit design, and provides an integrated circuit layout and wiring design method and system. The method comprises the steps of firstly obtaining an integrated circuit layout and identifying a target area in the layout; querying a preset deviation table according to the target area, and obtaining a corresponding resistance correction coefficient and a capacitance correction coefficient; for each candidate wiring path, calculating a first cost based on the wiring length, the congestion degree and the time sequence delay, and calculating a compensation cost in combination with the correction coefficient; taking the sum of the first cost and the compensation cost as total cost, and selecting a wiring path according to the total cost; if the selected path passes through the target area, line width and / or line spacing adjustment is carried out on line segments in the area; physical effect deviation of a specific area can be actively compensated in the design stage, path selection and geometric parameters are optimized, and therefore circuit performance and reliability are improved.

This invention provides a semiconductor device with minimal deviation in transistor characteristics. The invention provides a semiconductor device including a transistor, wherein the transistor includes: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide; a second insulator on the second oxide; and a third conductor on the second insulator, wherein the top surface of the first oxide in the region overlapping with the third conductor is lower than the top surface of the first oxide in the region overlapping with the first conductor, and in the region overlapping with the third conductor, a curved surface is formed between the side surface and the top surface of the first oxide, the radius of curvature of the curved surface being 1 nm or more and 15 nm or less.

This invention discloses a PSA aptamer sensor based on a screen-printed electrode, its preparation, and detection method. In this invention, a composite material of AuNPs and graphene aerogel is used to modify the surface of a screen-printed electrode. The aptamer is modified onto the sensor by forming gold-sulfur (Au-S) bonds with a thiol-modified DNA single-stranded aptamer. Excess gold active sites are blocked with MCH to construct the PSA aptamer sensor. A certain concentration of PSA and UA is selected and incubated with the sensor. The EIS test method is used to detect PSA by recording its impedance changes, and the detection limit of the sensor is obtained. Utilizing the advantages of large-scale mass production and low cost of screen printing technology, combined with the excellent physical and electrical properties of nanomaterials, an electrochemical sensor for the detection of prostate-specific antigen (PSA) is prepared, enabling convenient, efficient, and low-cost detection, providing a new approach for prostate cancer patients to be detected outside of hospitals and laboratories.

The present application relates to a growth inhibitor for film formation, a film formation method using the same, and a semiconductor substrate manufactured thereby. Specifically, it relates to a growth inhibitor for film formation which is a compound represented by Chemical Formula 1, a film formation method using the same, and a semiconductor substrate manufactured thereby, [Chemical Formula 1] AnB m X o Y i Z j wherein A is carbon or silicon; B is hydrogen or an alkyl group having 1 to 3 carbon atoms; X is one or more selected from fluorine, chlorine, bromine, and iodine; Y and Z are each independently one or more selected from oxygen, nitrogen, sulfur, and fluorine, and are different from each other; n is an integer of 1 to 15; o is an integer of 1 or more; m is 0 to 2n+1; i and j are each an integer of 0 to 3. The present application can suppress side reactions, reduce film growth rate, and remove process by-products in the film, thereby greatly improving step coverage and thickness uniformity of the film even when forming a film on a substrate having a complex structure.

Disclosed are a semiconductor device and a manufacturing method thereof. According to an embodiment, the semiconductor device can include a substrate, a buried oxide layer, a channel portion including a semiconductor layer, a source / drain portion, and a gate stack. The semiconductor layer includes a shell portion and a core portion spaced apart from each other and distributed in a projection direction overlapping each other, the shell portion being on the core portion, the shell portion and the core portion being respectively one of p-type doped and n-type doped.

The present disclosure provides semiconductor devices. A method of manufacturing a memory device includes sequentially forming a primary selector device layer, a primary intermediate electrode layer, and a primary variable resistance layer on a substrate and then etching the primary selector device layer, the primary intermediate electrode layer, and the primary variable resistance layer, thereby forming a selector device, an intermediate electrode, and a variable resistance layer. At least one of a side portion of the selector device and a side portion of the variable resistance layer is removed such that a first width of the intermediate electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selector device in the first direction. A cap layer is formed on at least one of a sidewall of the etched side portion of the selector device and a sidewall of the etched side portion of the variable resistance layer.

The invention belongs to the technical field of semiconductor technology and neuromorphic hardware, and discloses a metal halide film memristor and a preparation method and application thereof, and the metal halide film memristor provided by the invention comprises a bottom electrode, an inorganic resistive layer and a top electrode from bottom to top in sequence; the inorganic resistive layer is a metal halide thin film, and the metal halide thin film is a cuprous iodide thin film; the bottom electrode is made of indium tin oxide (ITO) and is used for inputting an electric signal of an external power supply; the top electrode is made of metal copper and is used for being connected with the ground; the cuprous iodide film is prepared by adopting a vacuum physical vapor deposition method; the metal halide film memristor provided by the invention can reach a large dynamic range of 6306 under-1V voltage stimulation, response current is at a microampere level, and the metal halide film memristor can be used for realizing neuron integral-emission function simulation due to good volatile characteristics and can be applied to a self-adaptive sensing system.

A light emitting device, a method of manufacturing the same, and a display apparatus including the same are provided. The light emitting device includes a first semiconductor layer doped with a dopant of a first polarity and including a first portion extending in a first direction and a second portion connected to one side of the first portion, a second semiconductor layer doped with a dopant of a second polarity different from the first polarity, an active layer disposed between the first semiconductor layer and the second semiconductor layer, and an insulating film disposed to surround at least an outer surface of the active layer and extend in the first direction, wherein a diameter of the second portion measured in a second direction perpendicular to the first direction is greater than a diameter of the first portion measured in the second direction, and a side surface of the second portion is inclined.