86 results about "Diffusion barrier" patented technology

This invention provides a PVD-grown undoped ε-Ga₂O₃ thin film and its preparation method. The preparation method includes the following steps: Step S1, preparing a substrate and target material, and placing them in the main deposition chamber of a physical vapor deposition (PVD) apparatus; Step S2, heating the substrate to above 650°C, introducing oxygen as the growth atmosphere gas, and using a gallium oxide target material with a tin atomic ratio of 0.5-2.5% to deposit a first thin film on the substrate; Step S3, depositing an aluminum oxide layer as a diffusion barrier layer on the surface of the first thin film; Step S4, using a pure gallium oxide target material, depositing a thin film on the surface of the aluminum oxide layer; cooling to room temperature to obtain the undoped ε-Ga₂O₃ thin film. The undoped ε-Ga₂O₃ photodetector prepared by the pulsed laser deposition system of this invention has a much higher PDCR value than tin-doped ε-Ga₂O₃ devices.

A method for forming a gate structure according to embodiments of the present disclosure includes: receiving a precursor structure, the precursor structure including a substrate, a first nanostructure located above a first region of the substrate, and a second nanostructure located above a second region of the substrate; depositing a gate dielectric layer over the first nanostructure and the second nanostructure; depositing a first work function metal layer over the first nanostructure and the second nanostructure; depositing a diffusion barrier layer over the first work function metal layer; selectively removing the diffusion barrier layer and the first work function metal layer from the first nanostructure above the first region; depositing a second work function metal layer over the first nanostructure and the second nanostructure; and depositing a metal filler layer over the second work function metal layer. Embodiments of this application also relate to semiconductor structures and methods for forming the same.

A CdTe based thin film solar cell device (10) and a method for manufacturing it in superstrate configuration are provided. The CdTe based thin film solar cell device (10) comprises a CdTe based absorber layer (13) comprising a first partial layer (131) being a selenium-rich CdTe layer, a second partial layer (133) having a smaller selenium content than the first partial layer (131), and a diffusion barrier layer (132) between the first partial layer (131) and the second partial layer (133). The diffusion barrier layer (132) is a layer having a band gap larger than that of the first partial layer (131) and a crystal structure differing from the crystal structure of the first partial layer (131). The method for manufacturing comprises a step of forming the CdTe based absorber layer (131), wherein this step comprises depositing a first layer, a second layer and a third layer and performing a thermal treatment after depositing all of these layers. As a result of the thermal treatment, the first partial layer (131) is formed from the first layer, the diffusion barrier layer (132) is formed from the second layer and the second partial layer (133) is formed from the third layer.

A semiconductor device includes an insulating layer having formed therein a gate electrode and overlying a substrate, a stack of a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer overlying a top surface of the gate electrode, and a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. The dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a dielectric compound of silicon, and suppresses loss of metallic elements during subsequent anneal processes.

The disclosed technology generally relates to semiconductor structures and their fabrication, and more particularly to diffusion barrier structures containing Ti, Si, N and methods of forming same. A method of forming an electrically conductive diffusion barrier comprises providing a substrate in a reaction chamber and forming a titanium silicide (TiSi) region on the substrate by alternatingly exposing the substrate to a titanium-containing precursor and a first silicon-containing precursor. The method additionally comprises forming a titanium silicon nitride (TiSiN) region on the TiSi region by alternatingly exposing the substrate to a titanium-containing precursor, a nitrogen-containing precursor and a second silicon-containing precursor. The method can optionally include, prior to forming the TiSi region, forming a titanium nitride (TiN) region by alternatingly exposing the substrate to a titanium-containing precursor and a nitrogen-containing precursor.

This invention relates to the field of nickel electrode paste preparation technology, and discloses an ultrafine roller-printed nickel paste for ultra-high capacitance MLCCs and its preparation method. The nickel paste includes nickel powder, Ni3Sn-coated nickel powder, diffusion barrier phase, resin, solvent, dispersant, and rheology modifier. The Ni3Sn-coated nickel powder is obtained by chemical plating, where Sn is bonded to Ni in the form of an intermetallic compound. The diffusion barrier phase is selected from nano-ZrO2 or TiO2 particles. After pre-dispersing each solid component with a portion of the dispersant and solvent, the mixture is ground and dispersed using a gradient grinding process, then mixed with an organic carrier to form a paste. After vacuum degassing and filtration, the nickel paste is obtained. This invention uses Ni3Sn-coated nickel powder to replace elemental Sn powder, inhibiting the formation of a dense SnO2 passivation layer. Combined with the blocking effect of the diffusion barrier phase at the grain boundaries and the protection of the coating layer integrity by the gradient grinding process, this invention solves the problem of long-term reliability degradation of MLCCs caused by Sn storage.

Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

In an embodiment, a semiconductor device is provided that includes a semiconductor substrate having a first major surface and a metallization structure located on the first major surface. The metallization structure includes one or more electrically conductive structures having a metallic diffusion barrier layer and a copper layer located on the metallic diffusion barrier layer. The metallic diffusion barrier layer has a thickness t, an upper surface, a lower surface, and a side face extending between an upper edge formed between the upper surface and the side face and a lower edge formed between the lower surface and the side face. The linear distance d between the upper edge and the lower edge is t≤d≤1.1 t or t≤d≤1.05 t.

This invention discloses a low-resistivity silicon suboxide lithium-ion battery anode material and its preparation method. Fluorinated silicon suboxide is mixed with a carbon precursor and a solvent, ground until dry, and the solvent is removed to obtain an intermediate material. The intermediate material is then calcined in a protective gas atmosphere using gradient heating and / or gradient pressurization to obtain the anode material. This invention constructs a fluorine gradient hole structure, which preferentially transforms into a stable LiF-rich solid electrolyte interphase (SEI) film during electrochemical cycling, significantly reducing the lithium-ion diffusion barrier and interfacial charge transfer impedance. The gradient heating and / or pressurization sintering process carbonizes the carbon precursor in situ on the surface of the fluorinated layer, forming a dense and robust coating layer. This coating layer forms a strong interfacial bond through vacancy bonding and mechanical interlocking, buffering volume expansion. The anode material obtained using this invention exhibits excellent electrochemical performance and significantly reduces impedance.

The present invention provides a substrate processing method comprising the steps of: forming, on a substrate, a pair of high dielectric constant thin films having an aluminum oxide film interposed therebetween; and forming an aluminum-doped diffusion barrier film between the aluminum oxide film and the high dielectric constant thin film in order to prevent aluminum from diffusing from the aluminum oxide film to the high dielectric constant thin films

Metal nitride diffusion barriers may be included between cobalt-based structures and ruthenium-based structures to reduce, minimize, and / or prevent intermixing of cobalt into ruthenium. A metal nitride diffusion barrier layer may include a cobalt nitride (CoNx), a ruthenium nitride (RuNx), or another metal nitride that has a bond dissociation energy greater than the bond dissociation energy of cobalt to cobalt (Co—Co), and may therefore function as a strong barrier to cobalt migration and diffusion into ruthenium. Moreover, cobalt nitride and ruthenium nitride have lower resistivity relative to other materials such as titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN). In this way, the metal nitride diffusion barriers are capable of minimizing cobalt diffusion and intermixing into ruthenium-based interconnect structures while maintaining a low contact resistance for the interconnect structures. This may increase semiconductor device performance, may increase semiconductor device yield, and may enable further reductions in interconnect structure size.

The application provides a hybrid bonding structure, a three-dimensional packaging structure and a preparation method thereof. The preparation method of the hybrid bonding structure comprises the following steps: providing an initial hybrid bonding structure, wherein the hybrid bonding structure comprises a medium layer, a bonding medium layer, a diffusion barrier layer, a bonding metal layer and a regulation layer; performing a first grinding process to remove the diffusion barrier layer and the regulation layer, and forming a convex part protruding from the top surface of the bonding medium layer; and performing a second grinding process to remove the convex part of the bonding metal layer, and forming a first recessed part on the top surface of the bonding metal layer, which is lower than the top surface of the bonding medium layer. The hybrid bonding structure is a product prepared by the above method. The three-dimensional packaging structure comprises the hybrid bonding structure prepared by the above method. By adding the regulation layer, the convex part is formed when the diffusion barrier layer and the regulation layer are removed in the first grinding process, and the second grinding process is performed on the convex part to effectively control the depth of the first recessed part on the bonding metal layer. Therefore, the metal bonding interface cavity during hybrid bonding is reduced, and the bonding strength is improved.

A semiconductor device includes a substrate, a stack structure including gate electrodes spaced apart from each other in a vertical direction, and a channel structure extending vertically in a channel hole through the stack structure in the vertical direction. The channel structure includes a channel layer on a sidewall of the channel hole, a resistance switching layer between the sidewall of the channel hole and the channel layer, the resistance switching layer configured to vary an electrical conductivity based on an electrochemical reaction involving a loss or a gain of oxygen ions, a diffusion barrier structure between the sidewall of the channel hole and the resistance switching layer, an electrolyte layer between the channel hole and the diffusion barrier structure, and an ion storage layer between the channel hole and the electrolyte layer. The diffusion barrier structure includes at least two diffusion barrier layers sequentially stacked.

The application discloses a preparation method of a single-crystal metal lithium negative electrode. The single-crystal metal lithium negative electrode with a dense packing surface Li(110) is obtained by annealing a polycrystal metal lithium foil horizontally placed after being heated in vacuum or inert atmosphere, and is directly used for battery assembly. The application remarkably improves the electrode reaction process kinetics of the metal lithium negative electrode by reducing the self-diffusion barrier of the surface of the metal lithium negative electrode, widens the safety boundary of the metal lithium negative electrode, and enables the metal lithium negative electrode to have no dendrite growth in a practical current density range. The prepared single-crystal metal lithium negative electrode can be directly used for battery assembly, and remarkably improves the cycle stability and safety of a high-specific-energy metal lithium battery, and promotes the development of practical high-safety metal lithium batteries.

Provided are a semiconductor device, an electronic apparatus, and / or a method of manufacturing the semiconductor device. The semiconductor device may include a substrate, an oxide semiconductor layer on the substrate, a first electrode on the oxide semiconductor layer, a second electrode on the oxide semiconductor layer and spaced apart from the first electrode, and a diffusion barrier. The diffusion barrier may be between the oxide semiconductor layer and the first electrode and / or the diffusion barrier may be between the oxide semiconductor layer and the second electrode.

This invention provides a composite hydrogen-barrier coating for high-strength steel and its preparation method. Belonging to the field of surface modification of metallic materials, the high-strength steel has a hardness of HV300-HV600, a tensile strength of 900-1200 MPa, a maximum thermal expansion coefficient of (8-20)×10⁻⁶ / K, and an elastic modulus between 100-200 GPa. The composite hydrogen-barrier coating consists of a transition layer and a hydrogen-barrier layer. The transition layer is composed of Al, Cr, and Zr, with each element having a molar ratio of not less than 30%. The hydrogen-barrier layer is composed of Al, Cr, Zr oxides and some unoxidized metal. Both the transition layer and the hydrogen-barrier layer have an amorphous structure. This coating utilizes the difference in binding energy between Al, Cr, and Zr and hydrogen to construct a material system with a tortuous hydrogen diffusion path and a high hydrogen diffusion barrier. Using magnetron sputtering technology, an amorphous (AlCrZr)O coating can be prepared on the surface of high-strength steel, effectively blocking and capturing hydrogen atoms, significantly improving the material's resistance to hydrogen embrittlement.

The application belongs to the field of integrated circuit manufacturing, and particularly relates to a single-layer diffusion barrier layer with low resistivity and high failure temperature for copper interconnection. The diffusion barrier layer is a copper interconnection diffusion barrier layer, which is located between copper and a silicon substrate, and contains M and N elements, wherein M is selected from one of Zr and Hf. The copper interconnection diffusion barrier layer is prepared by a magnetron sputtering process, and the nitrogen content accounts for 18% to 25% of the working gas content during the preparation of the copper interconnection diffusion barrier layer by magnetron sputtering. The single-layer nitride diffusion barrier layer prepared by magnetron sputtering has an ultra-thin thickness, a resistivity lower than 40 micro-ohm per centimeter (even lower than 10 micro-ohm per centimeter) at 600 degrees Celsius, and a failure temperature higher than 600 degrees Celsius. The application has reasonable component design, simple and controllable process, and is convenient for industrial application.

Various embodiments herein relate to methods, apparatus, and systems for forming an interconnect structure, or a portion thereof, on a substrate. In one example, the method includes receiving the substrate in a processing chamber, the substrate having dielectric material exposed within recessed features formed therein; exposing the substrate to plasma to thereby modify a top surface of the dielectric material; forming a metal oxide barrier layer on the modified top surface of the dielectric material, wherein the metal oxide barrier layer is formed through atomic layer deposition and / or chemical vapor deposition. In certain implementations, one or more additional step may be taken to improve processing results, for example to promote nucleation and / or adhesion of relevant layers.

The application discloses a high-strength and high-toughness Al-Ca-In series aluminum alloy low-oxygen spherical powder for additive manufacturing and a preparation method thereof, relates to the technical field of additive manufacturing powder, and comprises the following components in percentage by mass: 1.5-3.0% of magnesium, 0.15-0.60% of manganese, 1.0-2.0% of calcium, 0.06-0.25% of indium, 0.08-0.18% of zirconium and 0-0.05% of titanium, and the balance of aluminum and impurities, wherein the total oxygen is not more than 0.10%; the powder surface has a nitrogen-containing diffusion barrier layer with a thickness of 2-8 nanometers and an ultrathin oxide layer with a thickness of 0.5-2.0 nanometers in sequence, and the surface enrichment and interface capture indexes are limited; and the powder is prepared by high-temperature dissolution of manganese and zirconium, low-temperature segmented calcium addition, nitrogen-containing gas atomization and low-temperature micro-oxidation. The powder inhibits the surface migration and oxidation loss of calcium and indium, improves the component stability in recycling and forming, reduces defects and performance dispersion, and is suitable for the high-strength and high-toughness manufacturing consistency of thin-wall lattice load-bearing parts.

This invention provides a method for preparing a tungsten-titanium-aluminum alloy target. The method includes the following steps: ball milling tungsten powder, titanium powder, and aluminum powder under an inert atmosphere to obtain a mixed powder; adding the mixed powder in portions into a hot-pressing mold, performing hot-pressing sintering and post-treatment to obtain the tungsten-titanium-aluminum alloy target. The tungsten-titanium-aluminum alloy target provided by this invention is widely used in the field of high-performance thin film deposition as a diffusion barrier layer to prevent copper atoms from diffusing into the silicon substrate. Furthermore, due to its high thermal stability and low resistivity, it can also be used as a gate or contact electrode.

A semiconductor structure and a method for forming the same are disclosed. The method includes forming a diffusion barrier layer on a substrate. The step of forming the diffusion barrier layer includes: forming a first diffusion barrier layer on the substrate at a first preset temperature; and forming a second diffusion barrier layer on the first diffusion barrier layer at a second preset temperature. The first preset temperature is lower than the second preset temperature. Because the first preset temperature is lower than the second preset temperature, the rate of forming the first diffusion barrier layer is lower, resulting in an increased time for forming the first diffusion barrier layer. This allows dopant ions in the embedded layer more time to diffuse and distribute within the substrate, resulting in a more uniform concentration distribution of dopant ions in the embedded layer within the substrate. This reduces the concentration gradient of dopant ions in the substrate, thereby reducing the probability of dopant ions in the embedded layer diffusing to the substrate surface. In subsequent process steps, this increases the probability of neutralization between dopant ions in the epitaxial layer and dopant ions in the embedded layer.

This invention relates to the field of sodium-ion battery technology, and in particular to a polyanion-doped sodium vanadium manganese phosphate cathode material, its preparation method, and a sodium-ion battery. The general chemical formula of the polyanion-doped sodium vanadium manganese phosphate cathode material provided by this invention is Na₄VMn(PO₄). 3‑x (SiO4) x Where x is 0.01~0.08; SiO4 4‑ PO4 in the crystal framework is located by isomorphous substitution. 3‑ Site. The polyanion-doped sodium manganese phosphate cathode material of the present invention, SiO4 4‑ Partial PO4 substitution 3‑ The site can directly expand the migration channel size of sodium ions from a crystallographic perspective, effectively reducing the diffusion barrier of sodium ions; the stronger Si-O bond energy enhances the overall stability of the crystal structure. This synergistic effect of expanding channels and strengthening the framework effectively inhibits structural degradation during cycling, especially alleviating the degradation of Mn. 3+ The Jahn-Teller effect.

This invention relates to a heat-insulating and corrosion-resistant composite coating, its preparation method, and its application in ammonia fuel engines. The coating has a multi-layered composite structure, consisting of a bonding layer, a heat-insulating layer, a second corrosion-resistant layer, and a first corrosion-resistant layer. The bonding layer reliably bonds to the metal substrate to alleviate thermal stress differences. The heat-insulating layer enhances the phase stability and structural stability of the coating under high-temperature service conditions, slowing down the degradation of its heat-insulating performance. The second corrosion-resistant layer effectively blocks the pore penetration channels, reducing the risk of corrosive media such as water vapor and nitrogen oxides penetrating inward along the pores of the heat-insulating layer. The first corrosion-resistant layer, acting as an outer hydrogen diffusion barrier layer, effectively inhibits hydrogen penetration into the metal substrate, reducing the risk of hydrogen-related failures. This invention, through a multi-layered structure, synergistically improves the long-term thermal cycling stability and comprehensive protection capability of the composite coating system, ensuring the service reliability and lifespan of key components in ammonia fuel engines.

This application discloses a thermal barrier coating and its preparation method, relating to the field of coating preparation technology. The provided method for preparing the thermal barrier coating includes: providing a substrate; forming a diffusion barrier layer on the substrate; forming an adhesive layer on the diffusion barrier layer; and forming a ceramic layer on the adhesive layer. The diffusion barrier layer includes a nickel-rhenium diffusion barrier layer, and the preparation of the nickel-rhenium diffusion barrier layer includes: preparing a nickel-rhenium alloy, processing it to obtain a target material for multi-arc ion plating; and using a multi-arc ion plating process to prepare the nickel-rhenium diffusion barrier layer on the surface of the substrate. This invention solves the problems of low bonding ability and difficulty in controlling the preparation of thermal barrier coatings containing diffusion barrier layers in current methods, improving coating production efficiency and diffusion barrier layer quality, and avoiding problems such as uncontrollable diffusion barrier thickness and quality.

The disclosed technology generally relates to forming a diffusion barrier layer structure, and more specifically to a diffusion barrier layer comprising a metal silicide and a titanium silicon nitride and a method for forming the same. In one aspect, a method for forming a diffusion barrier layer comprises the steps of: providing a substrate comprising an exposed silicon surface; forming a metal silicide layer other than a titanium silicide layer by exposing the substrate to a metal precursor other than a titanium-containing precursor; and forming a titanium silicon nitride (TiSiN) layer by periodically exposing the substrate to a titanium-containing precursor, a nitrogen-containing precursor, and a silicon-containing precursor after forming the metal silicide layer.

A magnetic memory device includes a pinned magnetic pattern, a tunnel barrier pattern, a free magnetic pattern, a diffusion barrier pattern, a non-magnetic pattern and a capping pattern, which are sequentially stacked on a substrate. The diffusion barrier pattern includes a first non-magnetic metal and oxygen. The non-magnetic pattern includes a second non-magnetic metal and oxygen. An oxide formation energy of the first non-magnetic metal is lower than an oxide formation energy of the second non-magnetic metal.

The application relates to the field of optical communication, in particular to a high-speed external modulation laser chip and a preparation method, the chip comprising a modulator module and a laser module on the same substrate and the same first cladding layer, the laser module comprising a first confinement layer, a first multiple quantum well structure and a second confinement layer; the modulator module comprising a third confinement layer, a second multiple quantum well structure and a fourth confinement layer; the first confinement layer is butted with the third confinement layer, the first multiple quantum well structure is butted with the second multiple quantum well structure, and the second confinement layer is butted with the fourth confinement layer; a diffusion barrier layer is buried around the first multiple quantum well structure and the second multiple quantum well structure. The diffusion barrier layer is buried around the multiple quantum well structure of the chip, the diffusion barrier layer can effectively prevent the diffusion of Zn, reduce the leakage current, and improve the modulation bandwidth of the chip.

The application discloses a process method for improving Pd distribution on a FAB surface of a palladium-plated copper wire, and belongs to the technical field of semiconductor bonding wire materials. The application uses a dichlorotetraammine palladium plating system as a basis, uses Ni elements and / or platinum group noble metal elements as plating liquor modification components, combines copper core pretreatment, pulse plating, gradient coating preparation, IMC interface presetting and post-treatment, uses the interface diffusion barrier characteristics of Ni, uses the high surface energy advantage of platinum group noble metals, improves Pd-Cu interface diffusion activation energy, and solves the problems that in the existing palladium-plated copper wire FAB ball forming process, a Pd layer is easy to excessively diffuse to a copper core, surface Pd coating is discontinuous, and it is difficult to form a dense solid protective layer. The application widens the selection window of modification elements, takes into account low cost and high reliability, is suitable for existing dichlorotetraammine palladium industrial plating production lines and mainstream bonding equipment, does not need equipment modification, is stable and controllable, and is suitable for large-scale mass production application of semiconductor packaging palladium-plated copper wires.

A piezoelectric-on-insulator (POI) substrate includes a carrier substrate, a trapping layer on a free surface of the carrier substrate, a piezoelectric layer, in particular, a lithium tantalate or lithium niobate piezoelectric layer, and an intermediate structure sandwiched between the piezoelectric layer and the trapping layer of the carrier substrate. The intermediate structure includes at least one tantalum nitride-based or silicon carbon nitride based diffusion barrier layer preventing the diffusion of metal elements. A method is used to manufacture such a piezoelectric-on-insulator substrate.

A method for manufacturing an anti-oxidation coating for titanium alloys includes the following steps: providing a titanium alloy part and cleaning its surface; depositing a Ni / Re or Ta diffusion barrier layer on the surface of the titanium alloy part; and depositing an MCrAlY protective layer or an aluminide protective layer on the surface of the titanium alloy part using a vapor deposition process, wherein M is Ni or NiCo. The anti-oxidation coating for titanium alloys prepared by this method exhibits excellent high-temperature oxidation resistance and can inhibit interdiffusion between the coating and the titanium alloy substrate, thereby improving the bonding strength of the coating. This invention also provides an anti-oxidation coating for titanium alloys.