85 results about "Solder mask" patented technology

This disclosure relates to lidar and printed circuit boards and transmitting assemblies used therein. The printed circuit board may include a multilayer structure, a thermally conductive layer, a top metal layer, blind vias, and a solder mask. A ceramic block is embedded within the multilayer structure. The thermally conductive layer is located on the multilayer structure and includes a prepreg layer or an adhesive film layer with a modulus less than or equal to 5 GPa. The top metal layer is located on the thermally conductive layer. Blind vias extend longitudinally through the top metal layer and the thermally conductive layer above the ceramic block, and these blind vias are used for electrical coupling with a laser. The solder mask covers the top metal layer, which includes exposed areas corresponding to the ceramic block.

Systems and methods of the present disclosure are directed to an electronic substrate. The electronic substrate includes a base layer, first feature(s) formed from a first metal layer and a second metal layer, and second feature(s) formed from the first metal layer. The electronic substrate includes a polymerized photodielectric layer over the first feature(s) and the second feature(s). The polymerized photodielectric layer exposes a portion of the second metal layer of the first feature(s), and at least a portion of the first metal layer of the second feature(s).

This invention discloses a method for fabricating positioning points on a printed circuit board (PCB) and the PCB itself, belonging to the field of PCB fabrication technology. The method involves printing white ink onto the PCB, masking and exposing areas outside the positioning surface to allow the white ink covering the positioning surface to solidify into white ink blocks. The PCB is then immersed in a developing solution to remove the remaining white ink. The PCB is subsequently heated to solidify the white ink blocks into white positioning blocks. Next, green ink is printed onto the PCB, masking and exposing areas outside the solder mask surface to allow the green ink covering the solder mask to solidify into green ink blocks. The PCB is then immersed in a developing solution to remove the remaining green ink. The PCB is then heated to solidify the green ink blocks into solder mask bridges. This method improves the adhesion between the solder mask bridges and the white positioning blocks to the PCB, preventing the edges of the solder mask bridges and white positioning blocks from detaching and ensuring the positioning accuracy of the white positioning blocks.

This invention discloses a circuit board processing method and circuit board processing equipment, comprising: processing a first through hole on a multilayer circuit board, the multilayer circuit board including a first solder mask layer and a second solder mask layer respectively disposed on two adjacent circuit boards, the first solder mask layer and the second solder mask layer being disposed opposite to each other, and the first through hole penetrating the first solder mask layer and the second solder mask layer; performing a desmearing process on the multilayer circuit board to form a first space on the first solder mask layer and a second space on the second solder mask layer; depositing a first metal layer on the inner wall of the first through hole, the first space and the second space; removing the first solder mask layer and the second solder mask layer, and electroplating a second metal layer on the first metal layer on the inner wall of the first through hole to obtain a target circuit board including a target metallized hole, so as to completely remove the low-density first metal layer deposited in the first solder mask layer and the second solder mask layer, so as to achieve complete electrical isolation between the two adjacent circuit boards with the first solder mask layer and the second solder mask layer, and achieve zero residual solder.

The application discloses a kind of inspection methods, devices and equipment and medium for component heat dissipation pad design, comprising: reading PCB design file and screening out heat dissipation pad containing package;Each heat dissipation pad of screened package is executed checking step, checking step covers multiple checking items with certain checking order, when any checking item does not meet corresponding design requirement, it is judged that the heat dissipation pad needs to be redesigned, when multiple checking items all meet respective corresponding design requirements, it is judged that the heat dissipation pad meets all design requirements;Checking order is generated according to the design constraint between multiple checking items when meeting heat dissipation pad reliability requirement;Multiple checking items at least include copper foil area design of heat dissipation pad, solder mask bridge design, solder mask window area design, drill hole design in solder mask window, gas guide groove design, drill hole design on heat dissipation pad, jack design and backside bright copper design.The application is automatically checked after PCB design is completed, and can improve checking efficiency and accuracy.

The application belongs to the technical field of electronic component substrates, and discloses a multifunctional ceramic packaging substrate and a preparation method thereof. The multifunctional ceramic packaging substrate comprises a ceramic core plate and an ABF composite layer, and the upper and lower sides of the ceramic core plate are provided with the ABF composite layer, and the ABF composite layer is embedded with electronic components. The preparation method comprises the following steps: S10, providing a ceramic substrate; S20, providing an electroplated copper film layer on the surface of the ceramic substrate; S30, providing an ABF composite layer on the upper and lower sides of the ceramic substrate; S40, embedding electronic components in the ABF composite layer; S50, providing a solder resist layer on the surface of the outermost ABF layer; and S60, providing a surface treatment layer on the outer side of the solder resist layer. The reliability of the application is significantly improved, the space utilization rate and the advantages of lightness and thinness are prominent, the high-frequency and high-speed performance is optimized, and the process compatibility is strong.

The present disclosure provides a printed circuit board and a manufacturing method thereof, which can include an insulating layer, a pad disposed on the insulating layer, a solder resist layer disposed on the insulating layer and having an opening exposing at least a portion of the pad, and a solder bump at least partially disposed in the opening of the solder resist layer. The solder bump has a rectangular shape in a cross-sectional view cut in a direction parallel to a height direction, the height direction being perpendicular to a surface of the solder resist layer.

This invention discloses a method for fabricating a trench-based heterogeneous sandwich stepped solder resist structure and a semiconductor device. The semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a trench-based heterogeneous sandwich stepped solder resist structure. In the trench-based heterogeneous sandwich stepped solder resist structure, trenches are formed around the electrical connection structure of the pads formed by the metal interconnect layer. An insulating dielectric layer covers the passivation layer and part or all of the trenches to form a first stepped structure, and a solder resist layer covers the insulating dielectric layer and part or all of the trenches to form a second stepped structure. By utilizing the composite sandwich structure formed by the trench-based reinforced insulating dielectric layer and solder resist layer, multiple barriers can be formed against the intrusion of moisture and solder, effectively delaying or blocking the migration path of moisture along the interface between the passivation layer and the solder resist layer, significantly improving the moisture intrusion protection capability, and effectively preventing PI peeling.

This application relates to the field of semiconductor packaging technology, and in particular to a DPC-based SIP RF module. The DPC-based SIP RF module includes a ceramic substrate and a frame. A chip arrangement metal layer is formed on the first surface of the ceramic substrate, including a circuit plating layer and a solder plating layer surrounding the outside of the circuit plating layer. The bottom end of the frame is used for soldering to the solder plating layer. The thickness of the solder plating layer is less than that of the circuit plating layer, and a solder resist layer is provided along the peripheral edge of the circuit plating layer. A recess is formed on the inner side of the bottom end of the frame, and the end face of the bottom end of the frame can be adapted to face and soldered to the solder plating layer. The peripheral edge of the circuit plating layer and the solder resist layer are adapted to extend into the recess. Thus, a dam structure is formed on the ceramic substrate by soldering the frame, effectively preventing solder overflow during soldering. Furthermore, compared to directly electroplating an ultra-thick dam structure on the ceramic substrate, this method effectively shortens the processing cycle and improves production efficiency.

The application provides a packaging substrate and a preparation method thereof, the preparation method comprising the steps of: providing a semiconductor structure, the semiconductor structure comprising an insulating support layer and a metal layer covering at least one side of the insulating support layer, the metal layer comprising a metal circuit and a metal pad electrically connected to the metal circuit, forming a solder resist layer covering the insulating support layer and the metal layer, forming a pad opening in the solder resist layer, the pad opening exposing part of the surface of the metal pad, forming a metal plating layer of a preset thickness on the surface of the metal pad, implanting a solder ball in the pad opening, and electrically connecting the implanted solder ball and the metal pad through reflow soldering to obtain the packaging substrate. The preparation method of the packaging substrate can effectively avoid the product short circuit failure caused by side etching of the solder resist layer of the substrate and overflow of the solder during reflow soldering, thereby improving the reliability and stability of the product.

An electronic component includes a substrate having a surface; a solder mask on a portion of the surface of the substrate, the solder mask having at least one control feature defined by a gap between a first portion of the solder mask and a second portion of the solder mask; at least one electronic component having an edge spaced apart from the gap by a distance; and an underfill material located between the edge of the at least one electronic component and the at least one control feature, the gap being devoid of the underfill material.

The application discloses a kind of system-in-package substrate and its processing method, comprising: the intermediate plate formed with ultra-thick copper micro pitch circuit pattern is prepared, the relative length difference between multiple SET plate board edge area B of the intermediate plate and the reentrant lead connected with circuit pattern is not more than 15% respectively made out;Thermally reformed characteristic photosensitive insulating resin film and first ink dry film are stacked on the intermediate plate to fill the micro gap between circuit pattern;Part of the composite insulating film is removed to expose circuit pattern and reentrant lead;Make out solder mask layer and electroplated gold layer, control height difference between electroplated gold layer and solder mask layer ≤5 μm.The processing method is simple, easy to implement, and the system-in-package substrate obtained meets the technical requirements of high-density integrated packaging, ultra-high heat dissipation, resin-filled circuit pattern, ink thickness on copper surface ultra-thin, height difference between soldering surface and solder mask layer ≤5 μm, etc.;Promote the development of system-in-package technology.

A planar transformer including first and second parts of a core with least one of the first and second parts having a center post that resides in an aperture of a PWB. The PWB includes primary windings and secondary windings that surround the center post, are magnetically coupled by the core, and are electrically independent. Separating an uppermost winding from the first part of the core is a first prepreg structure and separating a lowermost winding from the second part of the core is a second prepreg structure. There being no windings disposed between the first and second prepreg structures and the core. This planar transformer structure inhibits the windings from electrically shorting through the core when the planar transformer is subjected to shock or vibration. One variant includes the use of pre-form adhesives sheets located between the solder mask layers of the PWB and the core.

A substrate comprising at least one dielectric layer; a plurality of interconnects comprising: a first plurality of trace interconnects located on a first metal layer of the substrate, wherein the first plurality of trace interconnects are configured as one or more coils of a first inductor; and a second plurality of trace interconnects located on a second metal layer of the substrate, wherein the first plurality of trace interconnects are configured as one or more coils of a second inductor, at least one cavity in the at least one dielectric layer; and a solder resist layer located at least partially in the at least one cavity in the at least one dielectric layer.

A transistor amplifier package includes a package substrate comprising conductive patterns exposed by solder mask patterns at a surface thereof, and at least one transistor die comprising a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask patterns such that respective gate, drain, and / or source terminals of the at least one transistor die are electrically connected to respective ones of the conductive patterns. Related transistor amplifiers and fabrication methods are also discussed.

A printed circuit board includes an electrically insulative layer and a conductive pad disposed over the electrically insulative layer. The conductive pad defines a contact area for attachment of a conductor and is partially covered by a solder mask that defines an exposed region of the conductive pad. The conductive pad extends underneath the solder mask along a periphery of the exposed region to form an extended pad area. The extended pad area protects the electrically insulative layer from thermal, mechanical, electrical, and vibrational damage during attachment of the conductor. The extended pad area further accommodates positional variation of non-rigid conductors resulting from inherent spring force introduced during prior manufacturing processes. Pad extension dimensions may be determined as a function of conductor length, pad geometry, and a spring displacement angle of the conductor. The configuration is applicable across multiple joining processes and improves manufacturability of printed circuit board assemblies.

The application relates to a PCB (printed circuit board) capable of preventing bending fracture, which comprises a substrate layer, a solder pad arranged on the substrate layer, at least one circuit layer and at least one solder resist layer in the thickness direction, characterized in that the PCB has a plurality of relatively independent connecting units in the length direction, and a connecting area is arranged between two adjacent connecting units; at least one via hole penetrating through the substrate layer is arranged at the end of the connecting unit or at least one of the connecting areas, and a conductive circuit on the circuit layer close to the solder pad or on the same surface as the solder pad is arranged.

This invention discloses a packaging substrate for buried interconnect bridges, a semiconductor packaging structure, and a method for fabricating the same. The packaging substrate includes a core board, which is a substrate or PCB board without a solder mask layer. The core board has opposing first and second surfaces. An outermost circuit layer is formed on the first surface and electrically connected to the circuit layer within the core board. The outermost circuit layer has a metal disk. Interconnect bridges are bonded or attached to the metal disk of the outermost circuit layer. A molding layer is formed on the first surface, the outermost circuit layer, and the interconnect bridges, and covers the interconnect bridges. Multiple conductive interconnect structures penetrate the molding layer and are electrically connected to the metal disk and interconnect bridges of the outermost circuit layer, respectively, to provide electrical paths to external chips. Multiple external connection terminals are electrically connected one-to-one to the side of the multiple conductive interconnect structures away from the core board. This packaging substrate for buried interconnect bridges can be used for board-level or system-level multi-chip packaging, achieving high-density interconnection between chips and compatibility with the domestic industrial chain.

The present invention provides a PCB including a solder mask and / or conductive traces that can be repaired quickly and cost-effectively. [Solution] A printed circuit board includes at least one solder mask formed from a repairable dielectric material and / or a conductive trace formed from a repairable conductive material. Thus, the solder mask and / or conductive trace can be selectively repaired. The repairable dielectric material may flow when heated to a repair temperature. The repairable conductive material may flow when a repair voltage is applied. As with methods for repairing the solder mask and conductive trace of the PCB of an electronic device assembly, an electronic device assembly is also disclosed.

The utility model discloses a kind of PCB solder mask ink roller coating devices, it is related to PCB solder mask technical field, including the limiting mechanism including support plate, antiskid block, clamping block and sliding assembly, the support plate is set on the main body upside, the antiskid block is provided with two, two The antiskid block is all set on the support plate upper surface, the clamping block is provided with two, two The clamping block opposite side is fixedly connected in the antiskid block opposite side, the sliding assembly is provided with two, two The sliding assembly is all set on the clamping block lower surface.The utility model is set by setting limiting mechanism, it solves that manual conveying PCB board cannot be accurately positioned to solder mask roller middle position, makes different batch product quality consistency poor, increases defective rate, simultaneously reduces production efficiency, cannot satisfy the precision requirement of scale production problem.

The utility model relates to the technical field of ceramic substrate, and disclose a kind of multilayer composite high-speed thin film ceramic substrate structure, solve the problem that the heat dissipation effect of current electronic equipment is not good, it includes ceramic substrate layer, the top of the ceramic substrate layer is equipped with transition metal layer, transition metal layer and ceramic substrate layer between being equipped with strengthening mechanism, the top of transition metal layer is equipped with circuit layer, the top of circuit layer is equipped with solder resist, the inside of ceramic substrate layer is equipped with multiple heat dissipation channels, the bottom of ceramic substrate layer is equipped with multiple ventilation holes, and the ventilation hole and heat dissipation channel of corresponding position are interconnected, the bottom of ceramic substrate layer is evenly equipped with multiple heat dissipation fins;The utility model discloses when electronic equipment operates, air can flow in heat dissipation channel by fan and the like device, heat dissipation is facilitated, and the existence of heat dissipation fin increases the heat dissipation area, can accelerate the heat dissipation speed to ambient environment.

This application relates to an inkjet printing method, apparatus, computer equipment, and workpiece. The method includes: providing a workpiece to be processed, wherein the printing area of ​​the workpiece is composed of multiple partitions, each partition including a sub-printing area, or multiple mutually separated sub-printing areas; controlling an inkjet printing device to sequentially perform inkjet printing on each partition, and curing the printed sub-printing areas, wherein adjacent sub-printing areas to the sub-printing area currently being printed are in a cured state. This method can improve the processing quality of the solder mask layer.

The application provides a packaging substrate and a packaging structure. The packaging substrate of the embodiment of the application comprises a solder resist layer, a copper layer and a substrate which are sequentially stacked, the solder resist layer comprises a first solder resist part on the copper layer and a second solder resist part on the substrate; the packaging structure further has a first channel and a second channel, the first channel penetrates the copper layer along the thickness direction of the substrate, and part of the first solder resist part is filled into the first channel; the second channel penetrates the second solder resist part along the thickness direction of the substrate. Therefore, the packaging substrate of the embodiment of the application has the characteristic that the solder resist layer, the copper layer and the substrate and the plastic package in the subsequent plastic package process are not prone to delamination.

The application discloses a PCB solder mask processing method and a PCB solder mask processing system. The PCB solder mask processing method comprises the following steps: low-pressure spraying a solder mask ink layer on a preset area of a target PCB to obtain a first processed PCB, wherein the preset area comprises a non-welding copper-clad area and a non-copper-clad area; determining a copper-clad edge of the non-welding copper-clad area of the first processed PCB; and printing the solder mask ink on the copper-clad edge to obtain a second processed PCB. The method realizes printing of the solder mask ink on the copper-clad edge area of the PCB with the low-pressure sprayed solder mask ink layer, thickens the solder mask ink layer at the copper-clad edge of the PCB, and can inhibit the problem that the solder mask ink at the copper-clad edge of the PCB is too thin during the solder mask processing of the PCB, which leads to unqualified solder mask processing of the PCB, and is beneficial to improving the quality of the solder mask processing of the PCB.

This invention discloses a long-distance vertical transmission conversion structure for radio frequency (RF) signals, belonging to the field of RF and microwave technology. It includes a housing with stepped holes and transmission through-holes, an RF connector, PTFE pillars, a printed circuit board (PCB), a PTFE clamping block, and a cover plate. The conductor pins of the RF connector pass through the central hole of the PTFE pillar, and the PTFE pillar provides rigid, full-path positioning within the transmission through-hole through an interference fit. The ends of the conductor pins pass through metallized vias on the PCB and are soldered. An anti-overflow solder mask layer is provided on the back of the PCB. The PTFE clamping block has grooves to avoid microstrip lines and is further secured by the grooves in the cover plate. This invention utilizes a fully dielectric-filled structure to achieve long-distance precision impedance matching, eliminates the oscillation space of the conductor pins in vibration environments, significantly optimizes phase noise, effectively prevents solder overflow and short circuits, and improves the reliability of vertical interconnects.

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

The application belongs to the technical field of semiconductor packaging, and discloses an integrated packaging substrate based on a ceramic core plate and a preparation method thereof. The integrated packaging substrate comprises a ceramic core plate and an ABF composite layer, the upper and lower sides of the ceramic core plate are provided with the ABF composite layer, a conductive medium layer is arranged between the ABF composite layer and the ceramic core plate, and the upper and lower surfaces of the ceramic core plate are embedded with electronic components. The preparation method comprises the following steps: S10, providing a ceramic substrate; S20, embedding electronic components; S30, arranging a copper electroplating film layer on the surface of the ceramic substrate; S40, arranging the ABF composite layer on the upper and lower sides of the ceramic substrate; S50, arranging a solder resist layer on the surface of the outermost ABF layer; and S60, arranging a surface treatment layer on the outer side of the solder resist layer. Compared with the traditional packaging substrate, the integrated density and reliability of the application are significantly improved, and the signal transmission performance is optimized.

A package substrate includes a base substrate, a plurality of chip connection pads on an upper surface of the base substrate, a plurality of interconnection patterns on the upper surface of the base substrate and coupled with the plurality of chip connection pads, and an insulating layer on the plurality of interconnection patterns. The insulating layer includes a solder resist layer and at least one opening. The at least one opening at least partially exposes a connection portion. The connection portion includes at least a portion of a first interconnection pattern from among the plurality of interconnection patterns.