8results about "Stacked resist layers" patented technology

A method for manufacturing a wiring board includes: disposing a first resist material on a substrate; forming a first resist layer by curing the first resist material; forming a resin layer on a release film; forming a conductor portion on the resin layer; covering the conductor portion by disposing a second resist material on the resin layer; forming a second resist layer by curing the second resist material; bringing the first resist layer into contact with the second resist layer, and thereafter bonding the first resist layer and the second resist layer by thermocompression bonding; and releasing the release film from the resin layer.

To solve problems with the prior art.SOLUTION: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.SELECTED DRAWING: Figure 1A

Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity, medium-photosensitivity, and low-photosensitivity layer are applied to a substrate and exposed at the same time with use of a multi-tone mask. After being developed, one layer forms a mold for a first via, one layer forms a mold for a conductive trace and a second via, and one layer forms an overhang over the position for the second via. The molds formed by the photosensitive layers are filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the region under the overhang forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.

An electronic device includes a substrate having a surface, a first conducting layer disposed on the surface of the substrate, a second conducting layer disposed on the first conducting layer, a first electronic component disposed on the first conducting layer and electrically connected to the first conducting layer, and a second electronic component disposed on the second conducting layer and electrically connected to the second conducting layer. The second conducting layer is disposed between the first conducting layer and the second electronic component. In a cross-section view, the first electronic component is overlapped with the second conducting layer along a direction parallel to the surface of the substrate.

An electronic device with an active region comprising a substrate; a first conducting layer, disposed on the substrate, comprising a first pad in the active region; a second conducting layer, disposed on the first conducting layer, comprising a second pad in the active region; a first electronic component, disposed on the first pad, and electronically connected to the first pad; and a second electronic component, disposed on the second pad, and electronically connected to the second pad.

The present disclosure provides a method for manufacturing an electrical contact element on a circuit structure, the method comprising depositing a separation layer on a carrier substrate, wherein the carrier substrate comprises the circuit structure, forming a structuring layer with a predefined structure on a basic layer that is arranged between the separation layer and the structuring layer, adding an electrical contact element layer by depositing electrically conductive material on the basic layer via the structuring layer according to the predefined structure, and removing the separation layer, and the structuring layer. Further, the present disclosure provides a respective measurement application device.

The method for manufacturing a wiring board comprises: a first configuration step of configuring a first resist material (200) on a substrate (10); a first curing step of curing the first resist material (200) to form a first resist layer (20); a first forming step of forming an outer coating layer (70) on a release film (80); a second forming step of forming first and second conductor portions (41, 61) on the outer coating layer (70); and a second configuration step of covering the first and second conductor portions. (41, 61) method is used to configure a second anti-etching material (300) on the outer coating layer (70); a second curing step is used to cure the second anti-etching material (300) to form a second anti-etching layer (30); a bonding step is used to bond the first anti-etching layer (20) and the second anti-etching layer (30); a hot pressing step is used to hot press the first anti-etching layer (20) and the second anti-etching layer (30) after the bonding step; and a stripping step is used to strip the release film (80).