106results about How to "Improve package yield" patented technology

A flip-chip (FC) package structure is provided. The FC package structure includes a substrate, a chip, a plurality of copper platforms, a plurality of copper bumps, a plating layer, a circuit layer and a solder mask layer. The copper bumps are disposed on the substrate. The copper platforms are stacked on the copper bumps. The plating layer covers the copper bumps and the copper platforms, for contacting with chip foot pads configured at a bottom of the chip. The FC package structure does not need to reserve a space for wire bonding, thus saving the area of the substrate. The copper platforms are stacked on the copper bumps, and are higher than the circuit pattern layer. Therefore, the chip is blocked up, and the gap between the chip and the substrate is enlarged, thus preventing the risk of configuring voids when filling the cladding material and improving the packaging yield.

A self repair device may include: an electrical fuse array configured to store bit information of a failed address in a fuse; an electrical fuse controller configured to store a row address or column address corresponding to a failed bit when a failure occurs, generate a repair address by comparing a failed address inputted during a test to the address stored therein, output a rupture enable signal for controlling a rupture operation of the electrical fuse array, and output row fuse set data or column fuse set data in response to the failed address; and a row/column redundancy unit configured to perform a row redundancy or column redundancy operation in response to the row fuse set data or the column fuse set data applied from the electrical fuse array.

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

A cap wafer including a cavity, a packaged semiconductor including the cap wafer, and a method of fabricating the cap wafer. The cap wafer includes a cavity formed in an area of a lower surface of the cap wafer; and at least one feed-through penetrating through upper and lower surfaces of the cap wafer so as to be connected to the cavity. The packaged semiconductor includes a base wafer including an upper surface including an area in which a circuit device is formed; a cap wafer including a lower surface including an area in which a cavity having a predetermined size is formed, the cap wafer being combined with the base wafer to position the circuit device in the cavity so as to package the circuit device; and at least one feed-through penetrating through upper and lower portions of the cap wafer so as to be connected to the cavity and electrically connected to the circuit device.

The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer. By removing the exposed portion of the plating bus, the breaking hole is formed to electrically isolate the extended trail from the contact pads in order to prevent a chip on the substrate strip from being damaged by ESD (Electrostatic Discharge) during packaging processes.

The present invention provides a LCOS display. The display comprises a first PCB, an interface module, a first silicon chip, and a flat cable. The interface module is disposed on the first PCB and used to receive an audio and video signal. The first silicon chip comprises a display area, a processing area, and a metal layer. The display area comprises a pixel array in a LCOS panel formed on the first silicon chip. The processing area comprises a processing unit formed on the first silicon chip. The metal layer is formed on the first silicon chip for electrically connecting the display area with the processing area. The flat cable is used to electrically connect the interface module with the processing unit.

The present invention discloses a semiconductor package comprising a substrate having a plurality of substrate units, a plurality of semiconductor chips respectively disposed on the substrate units, and a plurality of conductive guard lines each disposed between two adjacent substrate units. Each substrate unit is provided with a plurality of contact pads and a plurality of conductive leads respectively connected to the corresponding contact pads. The semiconductor chips are electrically connected to the plurality of contact pads through the conductive leads. Each substrate unit has at least one of the contact pads electrically connected to the conductive guard lines such that the semiconductor package of the present invention can efficiently achieve the function of electrostatic discharge (ESD) protection.

The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises an isolating base, a wafer level package, a lens holder, and a F.P.C.. The wafer level package having a plurality of image sensor dies and a plurality of solder balls is attached to the isolating base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dies. The lens holder is placed in the F.P.C., and the F.P.C. has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dies. Moreover, the image sensor dies may be packaged with passive components or other dies with a side by side structure or a stacking structure.

The present invention relates to a preparation method of epoxy resin compound for semiconductor packaging process. Said epoxy resin compound has the advantages of low-viscosity, high-flowability, low water absorption and low porosity, etc. and can be used for packaging various integrated circuits and semiconductor devices.

A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Provided is a lead wire framework based on DIP multiple substrates and a method of using the lead wire framework to manufacture a packaging part. The lead wire framework comprises a framework body with a plurality of rows of first framework unit sets and a plurality of rows of second framework unit sets, and the two kinds of framework unit sets are arranged at intervals. A framework unit is provided with three substrates, wherein two substrates are in connection with four inner pins of the framework unit through a dam bar, and are located between a third substrate and the dam bar; the third substrate is in connection with the frame of the framework body through a tie bar; the inner pin in the framework unit towards an adjacent framework unit and the inner pin of the adjacent framework unit towards the framework unit are interlaced. A wafer is thinned and sawed, and a chip is adhered to the lead wire framework according to requirements to obtain a packing part through processes including pressure welding, post curing, plastic package, etc. The lead wire framework is conductive to increasing product function integration, and improving product packaging yield, quality and reliability; in addition, the lead wire framework can be extended to multi-row matrix type packaging, and is not limited to a DIP packaging form.

An automatic packaging method of optical elements includes a focusing platform set, a Z-axis feeder set and an automatic feeding set. The Z-axis feeder set is provided above the focusing platform set. An automatic feeding set is arranged on a horizontal plane between the Z-axis feeder set and the focusing platform set by an appropriate distance. An upper part and a lower part of an optical element are supported by the lower end of the Z-axis feeder set and the upper end of the focusing platform set, respectively. The lower end of the Z-axis feeder set is adjusted vertically and horizontally with respect to the focusing platform set such that the upper part and the lower part are arranged in a line and coincide with each other. Afterward, by using the automatic feeding set, the upper part and the lower part of the optical element are bound together via the solders.

The invention discloses a radiating packaging structure of a semiconductor, which comprises a base plate, a frame, a radiating fin and a heat conducting interface material layer, wherein the base plate loads and is electrically connected with at least one chip; the frame is bonded to the periphery of the base plate; the radiating fin is provided with one bonding surface bonded to the frame, the bonding surface is additional provided with one heat conducting area, and the heat conducting area is provided with a barrier wall to surround and form a material limiting space; and the heat conducting interface material layer is arranged in the material limiting space. The chip is provided with a radiating surface stretching into the material limiting space. The heat conducting interface material layer is located between the heat conducting area of the radiating fin and the radiating surface of the chip. The material limiting space is used for preventing the overflow, voids or other defects of the heat conducting interface material layer during high-temperature manufacturing.

In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.

A high frequency power amplifying device has two amplifying lines. Each amplifying line has a configuration in which a plurality of amplifying stages are connected in cascade having two source voltage terminals, of which one is connected to the first amplifying stage of one amplifying line and to the remaining amplifying stages of the other amplifying line, and the other, to the first amplifying stage of the latter amplifying line and to the remaining amplifying stages of the former amplifying line. An air core coil with a low D.C. resistance, formed by spirally winding a copper wire of about 0.1 mm in diameter, is connected in series between the final amplifying stage of each amplifying line and the source voltage terminal.

A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

An image sensor package structure is proposed, in which an image sensor is fixed on a substrate having metallization traces and an adhesion layer. Electric paths of the package structure are changed from the COG (chip on glass) process to the CIS (CMOS image sensor) process to improve electric characteristics. Moreover, spacers are formed at appropriate positions to prevent glue overflow from contaminating the sensing regions and solder balls. The proposed package structure can also shrink the package area to greatly enhance the yield and quality.

A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

The invention discloses an ultrathin optical fingerprint intercepting module packaging structure, comprising: a circuit board, an image sensing module, a lighting module and a packaging cover body, where the image sensing module and the lighting module are both arranged electrically on the circuit board; the packaging cover body is arranged on the circuit board and has a first opening unit for exposing the image sensing module and a second opening unit for exposing the lighting module. Therefore, the invention implements an ultrathin structure by reducing packaging structure volume and then can reduce the manufacturing cost and raise the product yield.