108results about How to "Improve package yield" patented technology

The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises an isolating base, a wafer level package, a lens holder, and a F.P.C.. The wafer level package having a plurality of image sensor dies and a plurality of solder balls is attached to the isolating base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dies. The lens holder is placed in the F.P.C., and the F.P.C. has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dies. Moreover, the image sensor dies may be packaged with passive components or other dies with a side by side structure or a stacking structure.

An automatic packaging method of optical elements includes a focusing platform set, a Z-axis feeder set and an automatic feeding set. The Z-axis feeder set is provided above the focusing platform set. An automatic feeding set is arranged on a horizontal plane between the Z-axis feeder set and the focusing platform set by an appropriate distance. An upper part and a lower part of an optical element are supported by the lower end of the Z-axis feeder set and the upper end of the focusing platform set, respectively. The lower end of the Z-axis feeder set is adjusted vertically and horizontally with respect to the focusing platform set such that the upper part and the lower part are arranged in a line and coincide with each other. Afterward, by using the automatic feeding set, the upper part and the lower part of the optical element are bound together via the solders.

A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

The present invention discloses a staggered finger configuration comprising a plurality of first and second conducting wires alternately arranged on the substrate, wherein each of the first conducting wire connecting an inner and an outer fingers and each of the second conducting wire connecting an intermediate finger between the inner and the outer fingers, thereby forming a staggered configuration.

A self repair device may include: an electrical fuse array configured to store bit information of a failed address in a fuse; an electrical fuse controller configured to store a row address or column address corresponding to a failed bit when a failure occurs, generate a repair address by comparing a failed address inputted during a test to the address stored therein, output a rupture enable signal for controlling a rupture operation of the electrical fuse array, and output row fuse set data or column fuse set data in response to the failed address; and a row / column redundancy unit configured to perform a row redundancy or column redundancy operation in response to the row fuse set data or the column fuse set data applied from the electrical fuse array.

An integrated circuit package is described including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.