Radiating packaging structure of semiconductor chip

Abstract

The invention discloses a radiating packaging structure of a semiconductor, which comprises a base plate, a frame, a radiating fin and a heat conducting interface material layer, wherein the base plate loads and is electrically connected with at least one chip; the frame is bonded to the periphery of the base plate; the radiating fin is provided with one bonding surface bonded to the frame, the bonding surface is additional provided with one heat conducting area, and the heat conducting area is provided with a barrier wall to surround and form a material limiting space; and the heat conducting interface material layer is arranged in the material limiting space. The chip is provided with a radiating surface stretching into the material limiting space. The heat conducting interface material layer is located between the heat conducting area of the radiating fin and the radiating surface of the chip. The material limiting space is used for preventing the overflow, voids or other defects of the heat conducting interface material layer during high-temperature manufacturing.

Description

【Technical field】 [0001] The invention relates to a heat dissipation package structure of a semiconductor chip, in particular to a heat dissipation package structure of a semiconductor chip which can prevent overflow or gaps in a thermally conductive interface material layer. 【Background technique】 [0002] Nowadays, in order to meet various high-density packaging requirements, the semiconductor packaging industry has gradually developed various types of packaging structures, among which the common packaging structures with substrates include ball grid array packaging structures (ball grid array, BGA) , a pin grid array package structure (pin grid array, PGA), a land grid array package structure (land grid array, LGA) or a board on chip package structure (board on chip, BOC), etc. In the above packaging structure, at least one chip is carried on the upper surface of the substrate, and several pads of the chip are electrically connected to the upper surface of the substrate t...

AI Technical Summary

Problems solved by technology

However, the above heat dissipation package structure still has the following problems during actual assembly: such as Figure 1C As shown, when the solder balls 18 are planted by reflow soldering, it is usually necessary to use a high temperature of about 260° C., which is much higher than the temperature (about 160° C.) of the above-mentioned baking process.

As a result, the application range of such thermal design is greatly limited

Images