717 results about "Integrated circuit packaging" patented technology

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

The invention discloses a shielding protection adhesive tape for semiconductor integrated circuit packaging and a preparation method thereof, and relates to the technical field of semiconductor integrated circuit packaging. The shielding protective adhesive tape for packaging the semiconductor integrated circuit is prepared by taking polyimide as a base material and coating a coating, and the coating comprises the following raw materials in parts by weight: 3-5 parts of modified nano silicon dioxide, 30-40 parts of N, N-dimethylformamide, 1-3 parts of a curing agent and 1-3 parts of a curing agent. The invention discloses a high-temperature-resistant epoxy resin coating which is prepared from the following components in parts by weight: 25-30 parts of N, N-dimethylformamide, 25-30 parts of a modified acrylate copolymer, 17-26 parts of ethyl acetate, 12-15 parts of epoxy resin, 1-2 parts of a silane coupling agent KH-550, 0.5-1 part of an antioxidant 1010, 0.3-0.8 part of an ultraviolet absorbent UV-327, 1-2 parts of carboxyl-terminated nitrile rubber, 2-4 parts of decabromodiphenyl ether, 0.1-0.3 part of an organic siloxane defoaming agent, 0.2-0.5 part of an acrylate flatting agent and 10-11 parts of diaminodiphenyl sulfone. The adhesive tape contains the modified nano silicon dioxide, the modified acrylate copolymer and other components, so that the performance of the adhesive tape is guaranteed; pretreatment is meticulous, preparation steps are standard, and mass production is easy; a finished product can be effectively shielded, and the packaging yield and the product stability can be improved.

The invention discloses a low-warpage damp-heat-resistant liquid epoxy molding compound as well as a preparation method and application thereof. The liquid epoxy molding compound is prepared from the following raw material components in parts by mass: 85 to 90 parts of modified silicon dioxide, 5 to 8 parts of naphthalene type epoxy resin monomer, 5 to 8 parts of anhydride curing agent, 0.1 to 0.3 part of coupling agent, 0.1 to 0.3 part of adhesion promoter and 0.2 to 0.5 part of temperature response type amine catalyst. The modified silicon dioxide is obtained by carrying out surface modification on micron-sized silicon dioxide by adopting a silane coupling agent containing an epoxy group, and the mass of the silane coupling agent containing the epoxy group is 0.3-0.8% of the mass of silicon dioxide. The liquid epoxy molding compound provided by the invention has excellent flowability, adhesive force and heat and humidity resistance, can significantly relieve and reduce the warping of a silicon wafer, and is suitable for integrated circuit packaging.

Methods, systems, and methods of manufacture are described for integrating memory and compute die in a stacked configuration in an integrated circuit package without through silicon via. A packaging apparatus that includes a first semiconductor die comprising multiple memory cells and a second semiconductor die comprising compute logic representing a Processing-in-Memory (PiM) architecture. The PiM architecture is configured to process data stored at the memory cells. The first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data routed from a memory cell of the first semiconductor die.

Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a first glass layer including a first conductive through-glass via (TGV); and a second glass layer including a second conductive TGV, wherein the second glass layer is on and bonded to the first glass layer, the second conductive TGV is electrically coupled to the first conductive TGV, and the first conductive TGV and the second conductive TGV have an aspect ratio between 20:1 and 50:1.

A method and system are directed to generating, using a plurality of candidate machine learning models, a plurality of prediction outputs based on a testing dataset; determining, using the plurality of prediction outputs, a best-performing machine learning model from the plurality of candidate machine learning models based on one or more evaluation metrics; generating, using the best-performing machine learning model, one or more CAM images for an input image; and generating one or more counterfactual explanations based on the one or more CAM images and a subset of prediction outputs of the plurality of prediction outputs that correspond to the best-performing machine learning model.

An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive connector and a die that has an active side and a non-active side. The active side of the die is connected to the electrically conductive connector via interconnects. A molding compound encapsulates the die and portions of the electrically conductive connector. A thermally conductive contact extends from a thermal hotspot on the die to an entry surface of the molding compound.

The invention discloses an integrated circuit packaging method, which comprises the following steps of: 1, constructing a thermal expansion gradual change buffer layer, and arranging a buffer transition layer with a thermal expansion coefficient changing step by step between a chip and a re-wiring layer to realize smooth transition of thermal deformation between different materials, so that interface stress concentration caused by mismatching of thermal expansion is reduced; 2, flexible stress absorption layers are introduced, and the flexible stress absorption layers with elastic deformation capacity are arranged between the chip and the rewiring layer and between the rewiring layer and the substrate. A gradual change buffer structure with a thermal expansion coefficient changing step by step is introduced between a chip and a re-wiring layer and between the re-wiring layer and a substrate, and a flexible stress absorption layer with an elastic deformation capability is combined, so that thermal expansion mismatch transits from sudden change to continuous change, and generation of thermal stress in packaging is weakened from the source.

The invention relates to the technical field of integrated circuit packaging, solves the problem that a calibration process in the prior art lacks a stable displacement reference consistent with actual movement of equipment, and provides an integrated circuit visual positioning calibration method based on a pulse displacement reference and a medium. The method comprises the following steps: controlling a motion platform to move along a first direction and a second direction from a preset starting point according to a preset pulse number, and obtaining a calibration data set; acquiring pulse deviation data and pixel change data according to the calibration data set; according to the pulse deviation data and the pixel change data, obtaining a rotation deviation angle between the motion coordinate system and the imaging coordinate system; and when a target chip comprising an integrated circuit is subjected to die bonding, compensating a conversion relation between an imaging coordinate system and a motion coordinate system according to the rotation deviation angle. According to the invention, pulse displacement is introduced as a unified calibration reference, and the reliability of a visual positioning result in an integrated circuit die bonding process is improved.

In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

The invention relates to the technical field of an integrated circuit appearance inspection enhancement method for improving packaging reliability, particularly discloses an integrated circuit appearance inspection enhancement method for improving packaging reliability, and aims to solve the problems that in the prior art, the detection sensitivity of microdefects in packaging is low, and reliability evaluation lacks a quantitative basis. The method comprises the following steps: synchronously acquiring optical, infrared and X-ray multi-mode appearance data; fusing and constructing a three-dimensional geometry and material distribution model of the packaging structure; extracting three defect features of geometric morphology, thermal response and structural integrity; performing defect collaborative identification and risk grading through a weighted fusion strategy; and finally generating a structured inspection report containing defect information, risk levels and reliability prediction. According to the technical scheme, high-precision detection and reliability quantitative evaluation of potential defects such as microcracks, welding spot holes and packaging layering can be achieved, and the packaging quality control level and the detection efficiency of an integrated circuit are remarkably improved.

An exemplary package structure includes a package substrate; an integrated circuit (IC) package comprises one or more dies and having a first side and a second side opposite the first side, wherein the first side of the IC package is attached to the package substrate; a heat-dissipating lid module attached to the second side of the IC package, wherein the heat-dissipating lid module comprises an upper portion, a lower portion, and a middle portion disposed between and thermally coupled to the upper portion and the lower portion, wherein the middle portion includes a heat sink separating the heat-dissipating lid module into a liquid cooling system and a vapor chamber.

Aspects disclosed include an integrated circuit (IC) package comprising a substrate and a solder joint coupled to a corner interconnect structure of the substrate to improve the reliability of the package. Related apparatus and methods are also disclosed. The substrate includes the corner interconnect structure in a corner of the substrate. The corner interconnect structure includes a first metal interconnect adjacent to the corner of the substrate and a plurality of second metal interconnects adjacent to the first metal interconnect. The IC package includes a solder joint coupled to at least two of the metal interconnects in the corner interconnect structure improving the mechanical reliability of the IC package. In so doing, a plurality of third metal interconnects adjacent to the corner interconnect structure may be utilized for input / output (I / O) communication paths increasing the input / output of the IC package without growing the size of the package.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

The present invention discloses an automatic loading integrated circuit packaging detection device, which belongs to the field of integrated circuit processing technology, and includes a workbench, the upper surface of the workbench is bolted to a robotic arm, the upper surface of the workbench is bolted to a camera, and the internal bolts of the workbench are connected to a negative pressure adsorption plate, and the upper surface of the workbench is fixedly connected to a work plate. When the automatic loading integrated circuit packaging detection device is in operation, the chip to be tested is placed in a material box above the workbench, the chip is clamped and placed on the negative pressure adsorption plate by the robotic arm, automatic loading is achieved by the robotic arm, and appearance inspection is then achieved by the camera, and power-on inspection is completed by the automatic probe board. When the chip smokes, the motor starts working, and the clicker will make an intermittent sound at this time, which serves as a warning and emphasis, facilitates timely processing by the staff, and improves safety.

An apparatus comprising an integrated circuit package comprising a package substrate comprising an interconnect layer; and at least one dielectric material comprising hollow fillers, the at least one dielectric material in contact with at least a portion of a top side of the interconnect layer and at least a portion of a bottom side of the interconnect layer.

The invention discloses a signal integrity simulation analysis method for a digital radio frequency hybrid microsystem, and belongs to the field of advanced packaging of integrated circuits. According to the method, a complete analysis process accompanied with product research and development is established, systematic work of qualitative simulation evaluation, rule design and quantitative analysis verification is sequentially carried out in various stages of project approval demonstration, scheme design, design verification and the like of product design, and process conditions, material characteristics and rationality and feasibility of system layout are rapidly evaluated; qualitative support is provided for agile design of the scheme; designing rules and optimization ranges of structures such as a radio frequency link, a digital link and a coupling shield are formulated according to process and material rules, and accurate initial input is provided for comprehensive design of a product; according to the layout wiring form, digital, radio frequency and coupling areas are formed through division, time domain analysis, frequency domain analysis and near field analysis are carried out in a targeted mode, quantitative reference is provided for judging design reasonability, and an effective basis is provided for optimizing design content.

A package includes an encapsulant having a first side and a second side opposite to the first side, a first integrated circuit die and a second integrated circuit die embedded in the encapsulant, and a first interposer on the first side of the encapsulant. The first interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The package further includes a second interposer on the second side of the encapsulant. The second interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The second interposer optically or electrically couples the first integrated circuit die to the second integrated circuit die.

A microelectronics device with anti-counterfeiting measures that includes an integrated circuit packaging and a piezoelectric element embedded on the integrated circuit packaging, such as on the surface of the integrated circuit packaging. The piezoelectric element is configured to generate a unique identification code in response to a series of controlled mechanical stresses being applied to the piezoelectric element. Due to the inherent variability in piezoelectric responses, there is a high degree of uniqueness in the identification code making them extremely difficult for counterfeiters to replicate. Furthermore, by applying different stress sequences, a multitude of unique identification codes can be generated from a single piezoelectric element providing an additional layer of security. In this manner, by embedding a piezoelectric element on the integrated circuit packaging, a highly secure, cost-effective, and difficult to replicate anti-counterfeiting technique for the microelectronics industry has been developed.

The invention belongs to the technical field of integrated circuit packaging, and particularly relates to an integrated corrosion-resistant MEMS pressure sensor and a manufacturing method thereof. Comprising a PCB substrate, and an MEMS chip and an ASIC chip are mounted on the PCB substrate. The box dam forms double chambers for physical isolation; the box dam is bonded to the top of the PCB substrate through corrosion-resistant glue, the MEMS chip and the ASIC chip are separated through the double cavities, and the cavities where the MEMS chip is mounted are filled with corrosion-resistant protective gel so as to completely cover the MEMS chip; and the metal cover plate is bonded to the top of the box dam through corrosion-resistant glue, and a through hole is formed in one side of the top of the metal cover plate. According to the MEMS pressure sensor, the problem of miniaturization and standardization of the existing MEMS pressure sensor is solved, and the corrosion resistance requirement is met; the manufacturing process is suitable for batch high-precision machining, the product yield is improved, and the product cost is reduced.

An integrated circuit package may include a base die, a host device, a first bonding interface, a stacked memory structure, and a second bonding interface. The base die may include a first surface and a second surface. The host device may be disposed on the first surface of the base die. The first bonding interface may be located between the first surface of the base die and the host device. The stacked memory structure may be disposed on the first surface of the base die. The second bonding interface may be located between the first surface of the base die and the stacked memory structure.

The invention relates to the technical field of semiconductor manufacturing, discloses a high-precision positioning integrated circuit packaging film stripping system, and aims to overcome the defects in the aspects of flexible material processing, positioning precision stability, operation efficiency and the like in the prior art. The system comprises a high-precision visual positioning unit which is used for collecting a packaging film surface image and extracting a submicron positioning reference point coordinate; the flexible contact type clamping unit is used for fixing the edge area of the packaging film in a low-stress mode in the stripping process; and the six-degree-of-freedom precision motion platform is used for bearing and driving the flexible contact type clamping unit to execute a preset stripping track in a three-dimensional space. According to the technical scheme, submicron spatial positioning precision can be achieved, local stress concentration is remarkably reduced, material deformation is dynamically sensed and compensated, external interference is effectively isolated, the positioning process is simplified, and the overall efficiency and yield are improved.

A integrated circuit (IC) package device includes a first substrate, an IC device mounted to a first surface of the first substrate, a second substrate, and first power delivery circuitry. The second substrate is mounted to a second surface of the first substrate. The first surface is opposite the second surface. The second substrate includes a decoupling capacitor. The first power delivery circuitry is mounted to the second substrate and coupled to the IC device through the second substrate and the first substrate.

An integrated circuit package is provided in which a hybrid-bonded stack of memory dies couples through a plurality of through-mold vias to a redistribution layer. A logic die couples to the redistribution layer through a plurality of interconnects.

An integrated circuit package is provided including both an upper redistribution layer and a lower redistribution layer. A first stack of memory dies couples to the upper redistribution layer either through metal posts or through vertical wire bonds. Similarly, a second stack of memory dies couples to the lower redistribution layer either through metal posts or through vertical wire bonds. A logic die also couples to the lower redistribution layer through a plurality of interconnects.

A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.

A semiconductor die having a die interconnect and a die level distribution (DLD) metallization layer having a metal line and a metal pad having a width greater than the width of the metal line to support a larger die interconnect for improved signal path conductivity between the die interconnect and the metal pad is disclosed. Related integrated circuit (IC) packages and fabrication methods are also disclosed. The die includes a semiconductor layer, a DLD metallization structure, and a back end of line (BEOL) interconnect structure between the semiconductor layer and the DLD metallization structure. The DLD metallization structure mechanically supports die interconnects for coupling the die to another device, such as a package substrate or another die, and redistributes signals (e.g., power, ground, information) between the die interconnects and the semiconductor layer through the BEOL interconnect structure.

A method of forming an integrated circuit package includes following operations. A padding layer is formed on a portion of a carrier. A first semiconductor die is placed on the padding layer and a second semiconductor die is placed on the carrier. The first semiconductor die and the second semiconductor die are encapsulated with a first encapsulation layer. A first redistribution layer structure is formed over the first semiconductor die, the second semiconductor die and the first encapsulation layer. A third semiconductor die is placed on the first redistribution layer structure. The third semiconductor die is encapsulated with a second encapsulation layer. A second redistribution layer structure is formed over the third semiconductor die and the second encapsulation layer. The carrier is debonded. The padding layer is removed, and therefore, a recess is formed in the first encapsulation layer.

Aspects disclosed include an integrated circuit (IC) package including two substrates and vertical interconnects coupling the two substrates, the vertical interconnects comprising a metal ball and metal pin combination to address an increased distance between substrates. The vertical interconnects are disposed in a mold layer between the two substrates. The mold layer also includes a die, a plurality of metal pins, and a plurality of metal balls coupled to the plurality of metal pins to form the vertical interconnects. Larger distances between the two substrates are desirable when a die's thickness is increased to increase thermal dissipation from the die. As an example, by utilizing a plurality of metal ball and pin combinations as vertical interconnects, larger distances between the two substrates may be advantageously achieved with reduced risk of electrical shorting between vertical interconnects and without compromising pitch between vertical interconnects.

Embodiments include a device. The device includes an interposer, a package substrate, and conductive connectors bonding the package substrate to the interposer. Each of the conductive connectors have convex sidewalls. A first subset of the conductive connectors are disposed in a center of the package substrate in a top-down view. A second subset of the conductive connectors are disposed in an edge / corner of the package substrate in the top-down view. Each of the second subset of the conductive connectors have a greater height than each of the first subset of the conductive connectors.