941 results about "Integrated circuit packaging" patented technology

The invention provides a defect detection method and system for integrated circuit manufacturing. Wherein in the integrated circuit packaging stage, packaged chips are divided into a first type of chips meeting a preset physical characteristic threshold value and a second type of chips exceeding the physical characteristic threshold value through a pneumatic sorting device; performing scanning electron microscope imaging on the surface of the second type of chip, generating a three-dimensional topological structure by using an image reconstruction technology, and positioning a micron-sized particle defect area by comparing reference type differences; synchronously applying high-frequency electric signal excitation in the sorting process, detecting impedance response of the second type of chips, and recording an abnormal signal sequence exceeding a preset frequency domain range; performing space-time correlation matching on the micron-sized particle defect area and the abnormal signal sequence, and judging that the defect is a multi-layer composite defect when a preset coupling condition is met; and dynamically adjusting the mesh diameter and vibration frequency parameters of the pneumatic sorting device. According to the technical scheme provided by the invention, accurate identification of the multi-layer composite defect of the chip is realized, and the defect interception efficiency is remarkably improved.

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure having a first surface and a second surface opposite to the first surface, a high-power die over the substrate structure, a lower-power die over the high-power die, a first interposer between the first surface of the substrate structure and the high-power die, and a second interposer between the high-power die and the lower-power die. The substrate structure includes a thermal enhancement portion located under the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure. A substrate structure of the 3D integrated circuit package is also provided.

The invention discloses a shielding protection adhesive tape for semiconductor integrated circuit packaging and a preparation method thereof, and relates to the technical field of semiconductor integrated circuit packaging. The shielding protective adhesive tape for packaging the semiconductor integrated circuit is prepared by taking polyimide as a base material and coating a coating, and the coating comprises the following raw materials in parts by weight: 3-5 parts of modified nano silicon dioxide, 30-40 parts of N, N-dimethylformamide, 1-3 parts of a curing agent and 1-3 parts of a curing agent. The invention discloses a high-temperature-resistant epoxy resin coating which is prepared from the following components in parts by weight: 25-30 parts of N, N-dimethylformamide, 25-30 parts of a modified acrylate copolymer, 17-26 parts of ethyl acetate, 12-15 parts of epoxy resin, 1-2 parts of a silane coupling agent KH-550, 0.5-1 part of an antioxidant 1010, 0.3-0.8 part of an ultraviolet absorbent UV-327, 1-2 parts of carboxyl-terminated nitrile rubber, 2-4 parts of decabromodiphenyl ether, 0.1-0.3 part of an organic siloxane defoaming agent, 0.2-0.5 part of an acrylate flatting agent and 10-11 parts of diaminodiphenyl sulfone. The adhesive tape contains the modified nano silicon dioxide, the modified acrylate copolymer and other components, so that the performance of the adhesive tape is guaranteed; pretreatment is meticulous, preparation steps are standard, and mass production is easy; a finished product can be effectively shielded, and the packaging yield and the product stability can be improved.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors and multi-layer ceramic capacitors (MLCCs) are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.

The invention discloses a low-warpage damp-heat-resistant liquid epoxy molding compound as well as a preparation method and application thereof. The liquid epoxy molding compound is prepared from the following raw material components in parts by mass: 85 to 90 parts of modified silicon dioxide, 5 to 8 parts of naphthalene type epoxy resin monomer, 5 to 8 parts of anhydride curing agent, 0.1 to 0.3 part of coupling agent, 0.1 to 0.3 part of adhesion promoter and 0.2 to 0.5 part of temperature response type amine catalyst. The modified silicon dioxide is obtained by carrying out surface modification on micron-sized silicon dioxide by adopting a silane coupling agent containing an epoxy group, and the mass of the silane coupling agent containing the epoxy group is 0.3-0.8% of the mass of silicon dioxide. The liquid epoxy molding compound provided by the invention has excellent flowability, adhesive force and heat and humidity resistance, can significantly relieve and reduce the warping of a silicon wafer, and is suitable for integrated circuit packaging.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, e.g., three or more power components. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

The invention provides an integrated circuit packaging system with an isolation structure. The system comprises an isolation barrier building assembly which divides a function module and a signal path into a plurality of isolation areas; the electrical performance test assembly is responsible for applying an electrical performance test signal of the integrated circuit at the input end of the integrated circuit, collecting an output signal of the integrated circuit at the output end, and analyzing the electrical performance test signal and the output signal to obtain a quality parameter of the electrical performance test signal; and the signal path adjustment component is responsible for providing adjustment suggestions for the signal path of the current integrated circuit according to the analysis result of the quality parameters. According to the invention, electrical isolation and physical protection are ensured; the signal quality and the system performance under the isolation structure are evaluated through analysis of the test signal and the output signal; providing an optimization suggestion according to a test result, and adjusting a signal path and an isolation barrier design; and the integrated circuit packaging system with the isolation structure is ensured to reach the optimal level in the aspects of electrical performance, signal integrity and reliability.

The invention discloses a defect detection method and system for integrated circuit packaging, and the method comprises the steps: obtaining a scanning image of an integrated circuit packaging sample, and analyzing the scanning image to determine a defect region of the integrated circuit packaging sample; multi-modal data of the defect area are collected and fused, and comprehensive defect information of the integrated circuit packaging sample is obtained; counting defect types of the integrated circuit packaging sample and performance influence parameters caused by various types of defects according to the comprehensive defect information; and screening out to-be-repaired defects and negligible defects according to the defect types and performance influence parameters caused by each type of defect, and generating a visual report. The comprehensive defect information is determined by positioning the defect area and detecting the multi-modal fusion data of the defect area, so that multiple types of defects of the integrated circuit packaging sample can be determined in an all-around manner, and the defect detection precision, reliability and detection efficiency are ensured.

According to one aspect of the present disclosure, a transformer based integrated circuit (IC) package includes a portion including a recess. In some embodiments, a magnetic core disposed in the recess, wherein the recess is configured to provide a space between an interior surface of the recess and an exterior surface of the magnetic core, wherein the magnetic core includes a soft ferromagnetic material. In some embodiments, two or more support structures disposed in the recess and connected to the magnetic core and package portion. In some embodiments, a plurality of conductive traces forming first and second coils disposed about the magnetic core, wherein the first and second coils and magnetic core are configured as a transformer. In some embodiments, a molding material is configured to encapsulate a surface of the package portion and the transformer, wherein the molding material is configured to form a package body.

The present disclosure provides an integrated circuit (IC) structure that includes an IC packaging structure having an IC chip; and a thermoelectric self-cooling device (TESCD) integrated with the IC packaging structure. The TESCD further includes a thermoelectric cooling (TEC) device having a plurality of TEC units configured in an array and electrically connected to provide cooling effect to the IC packaging structure, and a liquid cooling module having a cooling liquid driving device and a generator coupled with the cooling liquid driving device to collectively generate an electrical power supplied to the TEC device with self-cooling function to the IC packaging structure.

Methods, systems, and methods of manufacture are described for integrating memory and compute die in a stacked configuration in an integrated circuit package without through silicon via. A packaging apparatus that includes a first semiconductor die comprising multiple memory cells and a second semiconductor die comprising compute logic representing a Processing-in-Memory (PiM) architecture. The PiM architecture is configured to process data stored at the memory cells. The first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data routed from a memory cell of the first semiconductor die.

Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a first glass layer including a first conductive through-glass via (TGV); and a second glass layer including a second conductive TGV, wherein the second glass layer is on and bonded to the first glass layer, the second conductive TGV is electrically coupled to the first conductive TGV, and the first conductive TGV and the second conductive TGV have an aspect ratio between 20:1 and 50:1.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die on the interposer, the integrated circuit die including a plurality of transistors. The carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact pad is directly over one or more of the top metal structures with the bonding layer between the dummy contact pads and the top metal structures. Embodiments of the present disclosure also relate to a method of forming an integrated circuit package.

Interposer substrate with integrated step die cavity, and related integrated circuit (IC) packages and related fabrication methods. A die cavity integrated in an outer layer(s) of the interposer substrate provides room for a die to extend into the interposer substrate (e.g., to facilitate increased die height). Forming the die cavity in the outer layer(s) facilitates metal interconnects in an outer metallization layer of the interposer substrate being located adjacent to the die cavity can also enhance heat dissipation for the die extending into the die cavity. Forming the die cavity in the outer layer(s) of the interposer substrate also facilitates reduced distance between the interposer substrate and package substrate to facilitate reduced height vertical interconnects coupling the interposer substrate to the package substrate. This facilitates vertical interconnects with reduced aspect ratio and reduced pitch that can support dies with higher input / output (I / O) connection density.

A method and system are directed to generating, using a plurality of candidate machine learning models, a plurality of prediction outputs based on a testing dataset; determining, using the plurality of prediction outputs, a best-performing machine learning model from the plurality of candidate machine learning models based on one or more evaluation metrics; generating, using the best-performing machine learning model, one or more CAM images for an input image; and generating one or more counterfactual explanations based on the one or more CAM images and a subset of prediction outputs of the plurality of prediction outputs that correspond to the best-performing machine learning model.

Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.

The invention discloses a dual in-line packaging integrated circuit rib cutter, and belongs to the technical field of integrated circuit packaging. Comprising a supporting column, a base plate, a three-axis adjustable air cylinder, an air cylinder adapter, a cutter seat, a lower cutter gasket, a lower cutter, a positioning block, an upper cutter, a scraping piece, a scraping piece three-axis air cylinder, a probe seat, a correlation optical fiber probe, an optical fiber amplifier, a PLC, a cutter electromagnetic valve and a scraping piece electromagnetic valve. The integrated design of a lower installation part, a stroke-adjustable lower cutter, an elastic pressing cutter and an upper cutter is adopted, and the design that waste is automatically scraped, product rib cutting is automatically detected, and rib cutting is conducted on the two sides of a product step by step is adopted. The rib cutting machine has the advantages of high rib cutting quality, high rib cutting speed, wide product adaptability and simple and reliable structure. The problems that in an existing full-manual rib cutting technology, the rib cutting operation labor intensity is large, the rib cutting quality consistency is poor, the rib cutting efficiency is low, the side rib splashing direction cannot be controlled, and lower cutters collide with one another are solved. The cutting device is applied to the technical field of cutting of the pin edge ribs of the dual-in-line packaging shell of the electronic component.

Integrated circuit package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce a die to a substrate clearance and related fabrication methods are disclosed. The IC package includes die interconnects coupled to first metal pad(s) of respective metal interconnects of a metallization layer of the substrate to provide support and signal routing paths. To reduce clearance between the die and the substrate and consequently the height of the IC package, a second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is coupled to the first metal pad(s). Solder is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate. When the solder is heated to form the solder joint, the solder flows along the reduced cross-sectional area of the second, additional metal pad(s).

An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive connector and a die that has an active side and a non-active side. The active side of the die is connected to the electrically conductive connector via interconnects. A molding compound encapsulates the die and portions of the electrically conductive connector. A thermally conductive contact extends from a thermal hotspot on the die to an entry surface of the molding compound.

The invention discloses an integrated circuit packaging method, which comprises the following steps of: 1, constructing a thermal expansion gradual change buffer layer, and arranging a buffer transition layer with a thermal expansion coefficient changing step by step between a chip and a re-wiring layer to realize smooth transition of thermal deformation between different materials, so that interface stress concentration caused by mismatching of thermal expansion is reduced; 2, flexible stress absorption layers are introduced, and the flexible stress absorption layers with elastic deformation capacity are arranged between the chip and the rewiring layer and between the rewiring layer and the substrate. A gradual change buffer structure with a thermal expansion coefficient changing step by step is introduced between a chip and a re-wiring layer and between the re-wiring layer and a substrate, and a flexible stress absorption layer with an elastic deformation capability is combined, so that thermal expansion mismatch transits from sudden change to continuous change, and generation of thermal stress in packaging is weakened from the source.

The invention relates to the technical field of integrated circuit packaging, solves the problem that a calibration process in the prior art lacks a stable displacement reference consistent with actual movement of equipment, and provides an integrated circuit visual positioning calibration method based on a pulse displacement reference and a medium. The method comprises the following steps: controlling a motion platform to move along a first direction and a second direction from a preset starting point according to a preset pulse number, and obtaining a calibration data set; acquiring pulse deviation data and pixel change data according to the calibration data set; according to the pulse deviation data and the pixel change data, obtaining a rotation deviation angle between the motion coordinate system and the imaging coordinate system; and when a target chip comprising an integrated circuit is subjected to die bonding, compensating a conversion relation between an imaging coordinate system and a motion coordinate system according to the rotation deviation angle. According to the invention, pulse displacement is introduced as a unified calibration reference, and the reliability of a visual positioning result in an integrated circuit die bonding process is improved.

The invention discloses an integrated circuit 3D packaging structure based on general IPs and a packaging method thereof, and belongs to the technical field of semiconductors. Hot spot areas of all layers of general IPs can be accurately identified through thermal simulation, stress concentration areas are identified in combination with simulation, then through-silicon-via parameters are adjusted, heat conduction paths are optimized, local temperature is effectively reduced, and the packaging efficiency is improved. Mechanical stress is relieved while the thermal reliability of the chip is improved, chip cracking or failure caused by stress concentration is avoided, and the structural reliability of packaging is improved; and comparing the cross-sectional view of the through-silicon via with a corresponding expected cross-sectional view of the through-silicon via, identifying abnormal depth points, adjusting etching parameters of the corresponding through-silicon via at the abnormal depth points, and repeatedly adjusting the etching parameters until the number of the abnormal depth points is zero, so that the aperture of the etched through-silicon via is close to an expected value, and the packaging quality is improved. The finished product performance is ensured.

In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

The invention relates to the technical field of an integrated circuit appearance inspection enhancement method for improving packaging reliability, particularly discloses an integrated circuit appearance inspection enhancement method for improving packaging reliability, and aims to solve the problems that in the prior art, the detection sensitivity of microdefects in packaging is low, and reliability evaluation lacks a quantitative basis. The method comprises the following steps: synchronously acquiring optical, infrared and X-ray multi-mode appearance data; fusing and constructing a three-dimensional geometry and material distribution model of the packaging structure; extracting three defect features of geometric morphology, thermal response and structural integrity; performing defect collaborative identification and risk grading through a weighted fusion strategy; and finally generating a structured inspection report containing defect information, risk levels and reliability prediction. According to the technical scheme, high-precision detection and reliability quantitative evaluation of potential defects such as microcracks, welding spot holes and packaging layering can be achieved, and the packaging quality control level and the detection efficiency of an integrated circuit are remarkably improved.

An exemplary package structure includes a package substrate; an integrated circuit (IC) package comprises one or more dies and having a first side and a second side opposite the first side, wherein the first side of the IC package is attached to the package substrate; a heat-dissipating lid module attached to the second side of the IC package, wherein the heat-dissipating lid module comprises an upper portion, a lower portion, and a middle portion disposed between and thermally coupled to the upper portion and the lower portion, wherein the middle portion includes a heat sink separating the heat-dissipating lid module into a liquid cooling system and a vapor chamber.

An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.

Aspects disclosed include an integrated circuit (IC) package comprising a substrate and a solder joint coupled to a corner interconnect structure of the substrate to improve the reliability of the package. Related apparatus and methods are also disclosed. The substrate includes the corner interconnect structure in a corner of the substrate. The corner interconnect structure includes a first metal interconnect adjacent to the corner of the substrate and a plurality of second metal interconnects adjacent to the first metal interconnect. The IC package includes a solder joint coupled to at least two of the metal interconnects in the corner interconnect structure improving the mechanical reliability of the IC package. In so doing, a plurality of third metal interconnects adjacent to the corner interconnect structure may be utilized for input / output (I / O) communication paths increasing the input / output of the IC package without growing the size of the package.

Device package (300, 550), comprising: an interposer (200), comprising: a semiconductor substrate (202); first vias (201) extending through the semiconductor substrate (202), the vias (201) protruding from a front side of the semiconductor substrate (202); an interconnect structure (206) over the front side of the semiconductor substrate (202), the interconnect structure (206) comprising: a first metallization structure (206A) in an inorganic insulating material (206B); and a passivation film (210, 212) over the first metallization structure (206A); and a first redistribution structure (240) over the passivation film (210, 212), the first redistribution structure (240) comprising a second metallization structure (218, 222, 226, 230, 234) in an organic insulating material (216, 220, 224, 228, 232, 236), the first redistribution structure (240) being flush with the interconnect structure (206) and the semiconductor substrate (202); an integrated circuit die (100A) over and attached to the interposer (200); and a first encapsulation material (304) around the integrated circuit die (100A).