1113 results about "Integrated circuit packaging" patented technology

The invention provides a defect detection method and system for integrated circuit manufacturing. Wherein in the integrated circuit packaging stage, packaged chips are divided into a first type of chips meeting a preset physical characteristic threshold value and a second type of chips exceeding the physical characteristic threshold value through a pneumatic sorting device; performing scanning electron microscope imaging on the surface of the second type of chip, generating a three-dimensional topological structure by using an image reconstruction technology, and positioning a micron-sized particle defect area by comparing reference type differences; synchronously applying high-frequency electric signal excitation in the sorting process, detecting impedance response of the second type of chips, and recording an abnormal signal sequence exceeding a preset frequency domain range; performing space-time correlation matching on the micron-sized particle defect area and the abnormal signal sequence, and judging that the defect is a multi-layer composite defect when a preset coupling condition is met; and dynamically adjusting the mesh diameter and vibration frequency parameters of the pneumatic sorting device. According to the technical scheme provided by the invention, accurate identification of the multi-layer composite defect of the chip is realized, and the defect interception efficiency is remarkably improved.

The invention provides a method and a system for evaluating the packaging tightness of an integrated circuit in a high-temperature environment, and relates to the technical field of circuit testing, and the method comprises the steps: obtaining the temperature, tracer gas concentration and gas pressure data of the integrated circuit, and extracting temperature nonlinear features; non-local weighted adaptive anisotropic diffusion filtering and mixed tensor decomposition are utilized to obtain concentration multi-dimensional distribution features, air pressure frequency domain features are extracted, and feature fusion and space-time dependency analysis are performed through a quantum depth auto-encoder, a multi-head cross attention network and a heterogeneous space-time diagram neural network. Time sequence features are extracted through waveform dynamic time warping and a bidirectional gating circulation attention network, sealing defect diagnosis is performed based on knowledge distillation, a failure trend is predicted by using a causal long-short term memory network, and a failure mode is matched in combination with a dynamic heterogeneous knowledge graph. And a multi-target Pareto differential evolution algorithm is adopted to evaluate the packaging reliability and generate an evaluation report.

The invention provides a dynamic method and system for thermal fatigue evaluation of integrated circuit packaging, and relates to the technical field of integrated circuits, and the method comprises the steps: employing a genetic algorithm to determine the arrangement position of a temperature sensor, and collecting a temperature data sequence of a temperature sensor array and the corresponding time information; establishing a thermal-mechanical coupling analysis model comprising a geometric model, a material constitutive relationship and a load boundary, and performing mesh generation on the thermal-mechanical coupling analysis model to obtain a finite element model; based on the finite element model, periodically solving by adopting a nonlinear iterative algorithm to obtain a welding spot stress-strain field data sequence and time information corresponding to the welding spot stress-strain field data sequence, establishing a corrected Coffin-Manson model considering a temperature-stress-time coupling effect, calculating a fatigue damage increment of the welding spot, and accumulating the fatigue damage increment in real time; and performing thermal fatigue state evaluation on the integrated circuit packaging structure according to the change rate of the accumulated fatigue damage value.

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

The invention belongs to the technical field of chip packaging, particularly relates to an integrated circuit packaging module with a detachable structure and a packaging method, and aims to solve the problem that an existing integrated circuit packaging module cannot be quickly detached after being packaged, and the following scheme is provided: the integrated circuit packaging module comprises a packaging base, a packaging upper cover is arranged on the upper side of the packaging base, and a detachable structure is arranged on the packaging upper cover; the packaging upper cover is arranged on the packaging base, two symmetrical insertion bolts are arranged on the packaging upper cover, dismounting modules are arranged outside the two insertion bolts, each dismounting module comprises a cylinder body, and two symmetrical grooves are formed in the upper side of the packaging base. According to the integrated circuit packaging module containing the detachable structure and the packaging method disclosed by the invention, the packaging module for packaging the integrated circuit body can be rapidly and conveniently disassembled, so that the integrated circuit body can be conveniently taken out, the polishing operation required during conventional package disassembly is effectively avoided, the package disassembly efficiency is greatly improved, and the packaging cost is reduced. And meanwhile, the integrity and the use function of the detached integrated circuit body are also ensured.

In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure having a first surface and a second surface opposite to the first surface, a high-power die over the substrate structure, a lower-power die over the high-power die, a first interposer between the first surface of the substrate structure and the high-power die, and a second interposer between the high-power die and the lower-power die. The substrate structure includes a thermal enhancement portion located under the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure. A substrate structure of the 3D integrated circuit package is also provided.

The invention discloses a shielding protection adhesive tape for semiconductor integrated circuit packaging and a preparation method thereof, and relates to the technical field of semiconductor integrated circuit packaging. The shielding protective adhesive tape for packaging the semiconductor integrated circuit is prepared by taking polyimide as a base material and coating a coating, and the coating comprises the following raw materials in parts by weight: 3-5 parts of modified nano silicon dioxide, 30-40 parts of N, N-dimethylformamide, 1-3 parts of a curing agent and 1-3 parts of a curing agent. The invention discloses a high-temperature-resistant epoxy resin coating which is prepared from the following components in parts by weight: 25-30 parts of N, N-dimethylformamide, 25-30 parts of a modified acrylate copolymer, 17-26 parts of ethyl acetate, 12-15 parts of epoxy resin, 1-2 parts of a silane coupling agent KH-550, 0.5-1 part of an antioxidant 1010, 0.3-0.8 part of an ultraviolet absorbent UV-327, 1-2 parts of carboxyl-terminated nitrile rubber, 2-4 parts of decabromodiphenyl ether, 0.1-0.3 part of an organic siloxane defoaming agent, 0.2-0.5 part of an acrylate flatting agent and 10-11 parts of diaminodiphenyl sulfone. The adhesive tape contains the modified nano silicon dioxide, the modified acrylate copolymer and other components, so that the performance of the adhesive tape is guaranteed; pretreatment is meticulous, preparation steps are standard, and mass production is easy; a finished product can be effectively shielded, and the packaging yield and the product stability can be improved.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors and multi-layer ceramic capacitors (MLCCs) are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.

The invention discloses a low-warpage damp-heat-resistant liquid epoxy molding compound as well as a preparation method and application thereof. The liquid epoxy molding compound is prepared from the following raw material components in parts by mass: 85 to 90 parts of modified silicon dioxide, 5 to 8 parts of naphthalene type epoxy resin monomer, 5 to 8 parts of anhydride curing agent, 0.1 to 0.3 part of coupling agent, 0.1 to 0.3 part of adhesion promoter and 0.2 to 0.5 part of temperature response type amine catalyst. The modified silicon dioxide is obtained by carrying out surface modification on micron-sized silicon dioxide by adopting a silane coupling agent containing an epoxy group, and the mass of the silane coupling agent containing the epoxy group is 0.3-0.8% of the mass of silicon dioxide. The liquid epoxy molding compound provided by the invention has excellent flowability, adhesive force and heat and humidity resistance, can significantly relieve and reduce the warping of a silicon wafer, and is suitable for integrated circuit packaging.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, e.g., three or more power components. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

The invention provides an integrated circuit packaging system with an isolation structure. The system comprises an isolation barrier building assembly which divides a function module and a signal path into a plurality of isolation areas; the electrical performance test assembly is responsible for applying an electrical performance test signal of the integrated circuit at the input end of the integrated circuit, collecting an output signal of the integrated circuit at the output end, and analyzing the electrical performance test signal and the output signal to obtain a quality parameter of the electrical performance test signal; and the signal path adjustment component is responsible for providing adjustment suggestions for the signal path of the current integrated circuit according to the analysis result of the quality parameters. According to the invention, electrical isolation and physical protection are ensured; the signal quality and the system performance under the isolation structure are evaluated through analysis of the test signal and the output signal; providing an optimization suggestion according to a test result, and adjusting a signal path and an isolation barrier design; and the integrated circuit packaging system with the isolation structure is ensured to reach the optimal level in the aspects of electrical performance, signal integrity and reliability.

The invention discloses a defect detection method and system for integrated circuit packaging, and the method comprises the steps: obtaining a scanning image of an integrated circuit packaging sample, and analyzing the scanning image to determine a defect region of the integrated circuit packaging sample; multi-modal data of the defect area are collected and fused, and comprehensive defect information of the integrated circuit packaging sample is obtained; counting defect types of the integrated circuit packaging sample and performance influence parameters caused by various types of defects according to the comprehensive defect information; and screening out to-be-repaired defects and negligible defects according to the defect types and performance influence parameters caused by each type of defect, and generating a visual report. The comprehensive defect information is determined by positioning the defect area and detecting the multi-modal fusion data of the defect area, so that multiple types of defects of the integrated circuit packaging sample can be determined in an all-around manner, and the defect detection precision, reliability and detection efficiency are ensured.

According to one aspect of the present disclosure, a transformer based integrated circuit (IC) package includes a portion including a recess. In some embodiments, a magnetic core disposed in the recess, wherein the recess is configured to provide a space between an interior surface of the recess and an exterior surface of the magnetic core, wherein the magnetic core includes a soft ferromagnetic material. In some embodiments, two or more support structures disposed in the recess and connected to the magnetic core and package portion. In some embodiments, a plurality of conductive traces forming first and second coils disposed about the magnetic core, wherein the first and second coils and magnetic core are configured as a transformer. In some embodiments, a molding material is configured to encapsulate a surface of the package portion and the transformer, wherein the molding material is configured to form a package body.

The present disclosure provides an integrated circuit (IC) structure that includes an IC packaging structure having an IC chip; and a thermoelectric self-cooling device (TESCD) integrated with the IC packaging structure. The TESCD further includes a thermoelectric cooling (TEC) device having a plurality of TEC units configured in an array and electrically connected to provide cooling effect to the IC packaging structure, and a liquid cooling module having a cooling liquid driving device and a generator coupled with the cooling liquid driving device to collectively generate an electrical power supplied to the TEC device with self-cooling function to the IC packaging structure.

The invention relates to the field of ceramic materials, in particular to a silicon nitride ceramic substrate and a preparation method thereof.The silicon nitride ceramic substrate is prepared from, by weight, 80-100 parts of silicon nitride, 5-10 parts of carbon nanotubes, 5-10 parts of a sintering aid, 5-10 parts of a binder, 1-3 parts of dibutyl phthalate, 1-3 parts of ammonium polyacrylate and 50-70 parts of deionized water. The binder is sulfonic modified polyvinyl alcohol, rare earth fluoride and nano iron particles are deposited on the surfaces of the carbon nanotubes, the prepared silicon nitride ceramic substrate has high mechanical strength and excellent heat-conducting property, a water-based tape casting process is adopted, use of a large amount of organic solvent is avoided, and the silicon nitride ceramic substrate is environment-friendly and energy-saving. The safety and environmental protection problems in the large-scale production process are fewer, and the application requirements of high-integration circuit packaging substrate materials can be met.

Methods, systems, and methods of manufacture are described for integrating memory and compute die in a stacked configuration in an integrated circuit package without through silicon via. A packaging apparatus that includes a first semiconductor die comprising multiple memory cells and a second semiconductor die comprising compute logic representing a Processing-in-Memory (PiM) architecture. The PiM architecture is configured to process data stored at the memory cells. The first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data routed from a memory cell of the first semiconductor die.

Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a first glass layer including a first conductive through-glass via (TGV); and a second glass layer including a second conductive TGV, wherein the second glass layer is on and bonded to the first glass layer, the second conductive TGV is electrically coupled to the first conductive TGV, and the first conductive TGV and the second conductive TGV have an aspect ratio between 20:1 and 50:1.

A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

The invention provides an integrated circuit packaging structure for multi-chip packaging, and relates to the technical field of chip packaging, the integrated circuit packaging structure comprises a packaging box, a plurality of chip mounting grooves are formed in one side of the packaging box in a penetrating manner and are arranged at intervals, pin mounting grooves are formed in the two sides of the interior of the bottom of each chip mounting groove, and filling sheets are arranged in the pin mounting grooves; the pin mounting groove can be filled with the filling sheet, the top surface of the filling sheet is flush with the inner wall of the bottom of the chip mounting groove, the inner walls of the two sides of the chip mounting groove are provided with storage grooves, and the filling sheet can be stored in the storage grooves; and a pressing strip is mounted in the storage groove. According to the integrated circuit packaging structure for multi-chip packaging provided by the invention, the packaging box, the filling sheet, the pressing strip, the cooling fins and the adjusting structure are arranged, so that disassembly of the chips is ensured, the situation of jamming in the disassembly and assembly process is reduced, pressing of the pins and installation of the cooling fins can be completed at the same time, the procedures of installation and disassembly are reduced, and the production efficiency is improved. Working efficiency is improved, and operation is simple and convenient.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die on the interposer, the integrated circuit die including a plurality of transistors. The carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact pad is directly over one or more of the top metal structures with the bonding layer between the dummy contact pads and the top metal structures. Embodiments of the present disclosure also relate to a method of forming an integrated circuit package.

The invention relates to the technical field of integrated circuit packaging, in particular to a three-dimensional stacked packaging system for a high-power integrated circuit. Comprising a shell, a plurality of sets of limiting shafts are arranged in the shell, a plurality of sets of spacing assemblies and a plurality of sets of slide glass mechanisms are slidably connected to the plurality of sets of limiting shafts, and the plurality of sets of slide glass mechanisms and the plurality of sets of spacing assemblies are arranged in a staggered mode; the slide glass mechanism comprises a limiting frame, and an integrated circuit chip is inserted into the limiting frame; the spacing assembly comprises a partition plate, and a plurality of adjusting mechanisms are installed on the partition plate in an embedded mode. The integrated circuit chips needing to be packaged are respectively placed in one group of chip carrying mechanisms, the integrated circuit chips are stacked and packaged, and the distance between the two adjacent groups of integrated circuit chips can be automatically adjusted according to the heating condition of the integrated circuit chips while the two adjacent groups of integrated circuit chips are electrically connected through the spacing assembly.

The invention discloses a novel three-dimensional packaging structure based on a flexible substrate and a chip heat dissipation method, particularly relates to the technical field of micro three-dimensional integrated circuit packaging structures, and solves the problems that in the prior art, a chip packaging structure is low in integration level and poor in heat dissipation performance, and the manufacturing process of a silicon through hole technology in advanced packaging is complex; in the prior art, a silicon chip needs to be drilled and filled with a conductive material, so that the production cost is increased, the drilling and filling process has extremely high requirements on precision and control, and secondly, signal interference is caused, and a series of signal distortion and crosstalk problems can be caused in the field of high-frequency signals due to the fact that a TSV is vertical; according to the technical scheme, a rigid-flexible combined packaging structure, a rigid metal stable three-dimensional packaging structure and a flexible substrate are adopted, and expensive technologies such as through silicon vias are not used; according to the three-dimensional packaging structure, essence of the rigid substrate and essence of the flexible substrate are respectively taken, dregs are removed, and the rigid substrate and the flexible substrate make up for each other.

Interposer substrate with integrated step die cavity, and related integrated circuit (IC) packages and related fabrication methods. A die cavity integrated in an outer layer(s) of the interposer substrate provides room for a die to extend into the interposer substrate (e.g., to facilitate increased die height). Forming the die cavity in the outer layer(s) facilitates metal interconnects in an outer metallization layer of the interposer substrate being located adjacent to the die cavity can also enhance heat dissipation for the die extending into the die cavity. Forming the die cavity in the outer layer(s) of the interposer substrate also facilitates reduced distance between the interposer substrate and package substrate to facilitate reduced height vertical interconnects coupling the interposer substrate to the package substrate. This facilitates vertical interconnects with reduced aspect ratio and reduced pitch that can support dies with higher input / output (I / O) connection density.

The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a micro-channel packaging structure based on cooling liquid cooling and a packaging method thereof. Comprising a packaging body, a plurality of grooves are symmetrically formed in the upper surface and the lower surface of the packaging body, functional chips are mounted in the grooves, and active bonding pads of the functional chips face the outer side; the metal wiring layers are respectively arranged on the surfaces of the functional chips on the upper side and the lower side; the silicon through holes are vertically formed in the left side and the right side of the packaging body respectively, copper layers are filled in the silicon through holes to form a silicon through hole structure, and the metal wiring layers on the upper side and the lower side are conducted through the silicon through hole structure; the micro-channel groove is formed between the functional chips on the upper side and the lower side in the left-right direction, and the two ends of the micro-channel groove extend in the vertical direction and are exposed to the outside. Liquid helium is introduced to improve the heat dissipation effect of the double-sided chip, double-sided interconnection is realized by using the silicon through hole structure, and the heat dissipation problem of the high-performance chip can be effectively solved while the integration degree is improved.

A method and system are directed to generating, using a plurality of candidate machine learning models, a plurality of prediction outputs based on a testing dataset; determining, using the plurality of prediction outputs, a best-performing machine learning model from the plurality of candidate machine learning models based on one or more evaluation metrics; generating, using the best-performing machine learning model, one or more CAM images for an input image; and generating one or more counterfactual explanations based on the one or more CAM images and a subset of prediction outputs of the plurality of prediction outputs that correspond to the best-performing machine learning model.

Aspects disclosed herein include integrated circuit (IC) packages employing capacitor interposer substrates with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies ("dies") electrically coupled to a package substrate that supports electrical signal routing to and from the die (s). A capacitor interposer substrate is disposed between the die (s) and the package substrate. The die (s) are coupled to the embedded capacitor (s) in the capacitor interposer substrate through a die interconnect coupled to an external interconnect of the capacitor interposer substrate. In an exemplary aspect, external interconnects on an outer surface of a capacitor interposer substrate are aligned. In this manner, if the die (s) and the package substrate have a pattern of die interconnects and external interconnects designed to align with each other when coupled to each other, the capacitor interposer substrate may remain compatible with the interconnects of the die (s) and the package substrate.

Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.