120 results about "Silicon interposer" patented technology

The invention relates to the technical field of edge computing, and discloses an intelligent edge computing co-processing system based on an integrated circuit, which comprises a heterogeneous computing cluster module, a hardware computing unit set, a multi-core control processor based on RISC-V, a programmable pulse tensor computing array and a reconfigurable engine oriented to streaming processing, according to the intelligent edge computing cooperative processing system based on the integrated circuit, zero-delay data exchange is realized through silicon intermediate layer integration of the heterogeneous computing cluster module and a snakelike data channel, and traditional bus arbitration delay is eliminated through real-time operation code analysis and optimal optical communication path mapping of the hardware task routing matrix (TRF) module; the priority path distribution of the task scheduling subsystem is synchronously coordinated with the time-sensitive task, so that the collaborative efficiency of the computing unit is improved in multiple dimensions, the non-blocking transmission of the high-priority task is ensured, and the effect of enhancing the overall processing capability and response speed of the intelligent edge computing is achieved.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

The invention provides a chip packaging structure and electronic equipment, relates to the technical field of chips, and can meet the requirement of high bandwidth density between chips on the basis of supporting integration of heterogeneous chips (die). The chip packaging structure comprises a first chip, an electronic element and a hybrid adapter plate with a novel structure. The hybrid adapter plate comprises a silicon interposer and a rewiring layer, the front surface of the silicon interposer is provided with a metal wiring layer, and the silicon interposer is provided with a silicon through hole. The first chip is arranged on the front surface of the silicon interposer and is electrically connected with the metal wiring layer. Or the hybrid adapter plate comprises a first rewiring layer, a second rewiring layer, a bridge chip and a metal connecting structure, the bridge chip and the metal connecting structure are located between the two rewiring layers, and the bridge chip achieves interconnection between the first chips through the first rewiring layer. The second redistribution layer is connected with the first redistribution layer through a metal connection structure. The electronic component is located on the back face of the redistribution layer and connected with the redistribution layer or connected with the redistribution layer through the substrate.

The present application relates to the technical field of dies, and provides a die packaging structure and an electronic device, which can satisfy the high-bandwidth density requirement for dies while supporting heterogeneous die integration. The die packaging structure comprises a first die, an electronic element and a hybrid interposer of a novel structure. The hybrid interposer comprises a silicon interposer and a redistribution layer, a metal wiring layer is provided on the front surface of the silicon interposer, and a through silicon via is formed in the silicon interposer. The first die is disposed on the front surface of the silicon interposer and is electrically connected to the metal wiring layer. Alternatively, the hybrid interposer comprises a first redistribution layer, a second redistribution layer, a bridge die located between the two redistribution layers, and a metal connecting structure, and the bridge die achieves interconnection between first dies by means of the first redistribution layer. The second redistribution layer is connected to the first redistribution layer by means of the metal connecting structure. The electronic element is located on the back surface of the redistribution layer, is connected to the redistribution layer or is connected to the redistribution layer by means of a substrate.

The invention discloses a broadband double-layer interconnection structure based on a silicon adapter plate technology, and belongs to the technical field of radio frequency microsystems. According to the method, a three-dimensional compensation structure is formed by adding square conductive metal and TSVs into lower-layer metal at one end, close to a transition structure, of an original coplanar waveguide transmission line, and a resonance point with return loss of-51dB is introduced at 17.59 GHz, so that the broadband interconnection effect that the return loss of 0-33GHz is smaller than or equal to-20dB is achieved, and the in-band insertion loss fluctuation value is reduced by 11.6% compared with that of the original structure. Compared with a traditional interconnection structure broadband design, the method has the advantages that on the premise that the plane area is not increased, the broadband interconnection design difficulty is greatly reduced through the three-dimensional structure design.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

Provided are systems, methods, and apparatuses for high bandwidth memory configurations. In one or more examples, the systems, devices, and methods include positioning a first memory physical layer (PHY) interface on a surface of a compute die and connecting a first memory to the first memory PHY interface of the compute die via a first through-silicon via (TSV) connection. The systems, devices, and methods include connecting a second memory to a base die that connects to the compute die via a silicon interposer, positioning the compute die on the silicon interposer, and positioning the base die on the silicon interposer.

A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

The invention relates to the field of chips, and discloses an HBM packaging-based cache structure and electronic equipment, and the structure is characterized in that a first surface of a silicon interposer is provided with a calculation bare chip and a first HBM stack, the first HBM stack is located outside a coverage area of the calculation bare chip, a second surface of the silicon interposer is provided with a second HBM stack and a third HBM stack, a part of a storage area of the second HBM stack is located in the coverage area, and the third HBM stack is located in the coverage area; the third HBM stack is completely located in the coverage area; the priority sensing module in the computing bare chip determines the priority of cache data, the address mapping module selects a storage area for mapping the cache data from the first HBM stack, the second HBM stack and the third HBM stack according to the priority of the cache data, the routing module allocates interconnection paths, the first HBM stack and the second HBM stack are located in the storage area outside a coverage area, and the first HBM stack and the second HBM stack are located in the storage area outside the coverage area. The second HBM stack is located in a storage area in the coverage area, and the priorities of the stored cache data of the third HBM stack are sequentially increased. And the high-priority cache data delay is reduced.

This invention relates to the field of chip technology, and more particularly to a memory system based on the UBM protocol packaging, comprising a UBM device, a silicon interposer, and a GPU, wherein the GPU includes a UBM physical layer; the UBM device, silicon interposer, and UBM physical layer are interconnected based on a preset UBM physical interconnect protocol, where UBM is an ultra-high bandwidth memory, with a bandwidth higher than that of HBM4; the UBM physical interconnect protocol includes: the UBM device being connected to the silicon interposer using a hybrid bonding packaging method, the UBM physical layer being connected to the silicon interposer using a hybrid bonding packaging method, and the UBM device and the UBM physical layer establishing an interconnection through wiring resources in the silicon interposer. This invention improves the bandwidth line density and bandwidth areal density of the memory system packaging structure.

This invention provides an ultra-thin 2.5D packaging structure and method, which reduces the thickness of the package and shortens the process flow. An ultra-thin 2.5D packaging structure includes: a functional chipset comprising at least two sets of functional chips, each set of functional chips having a first dielectric material layer on its lower surface, and an exposed copper pad at the bottom of the first dielectric material layer; a silicon interposer board comprising a silicon interposer board body, a second dielectric material layer on top, and a third dielectric material layer on the bottom, the second dielectric material layer having an exposed mating copper pad on its surface, metal circuitry within the second dielectric material layer, a TSV copper pillar embedded in the silicon interposer board body, the upper part of the TSV copper pillar being connected to the corresponding metal circuitry, and the lower part of the TSV copper pillar being inserted into the third dielectric material layer; a plurality of bump structures; a substrate including an upper connecting pad and a lower connecting pad; a molding compound; and an adhesive filler layer.

A chip packaging method and chip packaging structure are provided. The method includes: providing a substrate, a plurality of silicon wafers, and a plurality of chips; forming a plurality of sets of conductive connection structures on the plurality of silicon wafers respectively to form a plurality of silicon interposer plates; where at least one of the plurality of silicon interposer plates is different from other silicon interposer plates of the plurality of silicon interposer plates; cutting the plurality of silicon interposer plates respectively to obtain a plurality of silicon interposer blocks; selecting a plurality of target silicon interposer blocks from the plurality of silicon interposer blocks, and fixing the plurality of target silicon interposer blocks on the substrate; and interconnecting and arranging the plurality of chips on corresponding target silicon interposer blocks of the plurality of target silicon interposer blocks respectively.

A semiconductor die layer for a semiconductor package includes a first semiconductor die and a second semiconductor die adjacent the first semiconductor die. The first and second semiconductor dies are joined together by a filling material located between the dies. First and second RDLs are provided on first and second surfaces of the semiconductor die layer. Each RDL includes traces that enable the first semiconductor die to be directly coupled to the second semiconductor die, thereby eliminating the need for a silicon interposer. Vias are provided in the filling material and enable vertical communication between different semiconductor die layers that are included in the semiconductor package. Solder balls are provided on the second RDL and enable a semiconductor die layer to be directly coupled to a PCB or another semiconductor die layer.

The invention provides a packaging method of a chip embedded type silicon adapter plate, which is used for solving the problems of mismatch of thermal expansion coefficients and overlarge packaging warping in packaging in the prior art. A groove is formed in a silicon adapter plate through etching, the groove is used for embedding an element, and then the upper / lower surface of the silicon adapter plate is electrically connected with the embedded element through a vertical interconnection structure of a silicon through hole.

An optical package with increased mechanical stability of co-packaged optic components is described. The optical package includes an electronic mold compound (EMC) layer with copper pillars formed through the EMC layer. The optical package also includes a silicon interposer layer with through silicon vias (TSVs) and positioned on the EMC layer. A combined thickness of the EMC layer and the silicon interposer layer provide a combined mechanical coupling thickness for a connection component on a smooth diced edge side of the EMC layer and the silicon interposer layer. The optical package also includes devices attached to the silicon interposer layer.

A method of configuring a memory, a memory package, and a system on chip are provided. In one or more examples, the method includes disposing a first memory physical layer (PHY) interface on a surface of a computing die and connecting a first memory to the first memory PHY interface of the computing die via a first through silicon via (TSV) connection. The method includes connecting the second memory to a base die connected to the computing die via a silicon intermediate, disposing the computing die on the silicon intermediate, and disposing the base die on the silicon intermediate.

A chip packaging method and a chip packaging structure are provided. The method includes: providing a carrier and wafers, where at least one wafer is different from others; cutting each wafer to form chips; selecting target chips from the chips to form chipsets, and fixing functional surfaces of the chipsets to the carrier; forming a first plastic encapsulation layer on a side of the chipsets away from the carrier and removing the carrier; forming silicon interposer plates and bonding the silicon interposer plates to the chipsets; cutting the silicon interposer plates and the chipsets to form chip micro-modules each of which includes one chipset; fixing a side of the silicon interposer plates to the carrier and forming a second plastic encapsulation layer on a side of the chip micro-modules away from the carrier; and removing the carrier and cutting the second plastic encapsulation layer, to form independent packaging structures.

The invention discloses a chip module cutting method, and relates to the technical field of semiconductor manufacturing. The chip module cutting method comprises the steps that a wafer to be cut is cut, independent chip modules are obtained, the wafer to be cut comprises a plurality of chip modules, each chip module comprises an intermediary layer and crystal grains, and the crystal grains are arranged on the surface of the intermediary layer; and chamfering the chip module to obtain the chamfered chip module. By implementing the chip module cutting method provided by the embodiment of the invention, chamfering processing is performed on the four corners of the interposer of the chip module, stress concentration points are eliminated, the mechanical stress problem of the large-size expensive interposer is improved, and the product manufacturing yield is improved; furthermore, a silicon interposer with a larger size can be manufactured to carry a high-performance processor and more high-bandwidth memories, so that the computing power is further improved; and a secondary cutting process is adopted in the cutting process, so that damage to the silicon interposer caused by non-uniform stress at a medium junction can be avoided.

The invention relates to a wafer-level chip TSV packaging structure and a packaging method thereof, and belongs to the technical field of semiconductor manufacturing, the wafer-level chip TSV packaging structure comprises a CPU module, a silicon interposer and a substrate which are connected in sequence, the wafer-level chip TSV packaging structure further comprises first through silicon vias, a metal core and a first insulating layer, the first through silicon vias are formed in the silicon interposer, and buffer cavities are formed in openings of the first through silicon vias; the metal core is filled in the first silicon through hole, and the CPU module is electrically connected with the circuit etched on the substrate and the silicon interposer through the metal core; the first insulating layer is filled between the first silicon through hole and the metal core and does not comprise a section of the buffer cavity, and the first insulating layer has thermoplasticity; the technical problem of chip damage caused by thermal expansion of conductive metal filled in a TSV of a wafer-level chip in the prior art can be solved.

This invention relates to the field of semiconductor packaging technology, and in particular to a vertically wire-bonded in-memory computing fan-out package structure and its fabrication method. By introducing a hybrid vertical interconnect method combining vertical wire bonding and copper pillars into the fan-out package structure, this invention achieves high-density three-dimensional integration of computing chips and memory chips without using through-silicon vias (TSVs) or silicon interposers, effectively shortening the signal transmission path. This "memory below, computing above" three-dimensional stacking arrangement places the memory chip inside the package, close to the core area of ​​the redistribution layer and vertical interconnect structure. A large number of I / O signals from the memory chip can access the vertical interconnect network through a shorter path, thereby reducing interconnect parasitic parameters and improving signal integrity. Furthermore, this arrangement helps to keep the main heat sources away from the memory chip, improving the heat distribution inside the package and enhancing the reliability and process feasibility of the in-memory computing package structure.

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

This application provides a packaging process method for an NPO optical engine. The method includes: preparing a silicon interposer and pre-treating the silicon interposer; mounting an AWG chip to the silicon interposer and curing the mounted workpiece; mounting a VCSEL array to the silicon interposer and curing the mounted workpiece; aligning and coupling a silicon lens array to the silicon interposer and curing the coupled workpiece; aligning and assembling an FA fiber array to the silicon interposer and curing the assembled workpiece; and performing bonding and heat dissipation packaging on the assembled workpiece to obtain the NPO optical engine. This application integrates an AWG chip and a VCSEL array within the same NPO, thereby reducing hardware costs, minimizing PCB layout space requirements, and lowering the deployment complexity of the computing cluster.

An apparatus and a method for testing a multi-channel high-speed low-latency interconnect interface (HLII) for a silicon interposer are provided. The apparatus includes: a standard test port configured to exchange a test instruction; an asynchronous bypass port configured to directly access an input / output (I / O) port of a channel of a physical layer of the interconnection interface; a built-in self-test (BIST) engine configured to implement inter-level loopback testing and data verification; a redundant data channel configured to repair a damaged data channel; and a delay chain testing circuit configured to test a function and linearity of a delay chain. The apparatus embeds test and repair logic into the physical layer and a link layer, achieving internal test control without any external controller. In this way, a sample can be tested and quickly screened to ensure its performance.

This invention provides a modified substrate and a method for manufacturing the same. The modified substrate comprises a substrate, a polyimide layer disposed on at least one surface of the substrate, and a patterned conductive material, wherein the patterned conductive material is disposed on the polyimide layer. The polyimide layer enhances the adhesion of the conductive material to the substrate. This invention also provides a method for manufacturing the modified substrate, comprising heating the substrate at a temperature of about 150°C to about 350°C to cure a polyimide precursor into polyimide, thereby obtaining the modified substrate. This invention further provides an application of the modified substrate as a glass interposer, a silicon interposer, or an IC substrate.

The invention relates to a silicon substrate interposer metal wiring overhead calculation method and device. The method comprises the following steps: determining the number of first metal layers required for wiring of a power ground network according to the number of first convex points corresponding to the power ground network of a silicon interposer and the convex point bearing capacity value of a single metal layer; determining the number of second metal layers required by signal network wiring according to the size parameter of the chip to which the silicon interposer belongs and the wiring mode of the signal network of the silicon interposer; and according to the first metal layer number and the second metal layer number, obtaining the total metal layer number required by wiring of the silicon interposer. By adopting the method, the metal layer overhead of the silicon interposer wiring can be accurately calculated.

The invention relates to the field of chips, and discloses a cache system and method based on a silicon interposer structure, and the system comprises a silicon interposer, a computing bare chip, a plurality of HBM stacks, and a cache mapping scheduler embedded in the silicon interposer. The plurality of HBM stacks are distributed on the first surface and / or the second surface of the silicon interposer, and the computing bare chip is located on the first surface; all the HBM stacks in the plurality of HBM stacks are interconnected with the computing bare chip through a photon interconnection structure; or, a part of the HBM stacks in the plurality of HBM stacks are interconnected with the computing bare chip through the photon interconnection structure, and the other part of the HBM stacks are interconnected with the computing bare chip through the electric interconnection structure; the cache mapping scheduler determines the priority of the current cache data so as to map the cache data to a target HBM stack, and the access delay of the target HBM stack is matched with the priority of the current cache data; an interconnect path between the compute die and the target HBM stack is allocated. Signal congestion is reduced and access latency is reduced.

This invention belongs to the field of chip packaging technology, specifically an auxiliary device and method for semiconductor chip packaging, including a first rotary disk, a second rotary disk, at least three first loading stations and adsorption clamps installed in the first loading stations, at least three second loading stations and adsorption plates installed in the second loading stations; by the first and second rotary disks rotating synchronously in opposite directions, the independent material flows of the chip and the silicon interposer are deeply coupled in space and time. When the first and second rotary disks rotate 120° in opposite directions at a fixed rhythm, the chip and the silicon interposer are axially intersected at the same and unique bonding station. At the same time, other stations perform loading, pre-processing or unloading preparation in parallel, so that the loading, alignment, bonding and unloading processes form a continuous operation flow. When the bonding station is bonding, adjacent stations can perform loading or pre-processing simultaneously, eliminating the idle waiting between stations in traditional linear or single-disc equipment.

An electronic package is provided. The electronic package includes an encapsulating layer encapsulating a plurality of conductive pillars and an interposer board that has through-silicon vias. An electronic component is disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias. The conductive pillars act as an electric transmission path of a portion of electric functions of the electronic component. Therefore, the number of the through-silicon vias is reduced, and the fabrication time and chemical agent cost are reduced. Also, the through silicon interposer of a large area can be replaced by a smaller one, and the yield is increased. Further, a method of fabricating an electronic package is provided.

Voltage regulator devices on active silicon interposers and associated systems and methods are disclosed. Local High-Bandwidth Memory (HBM) device voltage regulation is provided via the active silicon interposer configured with one or more voltage regulators corresponding to one or more HBM devices of a system-in-package (SiP). Each of the voltage regulators are configured to receive a first voltage signal from an external power supply and to generate one or more voltage signals based on the first voltage signal. The one or more generated voltage signals are supplied to a given HBM device by a locally positioned voltage regulator. In some embodiments, the one or more generated voltage signals are further based on the voltage signal of a sense line coupling a given HBM device to a corresponding voltage regulator.

The invention relates to a chip packaging method and a chip packaging structure. The chip packaging method comprises the following steps: forming an initial silicon interposer; the initial silicon interposer comprises a dielectric layer and a plurality of conductive columns; one side of the dielectric layer is provided with a plurality of conductive column accommodating grooves which are arranged at intervals, and the conductive columns are correspondingly embedded in the conductive column accommodating grooves. At least one chip is connected to one side of the initial silicon interposer where the conductive pillars are embedded. And forming a chip packaging layer which coats the chip and covers the initial silicon interposer. And thinning the side, deviating from the chip in the vertical direction, of the initial silicon interposer until the surface of the side, deviating from the chip in the vertical direction, of the conductive column is exposed, and obtaining the silicon interposer. According to the invention, the chip packaging process flow is simplified and the process cost is saved.