85 results about "Silicon interposer" patented technology

The invention relates to the technical field of edge computing, and discloses an intelligent edge computing co-processing system based on an integrated circuit, which comprises a heterogeneous computing cluster module, a hardware computing unit set, a multi-core control processor based on RISC-V, a programmable pulse tensor computing array and a reconfigurable engine oriented to streaming processing, according to the intelligent edge computing cooperative processing system based on the integrated circuit, zero-delay data exchange is realized through silicon intermediate layer integration of the heterogeneous computing cluster module and a snakelike data channel, and traditional bus arbitration delay is eliminated through real-time operation code analysis and optimal optical communication path mapping of the hardware task routing matrix (TRF) module; the priority path distribution of the task scheduling subsystem is synchronously coordinated with the time-sensitive task, so that the collaborative efficiency of the computing unit is improved in multiple dimensions, the non-blocking transmission of the high-priority task is ensured, and the effect of enhancing the overall processing capability and response speed of the intelligent edge computing is achieved.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

The invention relates to the field of chips, and discloses an HBM packaging-based cache structure and electronic equipment, and the structure is characterized in that a first surface of a silicon interposer is provided with a calculation bare chip and a first HBM stack, the first HBM stack is located outside a coverage area of the calculation bare chip, a second surface of the silicon interposer is provided with a second HBM stack and a third HBM stack, a part of a storage area of the second HBM stack is located in the coverage area, and the third HBM stack is located in the coverage area; the third HBM stack is completely located in the coverage area; the priority sensing module in the computing bare chip determines the priority of cache data, the address mapping module selects a storage area for mapping the cache data from the first HBM stack, the second HBM stack and the third HBM stack according to the priority of the cache data, the routing module allocates interconnection paths, the first HBM stack and the second HBM stack are located in the storage area outside a coverage area, and the first HBM stack and the second HBM stack are located in the storage area outside the coverage area. The second HBM stack is located in a storage area in the coverage area, and the priorities of the stored cache data of the third HBM stack are sequentially increased. And the high-priority cache data delay is reduced.

This invention relates to the field of chip technology, and more particularly to a memory system based on the UBM protocol packaging, comprising a UBM device, a silicon interposer, and a GPU, wherein the GPU includes a UBM physical layer; the UBM device, silicon interposer, and UBM physical layer are interconnected based on a preset UBM physical interconnect protocol, where UBM is an ultra-high bandwidth memory, with a bandwidth higher than that of HBM4; the UBM physical interconnect protocol includes: the UBM device being connected to the silicon interposer using a hybrid bonding packaging method, the UBM physical layer being connected to the silicon interposer using a hybrid bonding packaging method, and the UBM device and the UBM physical layer establishing an interconnection through wiring resources in the silicon interposer. This invention improves the bandwidth line density and bandwidth areal density of the memory system packaging structure.

This invention provides an ultra-thin 2.5D packaging structure and method, which reduces the thickness of the package and shortens the process flow. An ultra-thin 2.5D packaging structure includes: a functional chipset comprising at least two sets of functional chips, each set of functional chips having a first dielectric material layer on its lower surface, and an exposed copper pad at the bottom of the first dielectric material layer; a silicon interposer board comprising a silicon interposer board body, a second dielectric material layer on top, and a third dielectric material layer on the bottom, the second dielectric material layer having an exposed mating copper pad on its surface, metal circuitry within the second dielectric material layer, a TSV copper pillar embedded in the silicon interposer board body, the upper part of the TSV copper pillar being connected to the corresponding metal circuitry, and the lower part of the TSV copper pillar being inserted into the third dielectric material layer; a plurality of bump structures; a substrate including an upper connecting pad and a lower connecting pad; a molding compound; and an adhesive filler layer.

A semiconductor die layer for a semiconductor package includes a first semiconductor die and a second semiconductor die adjacent the first semiconductor die. The first and second semiconductor dies are joined together by a filling material located between the dies. First and second RDLs are provided on first and second surfaces of the semiconductor die layer. Each RDL includes traces that enable the first semiconductor die to be directly coupled to the second semiconductor die, thereby eliminating the need for a silicon interposer. Vias are provided in the filling material and enable vertical communication between different semiconductor die layers that are included in the semiconductor package. Solder balls are provided on the second RDL and enable a semiconductor die layer to be directly coupled to a PCB or another semiconductor die layer.

The invention provides a packaging method of a chip embedded type silicon adapter plate, which is used for solving the problems of mismatch of thermal expansion coefficients and overlarge packaging warping in packaging in the prior art. A groove is formed in a silicon adapter plate through etching, the groove is used for embedding an element, and then the upper / lower surface of the silicon adapter plate is electrically connected with the embedded element through a vertical interconnection structure of a silicon through hole.

An optical package with increased mechanical stability of co-packaged optic components is described. The optical package includes an electronic mold compound (EMC) layer with copper pillars formed through the EMC layer. The optical package also includes a silicon interposer layer with through silicon vias (TSVs) and positioned on the EMC layer. A combined thickness of the EMC layer and the silicon interposer layer provide a combined mechanical coupling thickness for a connection component on a smooth diced edge side of the EMC layer and the silicon interposer layer. The optical package also includes devices attached to the silicon interposer layer.

The invention discloses a chip module cutting method, and relates to the technical field of semiconductor manufacturing. The chip module cutting method comprises the steps that a wafer to be cut is cut, independent chip modules are obtained, the wafer to be cut comprises a plurality of chip modules, each chip module comprises an intermediary layer and crystal grains, and the crystal grains are arranged on the surface of the intermediary layer; and chamfering the chip module to obtain the chamfered chip module. By implementing the chip module cutting method provided by the embodiment of the invention, chamfering processing is performed on the four corners of the interposer of the chip module, stress concentration points are eliminated, the mechanical stress problem of the large-size expensive interposer is improved, and the product manufacturing yield is improved; furthermore, a silicon interposer with a larger size can be manufactured to carry a high-performance processor and more high-bandwidth memories, so that the computing power is further improved; and a secondary cutting process is adopted in the cutting process, so that damage to the silicon interposer caused by non-uniform stress at a medium junction can be avoided.

This invention relates to the field of semiconductor packaging technology, and in particular to a vertically wire-bonded in-memory computing fan-out package structure and its fabrication method. By introducing a hybrid vertical interconnect method combining vertical wire bonding and copper pillars into the fan-out package structure, this invention achieves high-density three-dimensional integration of computing chips and memory chips without using through-silicon vias (TSVs) or silicon interposers, effectively shortening the signal transmission path. This "memory below, computing above" three-dimensional stacking arrangement places the memory chip inside the package, close to the core area of ​​the redistribution layer and vertical interconnect structure. A large number of I / O signals from the memory chip can access the vertical interconnect network through a shorter path, thereby reducing interconnect parasitic parameters and improving signal integrity. Furthermore, this arrangement helps to keep the main heat sources away from the memory chip, improving the heat distribution inside the package and enhancing the reliability and process feasibility of the in-memory computing package structure.

This application provides a packaging process method for an NPO optical engine. The method includes: preparing a silicon interposer and pre-treating the silicon interposer; mounting an AWG chip to the silicon interposer and curing the mounted workpiece; mounting a VCSEL array to the silicon interposer and curing the mounted workpiece; aligning and coupling a silicon lens array to the silicon interposer and curing the coupled workpiece; aligning and assembling an FA fiber array to the silicon interposer and curing the assembled workpiece; and performing bonding and heat dissipation packaging on the assembled workpiece to obtain the NPO optical engine. This application integrates an AWG chip and a VCSEL array within the same NPO, thereby reducing hardware costs, minimizing PCB layout space requirements, and lowering the deployment complexity of the computing cluster.

This invention provides a modified substrate and a method for manufacturing the same. The modified substrate comprises a substrate, a polyimide layer disposed on at least one surface of the substrate, and a patterned conductive material, wherein the patterned conductive material is disposed on the polyimide layer. The polyimide layer enhances the adhesion of the conductive material to the substrate. This invention also provides a method for manufacturing the modified substrate, comprising heating the substrate at a temperature of about 150°C to about 350°C to cure a polyimide precursor into polyimide, thereby obtaining the modified substrate. This invention further provides an application of the modified substrate as a glass interposer, a silicon interposer, or an IC substrate.

The invention relates to a silicon substrate interposer metal wiring overhead calculation method and device. The method comprises the following steps: determining the number of first metal layers required for wiring of a power ground network according to the number of first convex points corresponding to the power ground network of a silicon interposer and the convex point bearing capacity value of a single metal layer; determining the number of second metal layers required by signal network wiring according to the size parameter of the chip to which the silicon interposer belongs and the wiring mode of the signal network of the silicon interposer; and according to the first metal layer number and the second metal layer number, obtaining the total metal layer number required by wiring of the silicon interposer. By adopting the method, the metal layer overhead of the silicon interposer wiring can be accurately calculated.

The invention relates to the field of chips, and discloses a cache system and method based on a silicon interposer structure, and the system comprises a silicon interposer, a computing bare chip, a plurality of HBM stacks, and a cache mapping scheduler embedded in the silicon interposer. The plurality of HBM stacks are distributed on the first surface and / or the second surface of the silicon interposer, and the computing bare chip is located on the first surface; all the HBM stacks in the plurality of HBM stacks are interconnected with the computing bare chip through a photon interconnection structure; or, a part of the HBM stacks in the plurality of HBM stacks are interconnected with the computing bare chip through the photon interconnection structure, and the other part of the HBM stacks are interconnected with the computing bare chip through the electric interconnection structure; the cache mapping scheduler determines the priority of the current cache data so as to map the cache data to a target HBM stack, and the access delay of the target HBM stack is matched with the priority of the current cache data; an interconnect path between the compute die and the target HBM stack is allocated. Signal congestion is reduced and access latency is reduced.

This invention belongs to the field of chip packaging technology, specifically an auxiliary device and method for semiconductor chip packaging, including a first rotary disk, a second rotary disk, at least three first loading stations and adsorption clamps installed in the first loading stations, at least three second loading stations and adsorption plates installed in the second loading stations; by the first and second rotary disks rotating synchronously in opposite directions, the independent material flows of the chip and the silicon interposer are deeply coupled in space and time. When the first and second rotary disks rotate 120° in opposite directions at a fixed rhythm, the chip and the silicon interposer are axially intersected at the same and unique bonding station. At the same time, other stations perform loading, pre-processing or unloading preparation in parallel, so that the loading, alignment, bonding and unloading processes form a continuous operation flow. When the bonding station is bonding, adjacent stations can perform loading or pre-processing simultaneously, eliminating the idle waiting between stations in traditional linear or single-disc equipment.

Voltage regulator devices on active silicon interposers and associated systems and methods are disclosed. Local High-Bandwidth Memory (HBM) device voltage regulation is provided via the active silicon interposer configured with one or more voltage regulators corresponding to one or more HBM devices of a system-in-package (SiP). Each of the voltage regulators are configured to receive a first voltage signal from an external power supply and to generate one or more voltage signals based on the first voltage signal. The one or more generated voltage signals are supplied to a given HBM device by a locally positioned voltage regulator. In some embodiments, the one or more generated voltage signals are further based on the voltage signal of a sense line coupling a given HBM device to a corresponding voltage regulator.

The invention relates to a chip packaging method and a chip packaging structure. The chip packaging method comprises the following steps: forming an initial silicon interposer; the initial silicon interposer comprises a dielectric layer and a plurality of conductive columns; one side of the dielectric layer is provided with a plurality of conductive column accommodating grooves which are arranged at intervals, and the conductive columns are correspondingly embedded in the conductive column accommodating grooves. At least one chip is connected to one side of the initial silicon interposer where the conductive pillars are embedded. And forming a chip packaging layer which coats the chip and covers the initial silicon interposer. And thinning the side, deviating from the chip in the vertical direction, of the initial silicon interposer until the surface of the side, deviating from the chip in the vertical direction, of the conductive column is exposed, and obtaining the silicon interposer. According to the invention, the chip packaging process flow is simplified and the process cost is saved.

Barrier or cladding structures that prevent top vias from chemically reacting to tape residue or other impurities address reliability issues in local silicon interposer interconnection in semiconductor packaging by mitigating metal atom migration and wire growth, thereby enhancing long-term reliability. The via cladding structure incorporates a multi-layered barrier comprising, alone or in any combination, SiOCH, SiOx, SiON, SiNx, CuOx, Ta, Ti, TaN, TiN, Mo, MoN, TaC, TiC, TaCN, or TiCN, enhancing electrical performance and long-term reliability. The method of forming the cladding or barrier structure involves a combination of cladding layer deposition, patterning, wet etch, isotropic dry etch or anisotropic dry etch process, flowable dielectric deposition or spin-coat dielectric, and chemical mechanical planarization (CMP) to ensure robust and reliable connections. The integration of these layers mitigates issues related to metal atom migration and wire growth, providing a solution for the growing demand for high-density, high-performance semiconductor packages.

The invention discloses a deep silicon through hole preparation method, an integrated chip preparation method and an integrated chip, and relates to the technical field of semiconductor manufacturing. The deep through silicon via preparation method comprises the following steps: depositing silicon oxide on the upper surface of a silicon interposer of a wafer to form a silicon oxide film; coating photoresist on the upper surface of the silicon oxide film, and exposing and developing the photoresist through a preset through hole mask to expose a through hole area; etching the silicon oxide thin film and the silicon interposer in the through hole region in the etching process cavity through a dry etching process to form a deep silicon through hole; and removing the residual photoresist and silicon oxide film in the etching process cavity through a dry etching process. Through the technical means, the photoresist and the silicon oxide film are directly removed in the etching process cavity by adopting the dry etching process after the through hole is etched, and a wafer does not need to be transferred to other process tables, so that the preparation process flow of the deep through silicon via is simplified, and the preparation efficiency of the deep through silicon via is improved.

The invention discloses a chip module cutting method, and relates to the technical field of semiconductor manufacturing. The chip module cutting method comprises the following steps: chamfering an interposer unit arranged on an interposer wafer; bonding a conductive portion to the back surface of the chamfered interposer unit, and bonding a die to the surface of the chamfered interposer unit; and cutting the interposer wafer to obtain an independent chip module. By implementing the chip module cutting method provided by the embodiment of the invention, chamfering processing is performed on the four corners of the interposer of the chip module, stress concentration points are eliminated, the mechanical stress problem of the large-size expensive interposer is improved, and the product manufacturing yield is improved; furthermore, a silicon interposer with a larger size can be manufactured to carry a high-performance processor and more high-bandwidth memories, so that the computing power is further improved; a secondary cutting process is adopted in the process of cutting the interposer unit, so that the damage to the silicon interposer caused by non-uniform stress at a dielectric junction can be avoided.

Techniques for power delivery are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is connected mechanically to a unified control board (UCB). The UCB includes a plurality of DC-to-DC power converters. The plurality of MPSs is attached to a back side of the WSSI. The attaching is based on a plurality of compression connectors. The attaching is based on a compression force from the UCB. The attaching couples each MPS to one or more functional chips within the plurality of functional chips. DC power is sent, by the UCB, to the plurality of functional chips. The sending is based on the plurality of DC-to-DC power converters, the plurality of MPSs, and the plurality of TSVs.

The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

A package structure includes: a first redistribution layer; the second re-wiring layer and the first re-wiring layer are arranged in a stacked mode, and the second re-wiring layer and the second re-wiring layer are electrically connected; the first chip is electrically connected with the first rewiring layer; the second chip is electrically connected with the second rewiring layer; and the bridge chip is embedded in the first rewiring layer, the bridge chip is electrically connected with the first rewiring layer, and the bridge chip is electrically connected with I / O connection points of high-speed signals in the first chip and the second chip. A bridge chip is embedded in a first rewiring layer, and the bridge chip is used for connecting I / O connection points of high-speed signals in a first chip and a second chip. The bridge chip does not need to cover the whole chip area, and ultra-high density interconnection is only provided locally, so that the preparation cost of the whole large-size silicon interposer is reduced, the system manufacturing cost can be remarkably reduced, and meanwhile, the process complexity and the signal integrity risk caused by the through silicon vias are avoided.

This invention belongs to the field of integrated circuit layout and design technology, specifically relating to a multi-level interconnect planning method for signal-power-thermal integrity in 2.5D-3D integrated chips. It aims to solve the problems of low planning efficiency and design convergence difficulties caused by differences in design rules between silicon interposers and packaging substrates. This invention takes chip placement, chip pin layout, and available wiring resources as inputs. Based on a hierarchical variable scheduling strategy, it divides interconnect design variables into three subsets: interposer design variables, substrate design variables, and bridging variables. A three-stage Bayesian optimization algorithm is used to optimize sequentially: Stage 1 optimizes interposer and bridging variables, generates candidate designs and interconnect layouts, and updates the surrogate model until convergence; Stage 2 optimizes bridging and substrate variables, initializes with the optimal solution from Stage 1, and executes the same process; Stage 3 jointly optimizes all variables, executes the evaluation and update process until convergence; the algorithm finally outputs the optimal set of interconnect design variables.

An apparatus including a substrate having a first surface, and a silicon interposer including a first surface and a second surface, wherein the first surface is connected to the first surface of the substrate. The apparatus also includes at least one stack including an artificial intelligence (AI) chiplet and a plurality of static random-access memories (SRAMs) stacked below the AI chiplet, wherein the at least one stack includes a top surface, a bottom surface, a first side surface and a second side surface, and the at least one stack is orthogonally attached by the first side surface to the second surface of the silicon interposer. The apparatus additionally includes a heat spreader surrounding the top surface, the bottom surface and the second side surface of the at least one stack.

Voltage regulator devices on active silicon interposers and associated systems and methods are disclosed. Local High-Bandwidth Memory (HBM) device voltage regulation is provided via the active silicon interposer configured with one or more voltage regulators corresponding to one or more HBM devices of a system-in-package (SiP). Each of the voltage regulators are configured to receive a first voltage signal from an external power supply and to generate one or more voltage signals based on the first voltage signal. The one or more generated voltage signals are supplied to a given HBM device by a locally positioned voltage regulator. In some embodiments, the one or more generated voltage signals are further based on the voltage signal of a sense line coupling a given HBM device to a corresponding voltage regulator.

The application provides a high-frequency TSV silicon adapter plate and a design method thereof, wherein two ends of a ground wire through silicon via and a ground wire redundant through silicon via are electrically coupled with a ground pad respectively; two ends of a signal wire through silicon via and a signal wire redundant through silicon via are electrically coupled with a signal wire pad respectively; the ground wire through silicon via and the ground wire redundant through silicon via are first through silicon vias, the signal wire through silicon via and the signal wire redundant through silicon via are second through silicon vias, and a preset distance exists between the first through silicon vias and the second through silicon vias. In the application, the first through silicon vias and the second through silicon vias in the high-frequency TSV silicon adapter plate are quasi-coaxially distributed, the distance between the first through silicon vias and the second through silicon vias is adjusted to reduce the impedance discontinuity problem between the through silicon vias and transmission lines in the high-frequency TSV silicon adapter plate, and the radio frequency performance of the high-frequency TSV silicon adapter plate is improved. Meanwhile, the redundant through silicon via which is only used in the field of digital signal transmission to improve the fault tolerance rate is designed in the silicon adapter plate for the first time, the signal through silicon via and the multiple redundant through silicon vias share the pad, the radio frequency performance of the silicon adapter plate is optimized, and the process reliability is improved.

For transducer connection to an integrated circuit, a silicon or other wafer-based chip is processed to provide signal routing, such as altering the pitch using wafer process deposited conductors. This chip or silicon interposer may be more simply re-designed to relate the pitch of an array to the integrated circuit I / Os, avoiding redesign of the integrated circuit.

The invention provides a wafer structure cutting method and cutting system based on a silicon interposer. The silicon interposer wafer structure sequentially comprises a silicon substrate, a functional layer and a connecting substrate, the cutting method comprises the following steps: S1, adopting a V-shaped blade to carry out two times of V-shaped cutting with preset dislocation offset on a silicon substrate, and forming a splicing groove in the silicon substrate; s2, a laser ablation technology is adopted, the functional layer below the splicing groove is removed through the splicing groove, and the surface of the connecting substrate is exposed; and S3, cutting along the cutting path formed in the steps S1 and S2 by using a cutting blade, and cutting through the connecting substrate to realize separation of the wafer structure. According to the cutting method disclosed by the invention, through an innovative mechanical-laser-mechanical cutting synergistic process, cracks are effectively prevented from extending downwards from the brittle dielectric layer or collapsing from the surface of the silicon substrate, the integrity of a cutting interface is greatly improved, high-quality cutting of heterogeneous materials is realized, and the synergistic effect of mechanical cutting and laser processing is exerted.