Interconnection and package method on basis of TSV (through silicon via) chips

A packaging method and chip technology, applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc., can solve the problem of unguaranteed device reliability, and achieve the effect of improving device reliability and preventing low reliability.

Active Publication Date: 2013-09-11
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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  • Abstract
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However, this will expose the multilayer chip to the environment, resulti

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  • Interconnection and package method on basis of TSV (through silicon via) chips
  • Interconnection and package method on basis of TSV (through silicon via) chips
  • Interconnection and package method on basis of TSV (through silicon via) chips

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Embodiment Construction

[0047] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the specific embodiments discussed below are only specific embodiments in a specific environment, and do not limit the scope of the present invention.

[0048] A method for interconnecting and packaging based on TSV chips, comprising the following steps:

[0049] 1) Stack and bond multiple TSV chips with through holes to obtain stacked TSV chips;

[0050] 2) Interconnect the stacked multi-layer TSV chips with the interposer board with bumps to obtain the interposer board stack structure;

[0051] 3) Using flip-chip welding technology to interconnect the laminated structure of the adapter board with the substrate to obtain a laminated module;

[0052] 4) Carry out underfill protection between the chip and the chip, between the chip and the interposer, between the interposer and the substrate, and obtain an underfill prot...

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Abstract

The invention discloses an interconnection and package method on the basis of TSV (through silicon via) chips. By the aid of silicon interposers, interconnection of multi-layer laminated chips with narrow salient points and narrow spacing is changed into interconnection with large salient points and large spacing, and accordingly, subsequent installation process is achieved. By means of padding-bottom among the chips, between the chips and the interposers, and between the interposers and a substrate, multi-layer chip structure and the substrate structure are fixed onto the substrate. By means of package, seal protection of the TSV unpacked chips is realized and reliability of devices is improved.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, and relates to an interconnect packaging method based on TSV chips. Background technique [0002] Today's semiconductor industry generally believes that three-dimensional (3D) integration technology is one of the important technologies that can enable chips to continue to develop along the blueprint of Moore's Law. power consumption, and increase system memory bandwidth. Among them, 3D integration based on Through Silicon Via (TSV) technology is an important part. [0003] TSV technology is immature to the mass production stage, and the current development is mostly in the experimental processing stage, and it is difficult to control the process yield, resulting in high production costs. For the packaging of TSV chips, a bare chip packaging technology is generally used. However, this will expose the multi-layer chip to the environment, resulting in problems such as the reliability of th...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L21/56H01L21/768
CPCH01L2224/48091
Inventor 吴道伟刘永福冯一
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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