1860 results about "Die (integrated circuit)" patented technology

Embodiments of an integrated circuit (IC) package including a package substrate, a first microelectronic assembly including a plurality of first IC die, each first IC die having memory circuitry and a first surface, an opposing second surface, and a third surface orthogonal to the first and second surfaces; and a second IC die having a first surface and an opposite second surface, wherein the third surfaces of the first IC die are coupled to the second surface of the second IC die, and the first surface of the second IC die is coupled to the package substrate; a third IC die having a first surface and an opposing second surface, wherein the first surface third IC die is coupled to the package substrate; and a plurality of fourth IC die, each fourth IC die including compute circuitry and electrically coupled to the second surface of the third IC die.

A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

An apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. The first mating protrusion is to be partially disposed within a first recess formed in a second surface of a photonic integrated circuit (PIC) die when the first surface of the optical interposer opposes the second surface of the PIC die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die. A first portion of an outer surface of the first mating protrusion is to contact a first side wall of the first recess and a second portion of the outer surface of the first mating protrusion is to oppose a second side wall of the first recess such that a second space is to be defined therebetween.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (IC) dies; a second set comprising another one or more of the first IC dies; a plate between, and in direct contact with, the first set and the second set; and a second IC die coupled to the first set, the second set, and the plate. Each IC die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ILD), the substrate and the interconnect region share a planar interface, and the first IC dies and the second IC die are arranged with the planar interfaces of the first IC dies parallel to each other and orthogonal to the planar interface of the second IC die.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

Die or chip interconnect clock skew compensation can be performed for a multi -IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi - IC module that is receiving data and clock signals from a second die or chip of the multi -IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.

Interconnect structures for front-to-front stacked chips / dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.

Various embodiments of an integrated circuit (IC) die package are disclosed. An IC die package includes an IC die, an interposer structure electrically connected to the IC die, a first bonding structure, and a second bonding structure. The first bonding structure includes a first dielectric layer disposed on the IC die and also includes a first conductive pad having an embedded portion disposed in the first dielectric layer and an anchor portion extending over a top surface of the first dielectric layer. The second bonding structure includes a second dielectric layer disposed on the interposer structure, a second conductive pad disposed in the second dielectric layer, and an anchor layer surrounding the anchor portion.

The invention relates to an integrated circuit core particle time sequence optimization method and device, equipment and a medium. Analyzing the time sequence of the core particle according to the total negative time sequence margin of all paths generated by the OpenSTA tool on the establishment time, the total negative time sequence margin of all paths on the retention time, the negative time sequence margin of all paths under the worst establishment time and the negative time sequence margin of all paths under the worst retention time; when a violation occurs, the preliminary core particle division scheme is readjusted to determine an iterative division scheme until the time sequence of the core particles meets the requirement; and when the iteration division scheme meets the time sequence optimization requirement, recording and storing the current iteration division scheme, and continuing to perform regular division on the integrated circuit modules at the same level until all the preliminary core particle division schemes at the level are completely traversed. The design period can be greatly shortened, and automation and flexibility can be remarkably improved.

Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure having a first surface and a second surface opposite to the first surface, a high-power die over the substrate structure, a lower-power die over the high-power die, a first interposer between the first surface of the substrate structure and the high-power die, and a second interposer between the high-power die and the lower-power die. The substrate structure includes a thermal enhancement portion located under the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure. A substrate structure of the 3D integrated circuit package is also provided.

An integrated circuit (IC) device includes an IC die on a substrate, and the substrate includes a group of conductive lines between a high-permittivity dielectric layer and a low-permittivity dielectric layer, with a ground plane separated from the conductive lines by either the high- or low-permittivity dielectric layer. The substrate may include other low-permittivity dielectric layers. The substrate may include other groups of conductive lines between ground planes. The high-permittivity dielectric layer may be within a low-permittivity dielectric core layer.

A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

Multi-die bridge assemblies and methods for three-dimensional packaging. The architectures assemble a bridge component with two or more integrated circuit die to thereby create a multi-die (MD) bridge assembly. The means for attaching the bridge component to the dies can be hybrid bonding, solder bumps, thermal compression bonding, or a combination thereof. The created MD bridge assembly can be subjected to performance testing prior to attachment to a substrate. Attaching the MD bridge assembly to the substrate can include fitting the bridge component portion into a cavity in the substrate and attaching the bridge component to a cavity floor with another plurality of attachment options.

A method includes forming a first device die and a second device die. The first device die includes a first integrated circuit, and a first bond pad at a first surface of the first device die. The first integrated circuit is electrically connected to the first bond pad. The second device die includes a power switch that includes a first source / drain region, a second source / drain region, a second bond pad electrically connecting to the first source / drain region, and a third bond pad electrically connecting to the second source / drain region. The method further includes bonding the first device die with the second device die to form a package, with the first bond pad bonding to the third bond pad, and bonding the package to a package component.

Embodiments are directed to an integrated circuit with multiple dies connected in a die-to-die (D2D) configuration. The integrated circuit can include a first die and a second die connected to the first die via a D2D interface circuit in the D2D configuration forming a D2D structure with the first die. The D2D interface can connect a first plurality of superlanes of the first die with a second plurality of superlanes of the second die for streaming data between the first die and the second die along a first direction or a second direction orthogonal to the first direction.

Disclosed herein is an integrated circuit die stack and an integrated circuit die package assembly having the integrated circuit die stack. The integrated circuit die stack includes first plurality of integrated circuit dice disposed in a first tier of the die stack, and the first plurality of integrated circuit dice include a first integrated circuit die and a bridge die. The integrated circuit die stack further includes a second plurality of integrated circuit dice disposed in a second tier of the die stack, and the second plurality of integrated circuit dice are stacked vertically above the first plurality of the integrated circuit dice of the first tier and include a second integrated circuit die and a third integrated circuit die. The bridge die couples with both the second integrated circuit die and the third integrated circuit die.

A package structure is provided. The package structure includes a first package component, a second package component, and a lid structure. The first package component includes a plurality of integrated circuit dies and an underfill formed between the integrated circuit dies. The second package component includes a substrate, and the first package component is mounted on the substrate. The lid structure is disposed on the second package component and around the first package component, and the lid structure covers the integrated circuit dies and exposes the underfill.

Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.

Disclosed herein are integrated circuit (IC) packages with solder thermal interface materials (STIMs) with embedded particles, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, a die between the package substrate and the lid and a STIM between the die and the lid. The STIM may include embedded particles, and at least some of the embedded particles may have a diameter equal to a distance between the die and the lid.

Embodiments of the disclosure provide a semiconductor package including a first integrated circuit die having a first side and a second side opposite the first side, a first source / drain, a first interconnect structure disposed on the first side, a second interconnect structure disposed on the second side, and a first power rail extending between the first source / drain and the second interconnect structure. The package includes a second integrated circuit die disposed adjacent the first integrated circuit die, the second integrated circuit die having a first side and a second side, a second source / drain, a third interconnect structure disposed on the first side of the second integrated circuit die, a fourth interconnect structure disposed on the second side of the second integrated circuit die, and a second power rail extending between the second source / drain and the fourth interconnect structure, and an edge interconnect feature having a first end contacting the first interconnect structure and a second end contacting the third interconnect structure.

A structure adapted to optical coupled to an optical fiber includes a photoelectric integrated circuit die, an electric integrated circuit die, a waveguide die and an insulating encapsulant. The electric integrated circuit die is over and electrically connected to the photoelectric integrated circuit die. The waveguide die is over and optically coupled to the photoelectric integrated circuit die, wherein the waveguide die includes a plurality of semiconductor pillar portions extending from the optical fiber to the photoelectric integrated circuit die. The insulating encapsulant laterally encapsulates the electric integrated circuit die and the waveguide die.

Various embodiments of the present disclosure are directed towards an image sensor comprising a pixel with a dual-PD layout for enhanced scaling down. The pixel spans a first integrated circuit (IC) die and a second IC die stacked with the first IC die. The pixel comprises a plurality of photodetectors in the first IC die, and further comprises a plurality of pixel transistors split amongst the first IC die and the second IC die. The plurality of photodetectors are grouped into one or more pairs, each having the dual-PD layout. A DTI structure completely and individually surrounds the plurality of photodetectors, and further extends completely through a substrate within which the plurality of photodetectors are arranged. As such, the DTI structure completely separates the plurality of photodetectors from each other.

Apparatus and method for detachably connecting at least one optical fiber of a detachable photonic plug to a photonic integrated circuit (PIC). The detachable photonic plug comprises: a detachable plug die; an optically transparent spacer coupled to the detachable plug die; and at least one optical fiber held between the detachable plug die and the spacer. On the PIC side, apparatus includes a receptacle adapted to receive a detachable photonic plug adapted to couple at least one optical fiber to a photonic integrated circuit (PIC); and a photonic bump of the PIC, the photonic bump having a least one fine alignment feature. The method comprises permanently mounting a receptacle over at least a portion of the PIC; after completion of mounting, inserting the detachable photonic plug into the receptacle; and after the detachable photonic plug is inserted in the receptacle, securing the detachable photonic plug in the receptacle.

In one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (PIC) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. The package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the PIC die is located.

A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.