1091 results about "Die (integrated circuit)" patented technology

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

Various embodiments of the present disclosure are directed towards an image sensor comprising a pixel with a dual-PD layout for enhanced scaling down. The pixel spans a first integrated circuit (IC) die and a second IC die stacked with the first IC die. The pixel comprises a plurality of photodetectors in the first IC die, and further comprises a plurality of pixel transistors split amongst the first IC die and the second IC die. The plurality of photodetectors are grouped into one or more pairs, each having the dual-PD layout. A DTI structure completely and individually surrounds the plurality of photodetectors, and further extends completely through a substrate within which the plurality of photodetectors are arranged. As such, the DTI structure completely separates the plurality of photodetectors from each other.

A method for assembling a photonic computing system includes attaching a photonic source to a support structure, and attaching a photonic integrated circuit to the support structure. The photonic source includes a first laser die on a substrate configured to provide a first optical beam, and a second laser die on the substrate configured to provide a second optical beam. The photonic integrated circuit includes a first waveguide and a first coupler coupled to the first waveguide, and a second waveguide and a second coupler coupled to the second waveguide. The method includes attaching a plurality of beam-shaping optical elements to the support structure, the substrate, or the photonic integrated circuit, in which the attaching includes aligning a first beam-shaping optical element during attachment so that the first optical beam is coupled to the first coupler, and aligning a second beam-shaping optical element during attachment so that the second optical beam is coupled to the second coupler.

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

A system includes a substrate comprising a first circuit. The system also includes an integrated circuit formed in a first die disposed on the substrate. The integrated circuit includes at least a processor, a controller, and a first memory interface. The first memory interface is located in a first edge of the first die and is configured to couple to the first circuit. The system also includes a first buffer circuit formed in a second die disposed on the interposer substrate adjacent to the first edge of the first die. The first buffer circuit includes a second memory interface configured to couple to the first connection circuit. The system further includes multiple memory modules disposed on the second die. Each of the multiple memory modules at least partially share the second memory interface to communicate with the integrated circuit.

In a stacked integrated circuit device, there are two components, one in a first of the die and another in a second of the die. Each of the components is provided with two output connections, one leading above and one leading below the die, and two input connections, one leading above and one leading below the die, either of the two die. As a result of the redundancy, both die may be used in either position in the stacked structure. If either of the die is used as the top die, it sends data on its second output path and receives data on its second input path. On the other hand, when one of the die is used as the bottom die, it sends data on its first output path and receives data on its first input path. In this way, the same design may be used for the connections between each of the die.

A packaged integrated circuit (IC) (300) including a package substrate (110). The package substrate includes pins (321); a first metal layer (323) on the pins; a second metal layer (325) on the first metal layer; vias (322, 324, 326) on the second metal layer; an insulation material (308a, 308b) covering the pins, the first metal layer, the second metal layer, and the vias, and exposing surfaces of the pins and the vias. The packaged IC further includes a semiconductor die (101) on the package substrate, the semiconductor die having a surface (301) opposing the second metal layer; metal posts (305a, 305b) coupled between the semiconductor die and the exposed surfaces of the vias (326); and a mold compound (304, 304a) covering the semiconductor die and the metal posts, in which the surface is separated from the second metal layer (325) by the insulation material (308a) and the mold compound (304a).

Methods, systems, and methods of manufacture are described for integrating memory and compute die in a stacked configuration in an integrated circuit package without through silicon via. A packaging apparatus that includes a first semiconductor die comprising multiple memory cells and a second semiconductor die comprising compute logic representing a Processing-in-Memory (PiM) architecture. The PiM architecture is configured to process data stored at the memory cells. The first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data routed from a memory cell of the first semiconductor die.

An integrated circuit device that includes a substrate and a first die physically and electrically connected to the substrate. The integrated circuit device includes a manifold that includes a first surface, an inlet port configured as an entry for fluid into a chamber formed between the first die and the manifold, and an outlet port configured to provide an exit from the chamber for the fluid. The integrated circuit device also includes a sealant connecting the first die to the first surface of the manifold to form a seal between the first die and the manifold.

Embedded sensor structures and stretchable embedded sensor films including a plurality of embedded sensor packages are described. An embedded sensor structure may include a sensor package including an integrated circuit (IC) die and sensor die bonded to a front side of the IC die, with the sensor die including a diaphragm that is deflectable toward a cavity. A planarization layer laterally surrounds the sensor package, and metal routing is formed on a top side of the sensor die and spanning over the planarization layer. Other aspects are also described and claimed.

Gap-fill dielectrics for die structures and methods of forming the same are provided. In an embodiment, a device includes: an outer gap-fill dielectric having a first coefficient of thermal expansion; a first integrated circuit die in the outer gap-fill dielectric; a second integrated circuit die in the outer gap-fill dielectric; an inner gap-fill dielectric between the first integrated circuit die and the second integrated circuit die, the inner gap-fill dielectric having a second coefficient of thermal expansion, the second coefficient of thermal expansion being greater than the first coefficient of thermal expansion; and a third integrated circuit die over the inner gap-fill dielectric, the third integrated circuit die bonded to the first integrated circuit die and to the second integrated circuit die.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die, including a plurality of transistors, on the interposer. A carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact is positioned directly over one or more of the top metal structures with the bonding layer between them.

Stacked metal-oxide-metal (MoM) capacitor(s) in front side and back side metallization layers of a semiconductor die, and related fabrication methods. The stacked MoM capacitor includes a first, front side, MoM capacitor formed on the front side of the semiconductor layer of a die and in front side metallization layers in a front side interconnect structure. The stacked MoM capacitor also includes a second, back side MoM capacitor formed on the back side of the semiconductor layer in back side metallization layers in a back side interconnect structure. The front side and back side MoM capacitors are coupled to each other through a conducting structure in a second, vertical direction between the front side and back side interconnect structures to form the stacked MoM capacitor. In this manner, capacitance density in the die can be maintained or increase while providing sufficient area in the front side metallization layers for signal routing.

A photonic system includes an optical coupling interface for an optical fiber disposed on a first surface of a support material and a PIC die / chip disposed on a second surface of the support material that is opposite from the first surface of the support material. The PIC die / chip includes an oxide stack, where a portion of the oxide stack is configured as an optical reflector structure that includes a reflecting surface configured to direct a light beam conveyed from an optical waveguide within the PIC die / chip from a first direction of travel to a second direction of travel directed toward the second surface of the support material and toward the optical coupling interface for the optical fiber disposed on the first surface of the support material. The light beam travels through the optical reflector structure and through the support material to reach the optical coupling interface for the optical fiber.

One example includes a method for fabricating an integrated circuit (IC) device. The method includes fabricating a semiconductor die comprising a metal top (METTOP) structure and forming a barrier layer over the METTOP structure to cover approximately the entirety of the METTOP structure. The method also includes forming a polyimide (PI) layer over the semiconductor die and over a portion of the barrier layer to form a gap that exposes the barrier layer through the PI layer. The method further includes forming a conductive post in the gap over the barrier layer.

A first die includes a first substrate and a first interconnect structure. A second die is bonded to the first die and includes a second substrate and a second interconnect structure, such that the first and second interconnect structures are arranged between the first and second substrates. A redistribution layer (RDL) stack is arranged on an outer side of the first die opposite the first interconnect structure. A heat path includes a through substrate via (TSV) extending from a conductive layer in the first interconnect structure, through the first substrate, and into the RDL stack. An RDL dielectric material is included in the RDL stack and separates the heat path from an ambient environment. A thermal conductivity of the RDL dielectric is over twenty times a thermal conductivity of an interconnect dielectric material of the first interconnect structure or of the second interconnect structure.

A device package and heatsink assembly includes a device package containing one or more logic elements and one or more other integrated circuit devices mounted to a package substrate and one or more heatsinks. The other integrated circuit devices are higher above the package substrate's surface than the logic elements. Each heatsink contains chambers for a fluid heat transfer medium. A surface of the logic elements is thermally coupled to the fluid. A semiconductor chip package fabrication method includes bonding a diamond-containing dielet to a semiconductor logic die to form a logic die structure; mounting the logic die structure to a package substrate with the logic die sandwiched between the dielet and the substrate, exposing a surface of the dielet; and mounting one or more other integrated circuit devices to the package substrate. The other integrated circuit devices are higher above the package substrate's surface than the logic die structure.

A multi-die package includes both photonic and electronic integrated circuit (IC) dies interconnected to each other by a wiring structure constructed on a glass substrate. A glass preform including an optical waveguide may also be attached to the wiring structure. A plurality of electronic IC (EIC) dies may be arranged over the wiring structure along with a plurality of photonic ICs (PICs). Each PIC may be coupled to an optical waveguide within the glass preform. Conductive vias may extend through the glass substrate and further couple with the primary substrate. The primary substrate may include glass and an optical waveguide embedded within the glass. A vertical coupler may be attached to the primary substrate to optically couple the primary substrate to an optical waveguide within the glass preform of the multi-die package. Many of the multi-die packages may be arranged over a routing structure on a primary substrate.

A semiconductor die for an inductor-based switching power converter includes a semiconductor layer stack, a first enhancement mode, N-channel metal oxide semiconductor field effect transistor (first NMOS FET) formed in the semiconductor layer stack, a second enhancement mode, N-channel metal oxide semiconductor field effect transistor (second NMOS FET) formed in the semiconductor layer stack, first driver circuitry formed in the semiconductor layer stack, second driver circuitry formed in the semiconductor layer stack, and bootstrap capacitance. The first driver circuitry is configured to drive the first gate from a bootstrap power rail in response to a first control signal, and the second driver circuitry is configured to drive the second gate in response to a second control signal. The bootstrap capacitance includes one or more bootstrap trench capacitors formed in the semiconductor layer stack, and each bootstrap capacitor is electrically coupled between the bootstrap power rail and the switching node.

In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).

An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive connector and a die that has an active side and a non-active side. The active side of the die is connected to the electrically conductive connector via interconnects. A molding compound encapsulates the die and portions of the electrically conductive connector. A thermally conductive contact extends from a thermal hotspot on the die to an entry surface of the molding compound.

A three-dimensional integrated circuit device can include a group of die, a device layer and a thermal interface material formed above the substrate. A heat spreader can be located above the die, the device layer and the thermal interface material. The heat spreader can include a heat pipe comprising a rectangular-shaped heat pipe or disk-shaped heat pipe. A heat sink can be located above the heat spreader. The heat sink can include the heat pipe comprising the rectangular-shaped heat pipe or the disk-shaped heat pipe.

Systems, methods, and computer program products for identifying defective dies at a die processing service with machine learning are provided. A training dataset comprising training images taken by one or more cameras at a tape and reel machine is provided to train a machine learning system. The training images include images of dies having integrated circuits. Positions of solder points are determined in each training image. The positions of solder points in each training image are aligned with positions of solder points in other training images to generate aligned positions of the solder points. The aligned positions are clustered into multiple clusters. A centroid position for each cluster is determined, where the centroid positions correspond to locations of the solder points across all images. The centroid positions are transmitted to the machine learning system in a production environment and are used to identify images with defective dies.

The invention provides a storage and calculation integrated structure and a chip, and belongs to the technical field of integrated circuits, and the storage and calculation integrated structure comprises at least one near storage core grain which is used for providing large-capacity storage; the in-memory computing unit is used for providing computing processing, and the near-memory core grains provide cache space for data and / or instructions processed by the in-memory computing unit; the at least one logic processing core particle is used for loading the data and / or instructions stored in the near memory core particle into the in-memory computing unit, and updating and storing the data and / or instructions processed by the in-memory computing unit into the near memory core particle; and the logic processing core particle is integrated with the near memory core particle and the in-memory computing unit through hybrid bonding and / or TSV (Through Silicon Via). The storage and calculation integrated structure is applied to high-performance calculation, the high-performance calculation requirement and the large-capacity storage requirement can be met at the same time, the high-performance calculation of the system is maximized, and support is provided for the development of the calculation power technology from the hardware structure.

In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

An exemplary package structure includes a package substrate; an integrated circuit (IC) package comprises one or more dies and having a first side and a second side opposite the first side, wherein the first side of the IC package is attached to the package substrate; a heat-dissipating lid module attached to the second side of the IC package, wherein the heat-dissipating lid module comprises an upper portion, a lower portion, and a middle portion disposed between and thermally coupled to the upper portion and the lower portion, wherein the middle portion includes a heat sink separating the heat-dissipating lid module into a liquid cooling system and a vapor chamber.