670 results about "Die (integrated circuit)" patented technology

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

A photonic system includes an optical coupling interface for an optical fiber disposed on a first surface of a support material and a PIC die / chip disposed on a second surface of the support material that is opposite from the first surface of the support material. The PIC die / chip includes an oxide stack, where a portion of the oxide stack is configured as an optical reflector structure that includes a reflecting surface configured to direct a light beam conveyed from an optical waveguide within the PIC die / chip from a first direction of travel to a second direction of travel directed toward the second surface of the support material and toward the optical coupling interface for the optical fiber disposed on the first surface of the support material. The light beam travels through the optical reflector structure and through the support material to reach the optical coupling interface for the optical fiber.

One example includes a method for fabricating an integrated circuit (IC) device. The method includes fabricating a semiconductor die comprising a metal top (METTOP) structure and forming a barrier layer over the METTOP structure to cover approximately the entirety of the METTOP structure. The method also includes forming a polyimide (PI) layer over the semiconductor die and over a portion of the barrier layer to form a gap that exposes the barrier layer through the PI layer. The method further includes forming a conductive post in the gap over the barrier layer.

A device package and heatsink assembly includes a device package containing one or more logic elements and one or more other integrated circuit devices mounted to a package substrate and one or more heatsinks. The other integrated circuit devices are higher above the package substrate's surface than the logic elements. Each heatsink contains chambers for a fluid heat transfer medium. A surface of the logic elements is thermally coupled to the fluid. A semiconductor chip package fabrication method includes bonding a diamond-containing dielet to a semiconductor logic die to form a logic die structure; mounting the logic die structure to a package substrate with the logic die sandwiched between the dielet and the substrate, exposing a surface of the dielet; and mounting one or more other integrated circuit devices to the package substrate. The other integrated circuit devices are higher above the package substrate's surface than the logic die structure.

In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).

A three-dimensional integrated circuit device can include a group of die, a device layer and a thermal interface material formed above the substrate. A heat spreader can be located above the die, the device layer and the thermal interface material. The heat spreader can include a heat pipe comprising a rectangular-shaped heat pipe or disk-shaped heat pipe. A heat sink can be located above the heat spreader. The heat sink can include the heat pipe comprising the rectangular-shaped heat pipe or the disk-shaped heat pipe.

Systems, methods, and computer program products for identifying defective dies at a die processing service with machine learning are provided. A training dataset comprising training images taken by one or more cameras at a tape and reel machine is provided to train a machine learning system. The training images include images of dies having integrated circuits. Positions of solder points are determined in each training image. The positions of solder points in each training image are aligned with positions of solder points in other training images to generate aligned positions of the solder points. The aligned positions are clustered into multiple clusters. A centroid position for each cluster is determined, where the centroid positions correspond to locations of the solder points across all images. The centroid positions are transmitted to the machine learning system in a production environment and are used to identify images with defective dies.

The invention provides a storage and calculation integrated structure and a chip, and belongs to the technical field of integrated circuits, and the storage and calculation integrated structure comprises at least one near storage core grain which is used for providing large-capacity storage; the in-memory computing unit is used for providing computing processing, and the near-memory core grains provide cache space for data and / or instructions processed by the in-memory computing unit; the at least one logic processing core particle is used for loading the data and / or instructions stored in the near memory core particle into the in-memory computing unit, and updating and storing the data and / or instructions processed by the in-memory computing unit into the near memory core particle; and the logic processing core particle is integrated with the near memory core particle and the in-memory computing unit through hybrid bonding and / or TSV (Through Silicon Via). The storage and calculation integrated structure is applied to high-performance calculation, the high-performance calculation requirement and the large-capacity storage requirement can be met at the same time, the high-performance calculation of the system is maximized, and support is provided for the development of the calculation power technology from the hardware structure.

In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.

A photonic assembly includes: a composite die including a photonic integrated circuits (PIC) die and an electronic integrated circuits (EIC) die, the PIC die including waveguides and photonic devices therein, and the EIC die including semiconductor devices therein; an optical connector unit including a first connector-side mirror reflector and a first transition edge coupler and attached to a top surface of the composite die, wherein the first connector-side mirror reflector is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler; and a fiber array units assembly attached to a sidewall of the optical connector unit.

A hybrid integrated heat spreader suitable for an integrated circuit (IC) die package. The hybrid integrated heat spreader includes a top sheet material and a sealant interface material located where the heat spreader is to contact an assembly substrate. The sealant interface material may offer greater adhesion to a sealant employed between the interface material and the package substrate. In some examples, the sealant interface material has a greater surface roughness and / or a different composition than a surface of the integrated heat spreader that is in close thermal contact with an IC die through a thermal interface material. With the sealant interface material improving adhesion, the sealant may have a higher bulk modulus, enabling the integrated heat spreader to impart greater stiffness to the IC die package assembly.

An integrated circuit package may include a base die, a host device, a first bonding interface, a stacked memory structure, and a second bonding interface. The base die may include a first surface and a second surface. The host device may be disposed on the first surface of the base die. The first bonding interface may be located between the first surface of the base die and the host device. The stacked memory structure may be disposed on the first surface of the base die. The second bonding interface may be located between the first surface of the base die and the stacked memory structure.

An integrated circuit (IC) device includes a plurality of chiplets including a first device and a second device. A die-to-die (D2D) interconnect link connects between the first device and the second device. A link training and status state machine (LTSSM) of the IC device is configured to operate the degraded D2D interconnect link in a resilient link mode to provide a plurality of enabled lanes and a plurality of disabled lanes. The LTSSM detects a faulty lane among the plurality of enabled lanes, and replaces the faulty lane using a functional lane from the plurality of disabled lanes to maintain the degraded D2D interconnect link.

A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

In an embodiment, a package includes an encapsulant laterally surrounding a first integrated circuit device and a second integrated circuit device, wherein the first integrated circuit device includes a die and a heat dissipation structure over the die; a sealant disposed over the heat dissipation structure; an adhesive disposed over the second integrated circuit device; and a lid disposed over the sealant and the adhesive, wherein the lid includes a first cooling passage and a second cooling passage, the first cooling passage including an opening at a bottom of the lid and aligned to the heat dissipation structure, the second cooling passage including channels aligned to the second integrated circuit device and being distant from the bottom of the lid.

Photonics integrated circuit (PIC) dies bonded to photonics substrates, related apparatuses, systems, and methods of fabrication are disclosed. A photonics substrate and a PIC die include corresponding optical bonding regions one or both of which are surrounded by hydrophobic structures. A liquid droplet is applied to the PIC die or photonics substrate optical bonding region and the PIC die is placed on the optical bonding region of the photonics substrate. Capillary forces cause the PIC die to self-align to the optical bonding region, and an optical bond is formed by evaporating the liquid and subsequent anneal.

One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.

This invention discloses a method for manufacturing a flexible circuit board and a flexible circuit board, relating to the field of integrated circuit manufacturing technology. The method includes the following steps: providing a flexible copper-clad laminate (CCL) having a pre-processed area; drilling holes in the CCL to form positioning holes, the positioning holes partially overlapping with the pre-processed area and forming a semi-circular notch in the overlapping area; providing a punching die to punch the flexible CCL, the area covered by the projection of the punching die along the punching direction forming a first projection pattern, the first projection pattern partially overlapping with the pre-processed area and forming a pad half-hole in the overlapping area, the pad half-hole completely covering the semi-circular notch, and the sidewall of the pad half-hole forming a sidewall copper-plated area. By forming a larger sidewall copper-plated area formed by the sidewall of the pad half-hole, sufficient and stable solder volume can be provided for soldering, reducing the risk of cold solder joints and improving the yield of integrated circuit manufacturing, production of dedicated lithography machines, and etching machines.

A device package includes a first die comprising a semiconductor substrate; an isolation layer on the semiconductor substrate, wherein the isolation layer is a first dielectric material; a first dummy via penetrating through the isolation layer and into the semiconductor substrate; a bonding layer on the isolation layer, wherein the bonding layer is a second dielectric material that has a smaller thermal conductivity than the first dielectric material; a first dummy pad within the bonding layer and on the first dummy via; a dummy die directly bonded to the bonding layer; a second die directly bonded to the bonding layer and to the first dummy pad; and a metal gap-fill material between the dummy die and the second die.

Integrated circuit ("IC") structures and electronic packages that utilized an inorganic-convertible polymer to improve bond strength and thermal conductivity are described. In one embodiment, the inorganic-convertible polymer acts as a side fill material to seal a die periphery and improve direct bonding strength. In another embodiment, the inorganic-convertible polymer acts as a thermal bonding layer to increase the thermal conductivity between a die and a thermal solution.

Embodiments of the present disclosure relate to an integrated circuit chip package that does not utilize a leadframe. An integrated circuit die includes a semiconductor substrate, an interconnect layer including bond pads, and a passivation layer covering the interconnect layer and including openings at the bond pads. The passivation layer supports a conductive redistribution layer including conductive wires and conductive vias. An insulating layer covers the conductive redistribution layer and the passivation layer. Trenches formed in an upper surface of the insulating layer define pedestal regions in the insulating layer. Vias extend from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and contact a portion of the conductive redistribution layer. Metal pads are formed at the upper surface of each pedestal region in contact with the vias associated therewith. The metal pads are used for leads of a quad flat no-lead (QFN) type package.

Aspects disclosed an integrated circuit (IC) package having a mold layer between a die and a substrate comprising two types of resin to improve die interconnects having different sizes. The die interconnects include a first set of die interconnects and a second set of die interconnects. The first set of die interconnects are smaller and have a tighter pitch than the second set of die interconnects. A first resin is disposed around each of the first set of die interconnects. A second resin is disposed around each of the second set of die interconnects. These two types of resin enable a die to deploy die interconnects with different sizes which can increase the number of the first set of die interconnects and improve the power transfer over the second set of die interconnects.

The invention relates to a method of assembling a packaged integrated circuit device. The method comprises the following steps of: setting a supporting column of the assembling device to be at a height for applying a tube core bearing seat; applying solder over the semiconductor die positioned over the platform of the assembly apparatus while the support pillars are at a height for applying the die carrier; and positioning a die carrier over the solder and the semiconductor die.

A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include an integrated circuit die and a dielectric material on sidewalls of the integrated circuit die. The integrated circuit die may include a substrate, a protective structure in the substrate, an interconnect structure on the substrate, and a seal ring structure in the interconnect structure and in contact with the protective structure. The protective structure and the substrate may include a same semiconductor material, and the protective structure may include a first dopant and a second dopant different from the first dopant. The interconnect structure may include dielectric layers and conductive features in the dielectric layers. The seal ring structure may encircle the conductive features of the interconnect structure in a top-down view.

Various embodiments of the present disclosure are directed towards a semiconductor structure (e.g., an integrated circuit (IC) die) comprising an enhanced cap layer for pad oxidation prevention, as well as a method for forming the IC die. An interconnect pad overlies a substrate at a top of an interconnect structure, and a bond structure overlies and extends from a surface of the interconnect pad. A cap layer and an etch stop layer overlie the surface around the bond structure. Further, the cap layer separates the etch stop layer from the interconnect pad and is soft. Soft may for example, refer to a hardness less than silicon nitride and / or less than the etch stop layer. Because the cap layer is soft, a probe may be pushed through the cap layer to the interconnect pad for testing without first forming a pad opening exposing the interconnect pad.

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.

An apparatus and method for efficiently routing power signals across semiconductor dies. A semiconductor fabrication process (or process) places a first semiconductor die in an integrated circuit and stacks a second semiconductor die vertically adjacent to the first semiconductor die. The process forms multiple backside metal layers vertically adjacent to a backside of a silicon substrate of the second semiconductor die. The process forms a first backside metal layer that includes at least a first power route that forms a rectangle within the first backside metal layer. The process forms a second backside metal layer that includes at least a second power rail that forms an L-shape within the second backside metal layer. The process connects one or more corners of the rectangle of the first power rail to a corresponding corner of a separate power rail of the second backside metal layer that forms an L-shape.