216results about How to "Reduce area requirements" patented technology

Opto-electrical systems having electrical and optical interconnections formed in thin layers are disclosed. In one set of preferred embodiments, optical signals are conveyed between layers by respective vertical optical couplers disposed on the layers. In other preferred embodiments, optical signals are conveyed by stack optical waveguide coupling means. Yet other preferred embodiments have electrical via means formed in one or more layers to covey electrical signals between two or more layers.

In a semiconductor device, via holes are formed around a chip buried in a package, and conductor layers are respectively formed to be connected to one end and another end of the conductor filled in the individual via hole. Portions (pad portions) of the conductor layers which correspond to the conductors are exposed from protective films, or external connection terminals are bonded to the pad portions. The chip is mounted with flip-chip technology so that at least some of electrode terminals thereof are electrically connected to the conductor layers.

In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.

Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and, in combination with a sensor array, forms a digital focal plane array.

An apparatus and method for allowing two different signal paths to be coupled to a multi-tap transformer balun. The multi-tap transformer has a first port, which is coupled to a single antenna, and two or more differential secondary ports. Each port has one or more taps, which are optimized separately for each of the signal paths, allowing each of the two or more signal paths to operate in different frequency bands. Use of the method of the invention can decrease the number of external components and integrated circuit package pins, and reduce the area required for each signal path on an integrated circuit die, a printed circuit board, or the like.

A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

An inductor for a semiconductor device comprises a plurality of loops connected in series and formed along a lateral axis of the semiconductor device. Each loop comprises a bottom leg, a top leg, and a pair of side legs. The bottom legs are parallel and extend along a first plane. The top legs are also parallel and extend along a second plane. The second plane is parallel to and separate from the first plane. The first and second planes are parallel to said lateral axis, and the side legs are perpendicular to the first and second planes. The top and side legs can be formed from copper. A barrier layer between the top legs and a substrate layer adjacent the top legs and between the side legs and the bottom legs and the substrate layer can also be provided. The barrier can be formed from tantalum.

System and method for routing data packets in an Ethernet switch. A preferred embodiment comprises receiving a data frame at a first port, wherein the data frame comprises a header portion and payload portion. The header portion is analyzed to determine a destination port for the data frame. A destination status is added to the header portion to create a modified header portion. The modified header portion is stored in an on-chip memory. The payload portion is stored in an off-chip memory. An on-chip CPU instructs a DMA controller how to route the data frame.

Transaction identifier expansion circuitry is provided, along with a method of operating such circuitry. The transaction identifier expansion circuitry interfaces between a master device and interconnect circuitry used to couple the master device with a plurality of slave devices to enable transactions to be performed. Transaction analysis circuitry is responsive to each transaction in a sequence of transactions initiated by the master device, to compare at least one attribute of the transaction with predetermined attributes indicative of the target slave device for that transaction. Based on the comparison, an initial transaction identifier is then mapped to one of a plurality of revised transaction identifiers, such that the revised transaction identifier is dependent on the target slave device. Reordering circuitry is then arranged to buffer response transfers received from the interconnect circuitry destined for the master device, with each response transfer having the revised transaction identifier associated therewith. The reordering circuitry then re-orders the response transfers having regard to the original transaction order of those transactions within the sequence of transactions that had the same initial transaction identifier, prior to provision of each response transfer to the master device. By such an approach, the performance of a high performance master device can be maintained, by ensuring that for at least the transactions targeted to a particular subset of the slave devices, no intervention by deadlock avoidance circuitry within the interconnect is required when routing transactions to those slave devices, due to the use of different transaction identifiers when accessing those slave devices.

Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.

The invention provides a method for producing a thermoplastic composite material and a double steel-belt continuous press. The double steel-belt continuous press mainly comprises a set of paper and board feed system D, a set of preheating and prepressurizing system C which is arranged on driven rollers at an inlet of the press, a group of driving rollers, a group of driven rollers, and steel belts which are wound on the driving rollers and the driven rollers, wherein the inner part of the press is divided into a heating section A and a cooling section B. Raw materials (core boards and paper) of a product enter the preheating and prepressurizing system C through the paper and board feed system and are combined between the two driven rollers through heating and pressurization, enter the heating section for constant-temperature setting along with the traction of the steel belts, and are cooled and molded through the cooling section to produce finished sheets and strips. The defects of the conventional production machinery for composite boards are overcome; the press has a simple structure and reliable performance, and is relatively low in cost; the finished sheets and strips are pressed by a production process that the internal gluing is not required and the raw materials are combined after being molten; and products in corresponding sizes are processed according to requirements.

The invention discloses a silicon-based display adopting digital-analog hybrid drive. Pixels are driven to emit light through the method of combining the simulation amplitude modulation drive strategy and a digital pulse width modulation drive strategy, wherein the luminance of the pixels is determined by output current or voltage amplitude of the pixels in the subframe and the duty ratio of time of the output current or voltage of the pixels in the subframe, the frame of image is divided into a plurality of different digital subframes and simulation subframes, the digital drive strategy is adopted for the digital subframes, the time proportionable drive mode or luminance proportionable drive mode is adopted, the simulation drive strategy is adopted for the simulation subframes, many digital-analog converters with few digits are adopted, input data is converted into amplitude quantity of voltage or current, so that the pixels emit light, and the simulation subframes and the digital subframes are combined to generate the final display frame. The requirements of the simulation amplitude modulation drive strategy for the digital-analog converter and the requirements of the pixel circuit for the precision of analog quantity are reduced, and the conversion speed of the digital-analog converter and the contrast of the pixel luminance are improved.

A silicon dioxide layer is formed and a mask layer is deposited and then patterned to produce openings in the mask layer in the region around the gate contacts onto the gate electrode tracks in the logic region. The surface is uncovered around the gate contacts to the gate electrode tracks in the logic region, reducing the silicon dioxide layer. A sacrificial layer covering the gate electrode tracks is formed and patterned to form sacrificial layer blocks above the contact openings for the bit line contacts between the mutually adjacent gate electrode tracks in the cell array region and above the contact openings for the substrate contacts to the semiconductor surface and the gate contacts onto the gate electrode tracks in the logic region. A filling layer is formed between the sacrificial layer blocks, and the sacrificial layer blocks are removed. The contact opening regions are filled with conductive material.

A method and apparatus for performing syndrome computation in a decoder of a forward error correction (FEC) system. Syndrome computation logic of the decoder uses a partial parity-check matrix to recursively generate intermediate syndrome vectors based on a code word received by the decoder and to modulo-2 add the recursively generated intermediate syndrome vectors together until a final resolved syndrome vector has been generated. This recursive use of the partial parity-check matrix enables the syndrome computations to be performed very quickly so that the decoder is suitable for use in high data rate systems and provides a very large reduction in the amount of logic needed to perform the syndrome vector computations. The reduction in the syndrome computation logic results in reduced area requirements for the logic as well as reduced power requirements.

In the present invention, through the provision of a tray placing rack for storing trays in multi steps, the trays accommodating electronic parts after inspection are received in the racks and through the provision of a tray stacking rack above the tray placing rack, an empty tray emptied by having been inspected of the electronic parts before inspection at an inspection stage is stacked on the tray stacking rack. When a certain tray is filled with electronic parts after inspection and is discharged, an empty ray is taken out from the tray stacking rack and the empty tray is fed to the rack position of the discharged tray to permit re-use of empty trays

The invention relates to a memory cell for providing an information item, having a memory element, which has a PMC resistance component with a solid electrolyte material. The solid electrolyte material may be put into a first state with a high electrical resistance and into a second state with a low electrical resistance. The memory element has a resistance element which is connected up to the PMC resistance component in such a way as to reduce the total resistance of the memory element in the first state.

A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read / write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.

The invention relates to a semiconductor memory, particularly a DRAM, in which the memory cells in each case have a trench capacitor arranged in a lower area of a trench hole and a vertical selection transistor which is formed adjoining an upper area of the trench hole and which connects an inner electrode of the trench capacitor to a bit line, a conductive channel being capable of being formed in dependence on the potential of a word line in the channel area, the channel area completely enclosing the trench hole in its upper area, and the associated word line at least partially enclosing the channel area.

The present invention provides a multi-band antenna to which the arrangement of Koch fractal antenna is applied. The multi-band antenna is designed in triangular shape whose area is smaller than the general antenna structure. By using the arrangement of Koch fractal antenna, the area of the inverted-F dual-band antenna can be reduced efficiently, so as to enhance more usability.

Systems and methods for providing a fully differential amplifier performing common-mode voltage control having reduced area and power requirements are disclosed. The amplifier disclosed comprises an additional input stage at the amplifier input which senses the common mode voltage of the amplifier's inputs and applies internal feedback control to adjust the output common-mode voltage until the input common-mode voltage matches a target voltage and thereby indirectly set the output common-mode voltage. Furthermore the internal common-mode control can be implemented in such a manner as to provide a feed-forward transconductance function in addition to common-mode control if desired. Moreover it is possible to use feedback from other amplifier stages in an amplifier chain to implement common-mode feedback.

A display panel driving circuit includes N number of amplifiers configured to supply N number of output voltages to a display panel; N number of output switches configured to transmit output signals from the N number of amplifiers through N number of pads to the display panel; and a plurality of charge sharing switches configured to share charges among the N number of pads, wherein the charge sharing switches are formed in the pads.

A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified.