Semiconductor memories

Abstract

A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor memory, especially a dynamic random access memory (DRAM), and more particularly, the present invention relates to a series of cell structures, arrangements, and activation schemes for high density, low power semiconductor memories. [0003] 2. Description of the Background [0004] A conventional DRAM memory cell, consisting of one transistor and one capacitor (referred to as a 1T-1C configuration), is commonly used as a semiconductor memory when high bit density is required. This technology has several drawbacks and faces serious complications as device dimensions are scaled smaller. Most notably, since the DRAM cell has no internal gain, a high capacitance element (˜30 fF) must be fabricated in each cell to store a charge large enough to be adequately detected. Therefore, complex capacitor structures and expensive materials must be used to build a device with adequate c...

AI Technical Summary

Benefits of technology

The present invention provides a memory with a plurality of memory cells, each containing a gain cell structure. The method of writing information involves setting the storage node at a constant reference voltage and using the capacitance between the data line and the storage node to write information. The use of a thin-channel transistor as the charge transfer element to the storage node allows for a smaller area and a higher retention time. The memory cells can be fabricated in a 2-T or 4-T configuration with additional capacitive elements to increase retention time. The thin-channel transistor exhibits a static operation and a separate readout circuit is included in each cell to overcome slow read time. Overall, the present invention results in a high-density, low-power dynamic memory with improved performance.

Problems solved by technology

In addition, since a constant voltage is written to the storage node, an additional voltage boost circuit for the word line becomes unnecessary, thus reducing the area required by the memory array peripheral circuits.

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