Semiconductor memories

Abstract

A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor memory, especially a dynamic random access memory (DRAM), and more particularly, the present invention relates to a series of cell structures, arrangements, and activation schemes for high density, low power semiconductor memories. [0003] 2. Description of the Background [0004] A conventional DRAM memory cell, consisting of one transistor and one capacitor (referred to as a 1T-1C configuration), is commonly used as a semiconductor memory when high bit density is required. This technology has several drawbacks and faces serious complications as device dimensions are scaled smaller. Most notably, since the DRAM cell has no internal gain, a high capacitance element (˜30 fF) must be fabricated in each cell to store a charge large enough to be adequately detected. Therefore, complex capacitor structures and expensive materials must be used to build a device with adequate c...

AI Technical Summary

Benefits of technology

[0009] A semiconductor memory cell may achieve a smaller area by sharing the reference node between adjacent cells. In addition, since a constant voltage is written to the storage node, an additional voltage boost circuit for the word line becomes unnecessary, thus reducing the area required by the memory array peripheral circuits. This technique is used in several 2T and 3T memory cell structures presented according to the present invention.

[0011] According to the present invention, a memory is provided in which the memory cell combines the fixed voltage reference node writing method with the thin-channel charge transfer transistor to achieve a high-density, low-power dynamic memory. This memory cell may be fabricated in a 2-T configuration with a double-gate readout transistor and a 3-T cell in which separate storage and read transistors are included in each cell. In addition, a memory derived from the 2-T cell with series-connected memory cells arranged in subcolumns or parallel-connected memory cells arranged in subcolumns is also provided. The present invention results in a density approaching or surpassing that of conventional DRAM memories. Also, memory cells of this type, with an additional capacitive element to increase retention time, are also provided.

[0012] In at least one embodiment, a memory comprises a thin-channel transistor used in a memory cell in a four-transistor (4-T) configuration that exhibits a static operation. The memory cell preferably has two access transistors and two thin-channel transistors in a cross-coupling, self-restoring configuration. If the source-drain leakage current from the data line through the bulk transistor is higher than the leakage current from the storage node, a stable memory can be realized, obviating the need for a refresh operation. In addition, the thin-channel transistors may be fabricated in a much smaller area than bulk transistors, realizing a drastically reduced memory cell size. In a further embodiment, a separate two-transistor readout circuit is included in each cell to overcome the slow read time of the four-transistor cell. In this manner, a low power, high-speed memory cell is presented.

Problems solved by technology

In addition, since a constant voltage is written to the storage node, an additional voltage boost circuit for the word line becomes unnecessary, thus reducing the area required by the memory array peripheral circuits.

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