9 results about "Gain cell" patented technology

To provide a storage device having a gain cell type memory cell, and capable of storing a large amount of data per unit area.SOLUTION: A peripheral circuit of a storage device is configured using a transistor formed on a semiconductor substrate, and a memory cell of the storage device is configured using a thin film transistor. By providing a plurality of layers including the thin film transistors where the memory cells are configured in a lamination way over the semiconductor substrate, an amount of data that can be stored per unit area can be increased. In addition, by using an OS transistor with very small off-state current as the thin film transistor, a capacitance of a capacitor element that accumulates charges therein can be reduced. That is to say, an area of the memory cell can be reduced.SELECTED DRAWING: Figure 1

One aspect of the present disclosure pertains to a device. The device includes a first transistor and a second transistor coupled in series; a third transistor and a fourth transistor coupled in series; and a fifth transistor, a first terminal of the fifth transistor being coupled to each of a first terminal of the first transistor and a first terminal of the second transistor, and a control terminal of the fifth transistor being coupled to a second terminal of the second transistor at a storage node. A control terminal of the fourth transistor is coupled to the storage node, and at least one of the first to fifth transistors is located in a layer above another one of the first to fifth transistors.

A device includes a first gain cell. The first gain cell includes a first switch and a second switch. The switch is configured to transmit a first bit line signal to a first storage node. The second switch at least includes a first gate structure coupled to the first storage node and a first source / drain structure corresponding to a first terminal of the second switch. Along a first direction, the first gate structure is disposed above the first switch and the first source / drain structure is disposed above the first gate structure.

The present invention relates to a gain cell EDRAM with extended capacitance, providing a gain cell memory device including a semiconductor device layer including a silicon-on-insulator substrate of an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source / drain region adjacent to the storage transistor, the isolation structure extending through the active region to isolate a first portion of the active region from a second portion of the active region, and a capacitor coupled with the storage transistor. A bottom plate of the capacitor includes the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor includes the gate electrode of the storage transistor and a metal structure over the gate electrode.

A device includes a two transistor zero capacitor gain cell that is back end of line compatible and includes a write transistor and a read transistor that is electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel and the read transistor includes a polysilicon channel.

The invention provides a method for improving a feedback coefficient of a residual error amplifier in a double-capacitor sampling margin gain unit. A circuit comprises a sampling circuit module, a DAC module and a switched capacitor amplifier module. According to the circuit disclosed by the invention, a novel DAC control time sequence can be adopted under the condition of ensuring the same amplification times of residual error signals, so that the sampling capacitance of the DAC can be halved, the feedback coefficient of the RA can be increased, the noise suppression capability of the circuit can be improved, the design difficulty of the RA can be reduced, the power consumption of the circuit can be reduced, and the circuit performance can be improved.

A gain cell memory includes a write transistor located on a substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to a first source / drain region of the write transistor and to a gate electrode of the read transistor; and a peripheral circuit configured to electrically bias a source region of the read transistor at a normal source bias voltage while the gain cell memory device is not under a read operation, and at a current-boost source bias voltage that increases an on-current of the read transistor while the gain cell memory device is under the read operation.

A gain cell memory device includes a semiconductor device layer of a silicon on insulator (SOI) substrate comprising an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source / drain region adjacent to the storage transistor, the isolation structure extending through the active region such that a first portion of the active region is isolated from a second portion of the active region, and a capacitor coupled to the storage transistor. A bottom plate of the capacitor comprises the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor comprises the gate electrode of the storage transistor and a metal structure over the gate electrode.

This invention discloses a parasitic cancellation gain unit and a distributed amplifier, belonging to the field of amplifier technology. The parasitic cancellation gain unit is a parasitic cancellation common-source cascode gain unit, comprising two groups of small transistors and multiple parallel embedded capacitors. Each group of small transistors includes four small transistors connected in parallel, and the two groups of small transistors respectively replace a single large transistor in the common-source and common-gate stages. The multiple parallel embedded capacitors are embedded in the traces of the connection capacitors and decoupling capacitors of the common-source cascode gain unit to cancel the influence of parasitic inductance generated by the traces. A distributed amplifier is composed of multiple stages of the above-mentioned parasitic cancellation gain units and input / output transmission lines. This invention solves the problems of limited bandwidth, significant parasitic effects, and large size of distributed amplifiers under traditional bulk CMOS technology.