23 results about "Gain cell" patented technology

A 3T gain cell includes a write transistor, a storage transistor and a read transistor. The write transistor has a first diffusion connected to a write bit line (WBL), a gate connected to a write word line (WWL) and a second diffusion. The storage transistor has a gate connected to said second diffusion of said write transistor, a first diffusion connected to a read bit line (RBL), and a second diffusion. The read transistor has a gate connected to a read word line (RWL) a first diffusion connected to said second diffusion of said storage transistor, and a second diffusion connected to a reference voltage.

A gain cell for storing a data level includes a write element and a read element. The write element is connected to a write word line (WWL) and a bit line (BL), and is configured to write a logic level from the BL to a storage node of the gain cell when a write operation is triggered on the WWL. The write element includes at least one transistor. The read element is connected to a read word line (RWL) and the bit line (BL), and is configured to read a logic level from the storage node to the BL when a read operation is triggered on the RWL. The read element includes at least one transistor.

Various embodiments of the present application are directed to an integrated chip. The integrated chip includes first and second fin structures disposed on a base region of a substrate. A first source / drain region is disposed on the first fin structure. A second source / drain region is disposed on the second fin structure. A gate structure is disposed above the base region of the substrate and is laterally spaced between the first and second fin structures. A bottom surface of the gate structure is located below bottom surfaces of the first and second source / drain regions.

Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes a first fin structure and a second fin structure disposed on a base region of a substrate. A first source / drain region is disposed on the first fin structure. A second source / drain region is disposed on the second fin structure. A gate structure overlies the base region of the substrate and is spaced laterally between the first and second fin structures. A bottom surface of the gate structure is disposed below bottoms of the first and second source / drain regions.

To provide a storage device having a gain cell type memory cell, and capable of storing a large amount of data per unit area.SOLUTION: A peripheral circuit of a storage device is configured using a transistor formed on a semiconductor substrate, and a memory cell of the storage device is configured using a thin film transistor. By providing a plurality of layers including the thin film transistors where the memory cells are configured in a lamination way over the semiconductor substrate, an amount of data that can be stored per unit area can be increased. In addition, by using an OS transistor with very small off-state current as the thin film transistor, a capacitance of a capacitor element that accumulates charges therein can be reduced. That is to say, an area of the memory cell can be reduced.SELECTED DRAWING: Figure 1

One aspect of the present disclosure pertains to a device. The device includes a first transistor and a second transistor coupled in series; a third transistor and a fourth transistor coupled in series; and a fifth transistor, a first terminal of the fifth transistor being coupled to each of a first terminal of the first transistor and a first terminal of the second transistor, and a control terminal of the fifth transistor being coupled to a second terminal of the second transistor at a storage node. A control terminal of the fourth transistor is coupled to the storage node, and at least one of the first to fifth transistors is located in a layer above another one of the first to fifth transistors.

A device includes a first gain cell. The first gain cell includes a first switch and a second switch. The switch is configured to transmit a first bit line signal to a first storage node. The second switch at least includes a first gate structure coupled to the first storage node and a first source / drain structure corresponding to a first terminal of the second switch. Along a first direction, the first gate structure is disposed above the first switch and the first source / drain structure is disposed above the first gate structure.

An energy-efficient memory for cryogenic computing is provided. The energy-efficient memory includes a plurality of memory banks, where each of the memory banks includes a cryogenic semi-static, dual-port, boost-free gain cell (CSDB-GC) macro module, a universal address decoder, and a different address decoder. The CSDB-GC macro module includes a plurality of columns of local blocks, and each of the local blocks includes a plurality of CSDB-GC memory cells. A final measurement result of a 16 Kb CSDB-eDRAM shows that the 16 Kb CSDB-eDRAM achieves data retention time (DRT) of 16.67 seconds, which is 2.6 times longer than DRT of a state-of-the-art cryogenic eDRAM at a temperature of 4.2 K, and achieves lower refresh power (0.11 pW / Kb). In addition, the 16 Kb CSDB-eDRAM also achieves shorter access time, namely, 710 ps (1.41 GHz). Compared with the state-of-the-art work, the 16 Kb CSDB-eDRAM has a lowest dynamic power consumption overhead, namely, 49.23 uW / Kb.

The present invention relates to a gain cell EDRAM with extended capacitance, providing a gain cell memory device including a semiconductor device layer including a silicon-on-insulator substrate of an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source / drain region adjacent to the storage transistor, the isolation structure extending through the active region to isolate a first portion of the active region from a second portion of the active region, and a capacitor coupled with the storage transistor. A bottom plate of the capacitor includes the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor includes the gate electrode of the storage transistor and a metal structure over the gate electrode.

Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes a first fin structure and a second fin structure disposed on a base region of a substrate. A first source / drain region is disposed on the first fin structure. A second source / drain region is disposed on the second fin structure. A gate structure overlies the base region of the substrate and is spaced laterally between the first and second fin structures. A bottom surface of the gate structure is disposed below bottoms of the first and second source / drain regions.

Some embodiments relate to a memory cell comprising: a write transistor on a substrate comprising a first gate terminal, a first source / drain region, and a second source / drain region coupled to a storage node; a first read transistor on the substrate including a second gate terminal coupled to the storage node and a gate dielectric having a first capacitance; and a capacitor spaced apart from the first read transistor and the write transistor and also spaced apart from the substrate by the first read transistor and the write transistor, where the capacitor is coupled to the storage node and has a second capacitance greater than twice the first capacitance. The embodiment of the invention also relates to an integrated circuit and a method of forming a gain cell random access memory cell.

A device structure may be formed by bonding a processor die with at least one memory die using metal-to-metal bonding. The processor die comprises processing units for performing logical operations. The at least one memory die comprises at least two types of memory arrays selected from a static random access memory array, a gain cell random access memory array, and magnetoresistive random access memory array, and a resistive random access memory array. A bonded assembly of the processor die and the at least one memory die is formed. The bonded assembly can be bonded to an interposer using a first array of solder material portions that is bonded to on-die bump structures of the processor die and to a first subset of first bump structures of the interposer.

A gain cell memory device is provided, which includes a write transistor located on a substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to a first source / drain region of the write transistor and to a gate electrode of the read transistor; and a peripheral circuit configured to electrically bias a source region of the read transistor at a normal source bias voltage while the gain cell memory device is not under a read operation, and at a current-boost source bias voltage that increases an on-current of the read transistor while the gain cell memory device is under the read operation.

A gain cell memory device is provided that includes a write transistor on a substrate; a read transistor on the substrate; a capacitor having a first electrode electrically connected to the first source / drain region of the write transistor and the gate electrode of the read transistor, a node dielectric, and a second electrode; and a peripheral circuit configured to electrically bias the source region of the read transistor at a normal source bias voltage when the gain cell memory device is not in a read operation, and electrically biasing a source region of the read transistor with a current-enhanced source bias voltage that increases a turn-on current of the read transistor when the gain cell memory device is in a read operation. The embodiment of the invention also provides a method for operating the gain cell memory device.

The present invention belongs to the technical field of alkali metal lasers, and particularly relates to a temperature-controllable and high-pressure-resistant alkali metal gain generating device. The device includes a gain cell body, a laser window, and a heating device. A main gas channel is provided inside the gain cell body. Four laser windows are circumferentially arranged on the side wall of the gain cell body, and a plurality of air curtain grooves are respectively located above each laser window. The air curtain grooves are used to blow inert protective gas onto the inner surface of the laser window. The heating device is arranged inside the side wall of the gain cell body and is disposed around the main gas channel. Through the optimized design of the structures of the gain cell body and the laser window, the present invention not only provides the pressure and temperature conditions for the gain region to ensure the stable operation of the alkali metal laser, but also greatly guarantees the fluid uniformity, thereby ensuring the quality of the output laser beam.

A device includes a two transistor zero capacitor gain cell that is back end of line compatible and includes a write transistor and a read transistor that is electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel and the read transistor includes a polysilicon channel.

The invention provides a method for improving a feedback coefficient of a residual error amplifier in a double-capacitor sampling margin gain unit. A circuit comprises a sampling circuit module, a DAC module and a switched capacitor amplifier module. According to the circuit disclosed by the invention, a novel DAC control time sequence can be adopted under the condition of ensuring the same amplification times of residual error signals, so that the sampling capacitance of the DAC can be halved, the feedback coefficient of the RA can be increased, the noise suppression capability of the circuit can be improved, the design difficulty of the RA can be reduced, the power consumption of the circuit can be reduced, and the circuit performance can be improved.

Disclosed in the present invention is a cryogenic quasi-static embedded DRAM for high-energy-efficiency computing-in-memory. An cryogenic quasi-static embedded DRAM array is composed of four-transistor transmission gate gain cell (4T TGGC) memory cells; each 4TTGGC memory cell is composed of a PMOS transistor P1 and three NMOS transistors N1, N2 and N3. According to a cryogenic 4T TGGC topology provided by the present invention, the advantages of the cryogenic 4T TGGC topology in the aspects of reducing leakage and line transmission delay are fully used so as to achieve a quasi-static storage operation at a low temperature. In addition, the present invention uses a cryogenic write bitline (WBL) biasing technique and a dedicated readout circuit to optimize the power consumption of a read-write operation.

A structure may be formed by bonding a processor die with at least one memory die using metal-to-metal bonding. The processor die includes a processing unit to perform logical operations. The at least one memory die includes at least two types of memory arrays selected from a static random access memory array, a gain cell random access memory array, a magnetoresistive random access memory array, and a resistive random access memory array. A bonded assembly of the processor die and the at least one memory die is formed. The bond assembly may be bonded to an interposer using an array of first solder material portions that are bonded to on-die bump structures on the processor die and a first subset of first bump structures of the interposer.

A gain cell memory includes a write transistor located on a substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to a first source / drain region of the write transistor and to a gate electrode of the read transistor; and a peripheral circuit configured to electrically bias a source region of the read transistor at a normal source bias voltage while the gain cell memory device is not under a read operation, and at a current-boost source bias voltage that increases an on-current of the read transistor while the gain cell memory device is under the read operation.

A gain cell memory device includes a semiconductor device layer of a silicon on insulator (SOI) substrate comprising an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source / drain region adjacent to the storage transistor, the isolation structure extending through the active region such that a first portion of the active region is isolated from a second portion of the active region, and a capacitor coupled to the storage transistor. A bottom plate of the capacitor comprises the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor comprises the gate electrode of the storage transistor and a metal structure over the gate electrode.

A method is presented for employing a physically unclonable function (PUF) structure for chip authentication. The method includes connecting a plurality of gain cells to either a first multiplexer or a second multiplexer and receiving outputs from the first and second multiplexers by a current sense amplifier. The plurality of gain cells can be either two-transistor gain cell memories or three-transistor gain cell memories.

This invention discloses a parasitic cancellation gain unit and a distributed amplifier, belonging to the field of amplifier technology. The parasitic cancellation gain unit is a parasitic cancellation common-source cascode gain unit, comprising two groups of small transistors and multiple parallel embedded capacitors. Each group of small transistors includes four small transistors connected in parallel, and the two groups of small transistors respectively replace a single large transistor in the common-source and common-gate stages. The multiple parallel embedded capacitors are embedded in the traces of the connection capacitors and decoupling capacitors of the common-source cascode gain unit to cancel the influence of parasitic inductance generated by the traces. A distributed amplifier is composed of multiple stages of the above-mentioned parasitic cancellation gain units and input / output transmission lines. This invention solves the problems of limited bandwidth, significant parasitic effects, and large size of distributed amplifiers under traditional bulk CMOS technology.