Gain cell type non-volatile memory having charge accumulating region charges or discharged by channel current from a thin film channel path

Abstract

A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure. The conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor element and a semiconductor device. [0003] 2. Description of the Related Art [0004] MOSFETs (metal-oxide-semiconductor field effect transistors) are normally placed in an off-state to prevent currents from leaking by means of pn junctions. The primary causes of leak currents include subthreshold currents and reversed carrier recombination. Such currents are small but not negligible; they determine the data holding time of DRAMs (dynamic random access memories) and define their refresh cycles. Schemes proposed so far to minimize leak currents include the reduction of crystal defects with wafers subject to epitaxial growth, and complete depletion in the off-state by use of SOI (silicon on insulator) wafers. [0005] There has been proposed a memory element structure called gain cells capable of operating as DRAM cells with reduced stored charges. The proposed structure in...

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Benefits of technology

[0014] In carrying out the invention, there is also provided a semiconductor memory element wherein conductance between the source and drain of a read transistor is varied depending on the amount of stored electrical charges, the conductance variation being used to retain a piece of data, and wherein a channel of a transistor for electrically charging or discharging a charge accumulating region is made of a semiconductor 5 nm or less in thickness. This structure enables both high-speed data write performance and prolonged data retention. The thickness of transistor channels may be minimized as desired so long as film defects do not become apparent during fabrication processes.

Problems solved by technology

According to this principle, reduction of the size to 1 / K requires multiplying the substrate density by a factor of K. However, raising the substrate density narrows the depletion layer width and increases leaks from junctions.

At very advanced levels of micro-fabrication, uneven positions of impurities in channels can trigger the flow of leak currents.

The growing scale of memories, however, requires longer refresh cycles.

Hence the problem of having to devise for each new generation of DRAMs a novel scheme for building a three-dimensional capacitor structure or for enhancing the dielectric constant of capacitor insulating films.

This, it can be expected, will eventually result in another problem.

One disadvantage of this type of memory is that it takes time to write or read data because currents are made to flow through the insulating films.

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