4results about How to "Improve data retention" patented technology

The invention discloses a ferroelectric memory cell, which comprises an oxide layer arranged in the middle of a ferroelectric layer and at least one side surface of the ferroelectric layer, and the material of the oxide layer and the material of the ferroelectric layer comprise the same main body element. By inserting the oxide layer having the same main body element as the ferroelectric layer between the electrode and the ferroelectric layer and inside the ferroelectric layer, the proportion of an orthogonal phase and a tetragonal phase in the ferroelectric memory unit can be regulated and controlled, and then regulation and control of a coercive field of the ferroelectric memory unit are realized; and finally, the data retention capability and the durability of the ferroelectric storage unit under a low operation electric field are improved.

The invention discloses a transistor, a semiconductor device, a preparation method thereof and electronic equipment. The transistor comprises a source electrode, a channel region and a drain electrode which are sequentially arranged along a first direction, and a grid electrode which is arranged at the periphery of the channel region in an insulating manner; the source electrode comprises a first semiconductor layer and a second semiconductor layer, the same ends of the first semiconductor layer and the second semiconductor layer in the first direction are connected with the channel region, and the second semiconductor layer is located on the side, close to the grid electrode, of the first semiconductor layer in the direction perpendicular to the first direction. The doping concentration of the first semiconductor layer is smaller than that of the second semiconductor layer. The invention relates to the technical field of semiconductor devices, in particular to a transistor, a semiconductor device, a preparation method of the semiconductor device and electronic equipment, and aims to restrain accumulation of holes in a channel as a starting point, relieve formation of a parasitic bipolar transistor and prolong storage retention time.

The application relates to the technical field of semiconductor nonvolatile storage devices, in particular to a ferroelectric thin film and a ferroelectric field effect transistor. The ferroelectric thin film comprises a quantum well ferroelectric charge storage layer, a bottom electrode or semiconductor layer and a top electrode layer, wherein the bottom electrode or semiconductor layer, the quantum well ferroelectric charge storage layer and the top electrode layer are stacked in sequence from bottom to top; the quantum well ferroelectric charge storage layer is composed of hafnium silicon oxide and doped transition material. The ferroelectric thin film can improve the durability and data retention capability of the ferroelectric field effect transistor, and has a more stable layer structure in terms of resistance to doping concentration change, thickness change, temperature change and stress change.

This invention provides a method, electronic device, and storage medium for dynamically adjusting the operating voltage of flash memory, relating to the field of semiconductor testing. The method includes: adjusting the bit line voltage and control gate voltage of the flash memory chip to predetermined values; adjusting the control gate voltage level while keeping the bit line voltage level unchanged to program the array; adjusting the word line voltage and setting the read level; reading the array status, and if successful, recording the current voltage and level as the operating voltage; if unsuccessful, adjusting the bit line or control gate voltage level and cyclically programming and reading until successful or reaching the highest level. This application solves the problem of over-programming or under-programming caused by uniform target voltage adjustment by dynamically determining the optimal operating voltage on a chip-by-chip basis, covering the current increase after baking, and significantly improving wafer yield and chip reliability.