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411results about How to "Improve data retention" patented technology

Tool for synchronization of business information

Disclosed herein are systems, electronic tools and related methods for integrating the business rules, processes, and technology necessary to enable collaboration between personal office management applications, which are used by individuals on a daily basis to organize personal contacts, appointment calendars, and tasks, with sales force management applications, which are used to manage client and account contact information and coordinate the pursuit of business opportunities across an organization. Users of both applications can have their data electronically synchronized to share specifically designated information automatically within the applications. The information designated for synchronization can be of three types having different rules regarding their sharing among the applications, wherein the types include business contacts, sales force activities, and opportunity tasks. Users can thereby manage a large synchronized base of business contacts via both their personal office management application and a sales force management application, synchronize sales force activities from their personal office management application into the sales force management application, and assign client or account opportunity action items to other users in the organization via the sales force management application, and then have those action items automatically appear to the assigned user in that assigned user's personal office management application as a task.

Gain cell type non-volatile memory having charge accumulating region charged or discharged by channel current from a thin film channel path

A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most. The arrangement affords both high-speed data write performance and an extended data retention time. The invention provides a high-speed, power-saving semiconductor device of high integration particularly advantageous for producing a small-scale system of low-power dissipation.

Variable resistance element, its manufacturing method and semiconductor memory device comprising the same

InactiveUS20090097300A1Stable switching operationFavorable data retention characteristicCurrent responsive resistorsSolid-state devicesElectrical resistance and conductanceVoltage pulse
Provided is a variable resistance element capable of performing a stable resistance switching operation and having a favorable resistance value retention characteristics, comprising a variable resistor 2 sandwiched between a upper electrode 1 and lower electrode 3 and formed of titanium oxide or titanium oxynitride having a crystal grain diameter of 30 nm or less. When the variable resistance 2 is formed under the substrate temperature of 150° C. to 500° C., an anatase-type crystal having a crystal grain diameter of 30 nm or less is formed. Since the crystalline state of the variable resistor changes by applying a voltage pulse and the resistance value changes, no forming process is required. Moreover, it is possible to perform a stable resistance switching operation and obtain an excellent effect that the resistance fluctuation is small even if the switching is repeated, or the variable resistance element is stored for a long time under a high temperature.

Semiconductor memory

ActiveUS20070091703A1Easy switch controlPrevent circuit scaleDigital storageBit lineAudio power amplifier
A precharge voltage generating circuit outputs any of a plurality of kinds of precharge voltages in accordance with an ambient temperature. A precharge circuit supplies the precharge voltage to a bit line during the nonaccess of a dynamic memory cell. A sense amplifier amplifies a difference between the voltage of a data signal read from the dynamic memory cell onto the bit line and the supplied precharge voltage. The precharge voltage is altered in accordance with the ambient temperature, whereby the read margin of the sense amplifier can be changed, and the worst value of the data retaining time of the memory cell can be improved. As a result, the frequency of refreshing of the memory cell can be lowered, reducing power consumption and a standby current.

Semiconductor device

InactiveUS20120112191A1Increase in number of manufacturing step can be suppressedExtended maintenance periodSolid-state devicesRead-only memoriesElectrical conductorMemory circuits
A data retention period in a semiconductor device or a semiconductor memory device is lengthened. The semiconductor device or the semiconductor memory includes a memory circuit including a first transistor including a first semiconductor layer and a first gate and a second transistor including a second semiconductor layer, a second gate, and a third gate The first semiconductor layer is formed at the same time as a layer including the second gate.

Low Power Retention Random Access Memory with Error Correction on Wake-Up

Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.
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