46results about How to "Avoid programming" patented technology

A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a NOR-type Flash nonvolatile memory cells and with one or two select transistors forms a two and three transistor EEPROM cell. The nonvolatile memory cells use a large positive programming voltage (+18V) applied to the word lines or select gating lines for programming the memory cells and a large negative erasing voltage (−18V) applied to the word lines or select gating lines for erasing the memory cells. The NOR-type Flash nonvolatile memory array is used to store code of embedded processor programs or application programs for smart cards. The EEPROM array is preferably used to store byte alterable data and NAND-type Flash nonvolatile memory array is used to store personalized biometric data such as Iris, DNA, facial picture and finger prints.

The present invention relates to a method for operating a PMC memory cell for use in a CBRAM memory array, wherein the PMC memory cell includes a solid electrolyte which is adapted to selectively develop and diminish a conductive path depending on an applied electrical field. The PMC memory cell is programmed to change to a programmed state by applying a programming voltage, and the PMC memory cell is erased to change to an erased state by applying an erase voltage. A refresh voltage is applied to the PMC memory cell at a predetermined time to stabilize the programmed state of the PMC memory cell, wherein the refresh voltage is selected such as that, while applying the refresh voltage, a programming of the PMC memory cell in the erased state to a programmed state is prevented, and that, by applying the refresh voltage, a stabilizing of the programmed state of the PMC memory cell is performed.

Programming NAND strings in a 3D stacked storage device to a conductive state is disclosed. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided.

A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.

A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.

A graphical user interface, implemented in a standard system management environment, accepts selections of logical instruction steps that are external to the standard system management environment. The logical instruction steps may include process steps, specify chemical formulae, or identify other components of master recipes that control drug manufacture or dispensing, as examples. The external logical instruction steps are introduced into the standard system management environment and approved. The standard system management environment subsequently controls the drug manufacturing or dispensing processes according to the external logical instruction steps.

The invention relates to a real-time fixed wing aircraft simulation system and a simulation method. The real-time fixed wing aircraft simulation system comprises a lower computer, a host computer, a ground station unit, an instrument unit, a vision unit and a parameter interface unit, wherein the lower computer is used for operating an aircraft model in a real-time embedded system, the host computer is used for compiling an aircraft model application program into the real-time embedded operation system and sending the compiled real-time embedded operation system to the lower computer, PID control parameters of the aircraft model are modified in real time, an operation state of the aircraft model is monitored, and the parameter interface unit is used for sending designated aircraft model parameters to the lower computer to realize real-time simulation of a designated fixed wing aircraft. Through the system and the method, a flight scene is simulated in real time, versatility of the aircraft simulation system is improved, complex programming and debugging are avoided, and simulation cost is reduced.

A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select line. A second voltage for activating a programmed memory cell is applied to a word line to which the programmed memory cell is connected. A programming operation is performed by applying a program voltage to a selected word line and applying a pass voltage to the unselected word lines.

Provided is an information processing apparatus including: a broadcast signal processing portion to receive and reproduce a program of a channel chosen by a user; a storage portion to store preference information of the user and to store, as a user viewing history, information of channels viewed by the user; a user preference learning portion to learn the user preference information based on information about the reproduced program, and to record information of the channel of the reproduced program in a viewing history list; a feature information generating portion to select, as first channels, channels among the channels on the air based on the viewing history list, and to generate feature information of a program of the selected first channels; and a recommended program determining portion to determine a recommended program based on the feature information of the program of the channels and on the user preference information.

A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current. This invention can reduce variance of programming current by the bit-line decoder diverted pull-up current, so can obtain more exact programming current to get preferable productivity, and this mechanism can be used for upgrading bit-line.

The invention provides an organic electroluminescent device, an OLED substrate, and a display device, and belongs to the display technology field. The problems of the conventional organic electroluminescent devices such as low ink-jet printing experiment continuity during the preparation process thereof and requirements on complicated computer programs between different luminescent layers are solved. The organic electroluminescent device comprises a cathode, an anode, and a function layer disposed between the cathode and the anode. The function layer comprises a first luminescent layer and a second luminescent layer, which are sequentially arranged in a direction away from the anode. The first luminescent layer comprises a first blue light luminescent material, and after the cathode and the anode are electrified, the first luminescent layer and the second luminescent layer are used to form a composite product to emit light, the color of which is different from the color of the blue light.

An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses.

Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.