439 results about "Error correction coding" patented technology

A remote camera relay method and apparatus for remotely operating a self-contained, unattended digital camera over a communications link. Format conversion means are included for transparently relaying control signals and remote image data between a local host processor and the remotely located digital camera, independently of specific camera command and image protocols. It thereby functions as a universal remote image transmission adapter, operable as an attachment for use with self-contained digital cameras. A portable enclosure is provided for accommodating the remote relay communications and control electronics and for attaching a hand-held digital camera thereto. Further means are included for remotely actuating the pan and tilt orientation of the camera in accordance with field-of-view selection commands. Data rate conversion and error correction coding are included for providing reliable, low power image forwarding. The communications channel could be a dial-up telephone system, a network connection, modem, an infra-red link or a wireless RF link, for example. Additional control means are provided for remotely selecting the camera field of view for image capture, and includes the ability to access only those subsets of image scenes for which viewing permissions are authorized. A further mode of operation includes protocol training whereby host photographing commands are captured by the remote relay invention during on-line operation, then replayed at programmed times resulting in automatic scheduled remote image capture. Power management is provided for maximizing operating time when used in low power, portable, battery operation.

The invention discloses a polarization code and multi-bit even parity check code cascaded error correction coding method. The method comprises the steps: a transmitting end encoder utilizes a multi-bit even parity check code as an outer code, and utilizes a polarization code as an inner code; a receiving end decoder decodes by utilizing a modified successive cancellation list (SCL) decoding algorithm. On the aspect of error correction performance, comparing with the prior art utilizing middle-short code length non-cascaded polarization codes of the SCL decoding algorithm, the polarization code and multi-bit even parity check code cascaded error correction coding method has the advantages that frame error rate performance of a system can be remarkably improved, and a maximum likelihood bound (ML Bound), which cannot be broken through by the SCL decoding algorithm, can be remarkably broken through. On the aspect of engineering realization, according to the polarization code and multi-bit even parity check code cascaded error correction coding method, the outer code utilizes the multi-bit even parity check code, which is simple to code; the modified SCL decoding algorithm is utilized to decode, bit decision and even parity check are combined to be carried out in a decoding process, and compared with the original SCL decoding algorithm, the method provided by the invention does not increase the decoding complexity, and facilitates the engineering realization.

A flash memory device, and a method of operating the same, is disclosed. The array of the flash memory device is arranged in pages of memory cells, each page having memory cells associated into groups of memory cells within the page for purposes of fail bit detection in program verification. For example, these groups may correspond to sectors within the page. In a programming operation, the verify process determines whether each group of memory cells within the page has fewer than a selected ignore bit limit for the sector. If not, additional programming is required for the insufficiently programmed cells in the page. By applying a fail bit detection threshold for each of multiple groups within the page, the efficiency of error correction coding in the flash memory is improved. A similar verify and fail bit detection approach may be used in erase and soft programming operations.

Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that is subsequently used in decoding a second page.

Data is wirelessly transmitted from a base station, and/or wirelessly received at a plurality of subscriber stations that are at a plurality of distances from the base station using a Time Division Multiple Access (TDMA) frame by transmitting a same amount of data to each of the subscriber stations at a same power level during the TDMA frame while varying at least one other parameter as a function of the distance of the respective subscriber station from the base station. The at least one other parameter may be an amount of error correction coding, a sub-period duration in the TDMA frame, a number of modulation symbols from a set of modulation symbols and/or a number of sub-periods of the TDMA frame.

A method and system detects and corrects errors in data bits of data words stored in a system memory. Each data word includes a plurality of data bits and the method includes generating a horizontal error correcting code for each data word. Vertical error correcting codes are generated, with each vertical error correcting code being generated using a particular bit from all of the data words. Each vertical and horizontal error correcting code is stored in the system memory. Vertical scrubbing is performed using the vertical error correcting codes to detect and possibly correct errors in the data words and horizontal scrubbing is performed using the horizontal error correcting codes to detect and correct errors in the data words. The vertical scrubbing may be done automatically either through suitable hardware contained on memory modules in the system memory or by a memory controller.

An error correction decoding (ECC) processing scheme is disclosed that reduces computational complexity normally associated with multiuser detection (e.g., TurboMUD) solutions, without causing degradation in quality of service or decreasing the total throughput. Error correction decoding algorithms are applied only to portions of the estimates that were affected by the immediately previous MUD update process. Even though the MUD and/or ECC updating is targeted so as to reduce complexity of each iteration, all of the estimates are maintained and remain candidates for future updates. As such, there is no negative impact real-time or future performance. This targeting approach can be used in conjunction with many variations of MUD, including full-complexity or reduced complexity, and may include MUD with confidence ordering or voting, and other techniques for facilitating efficient and effective MUD processing.

A system for error correction coding and decoding information is disclosed. In one embodiment, the first and second encoders are each configured to encode the information, wherein the second encoder has a higher capability than the first encoder. First and second decoders are configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.

A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers. The internal bus is then driven with the data to be written to the first group of columns in the row, and latched into the first bank of sense amplifiers. To the extent that the data in the second group of columns does not change from the read to write operations, power consumption otherwise necessary for switching the internal bus is avoided.

A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

The invention includes following steps: first, carrying out compressed encoding process for video data to be transmitted so as to obtain multiple data blocks after encoding process; then, carrying out error correction coding process for the said multiple data blocks to obtain corresponding checking blocks; finally, carrying out interlacing process for the said data blocks and the checking blocks, as well as packing, packaging, and transmitting the interlaced data blocks and checking blocks. In the invention, since it is lower correlativity between data blocks packaged in same or successive interlaced data packets, thus even if packet loss occurs in the transmission, the possibility that the receiving end is unable to decode the received data is reduced greatly. The invention raises quality for transferring video data through IP network, wireless network etc, where packet loss exists.

The invention relates to the technical filed of the error correction and coding of communication and information systems and discloses a method for generating a quasi-cyclic low density parity check code. The method comprises the following steps: according to the requirements on code rate and code length of the low density parity check code to be designed and system requirements, determining a degree distribution sequence which is selected by adopting a density evolution method; setting the column weight of each column of a basic matrix according to the selected degree distribution sequence; setting the positions and values of non-zero elements in each column in the basic matrix according to the column weights of the basic matrix to obtain the basic matrix; and expanding the obtained basic matrix into a check matrix. At the same time, the invention also discloses a method for coding the quasi-cyclic low density parity check code and provides corresponding devices. The methods and the devices provided by the embodiment of the invention enable finally obtained code words to effectively reduce influences of cycle overlapping.

A cache includes a plurality of cache lines, where each cache line includes a detection type field, corresponding cache data field, a detection field, and a corresponding tag field. The detection type field indicates an error detection scheme from a plurality of error detection schemes currently in use for the corresponding cache data field. One example of an error detection scheme is a multiple bit error detection scheme (e.g. an error detection coding (EDC) or an error correction coding (ECC)). Another type is a single bit error detection scheme (e.g. parity error detection). The detection bits field stores parity bits if parity error detection is used. The detection bits field stores checking bits if EDC coding is used.

A communication system supports multiple modulation/coding schemes. When connection quality drops below an acceptable threshold, ARQ techniques use an alternative modulation/coding scheme which is more resistant to noise and/or interference. Flexible resegmentation and mapping of information blocks is supported.

The invention relates to a highly efficient information dotting image and its generation and decoding method. It comprises the horizontal rotary aiming, search, synchronic and data areas. It comprises the classification of the original information data, safely processing the information, wrong code correction, pin dot matrix generation and information pin dot image generation. The information pin dot image decoding comprises the abstraction of the information pin dot image information matrix, information matrix correction method and the decoding output. The information pin dot matrix figure uses the innovative center search method being able to quickly and precisely defining the location, angle, and dimension information of the pin dot matrix image. Besides, it can get the dimension right and no deformation information pin dot image.

The invention provides a decoding method, a decoding device, and a communication system. Through a mixed mode of soft-decision error correcting coding and hard-decision error correcting coding, multi-grade coding is realized, and through a mixed mode of soft-decesion error correcting decoding and hard-decesion error correcting deconding, multi-grade decoding is realized, the advantages of the two modes are integrated: the system complexity and resource cost are reduced by replacing a multi-grade soft-decision error correcting coding and decoding mode with a primary soft-decesion error correcting coding and decoding mode; other grade hard-decision error correcting coding and decoding are carried out on the basis of the primary soft-decision error correcting coding and decoding, thus the gain performance is guaranteed, and the requirement on gain for a high-speed light transmission system is fulfilled.

Transmission digital data is converted to N parallel data sequences by an S/P converting section (103) via an error correction coding section (101) and a digital modulating section (102). A subcarrier selecting section (104) selects M parallel data sequences thereamong. The selected data sequences are converted to an OFDM signal via an IFFT section (105-1) and a P/S converting section (106-1) and a peak is detected by a peak detecting section (107). A signal output to an IFFT section (105-2) is also processed in the similar way to detect a peak. A signal selecting section (108) selects one of OFDM signals based on information reported from the peak detecting section (107) and outputs it. The signal is transmitted via a RF transmitting section (109) and an antenna (110). This enables to control a peak power of a multicarrier signal and suppress deterioration in an error rate at a receiving time and interference with a signal of another system.

A system for transmitting data over a physical resource including a layer configured to manage the physical resource and to guarantee a quality of service, and a first sub-layer configured to supply a transmission support in accordance with the quality of service and to segment the data into transmission units. The first sub-layer reduces a size of at least one of the transmission units when transmission conditions on the physical resource are degraded. A second sub-layer is configured to transmit at least one of the transmission units over the physical resource during each of transmission time intervals. The transmission time interval is a periodic time interval during which the second sub-layer is allowed to access the physical resource. A physical layer is configured to perform error correction coding or decoding of the data.

Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.