23 results about "Parity check code" patented technology

An integrated circuit includes data terminals 0 to 11; an ECC encoder circuit configured to operate an H matrix on transmission data to be transmitted to the data terminals 0 to 11 to generate a transmission parity code, the transmission parity code corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity code received through the data terminals 0 to 11 to detect and correct an error in the reception data. A data portion of the H matrix is divided into 24 groups, each of the 24 groups includes a group matrix portion and a non-group matrix portion, the group matrix portion is used by k group matrices that circulate in the 24 groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups is shifted.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

The objective is to obtain a method for decoding a multi-variable low-density parity check code that can reduce the amount of memory in the memory device constituting the decoding circuit for the multi-variable low-density parity check code, and also reduce the amount of computation required. [Solution] The decoding method for a multi-variable low-density parity check code involves performing row operations and column operations on the result of binary expansion of the Galois field elements that constitute the check matrix in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field.

The application relates to the fields of integrated circuits and chip design, and provides a customized logic circuit and design method for peripheral interfaces, which comprises a clock generation module for generating clock signals required by different peripheral interface IPs according to a main clock signal; a synchronous reset module for generating reset signals required by different peripheral interface IPs according to a main reset signal; a self-defined register read-write module for connecting detection signals of the peripheral interface IPs to a state register, reading the state register through a bus, connecting control signals of the peripheral interface IPs to a to-be-configured register, and performing a configuration operation on the register inside the peripheral interface IP through the bus; and a parity check module for generating parity check codes on data links at outputs and inputs of the peripheral interface, and comparing the parity check codes. The application can save a chip design period and accelerate the integration time of a high-speed peripheral interface IP of an SoC chip.

The embodiment of the invention provides a construction method of a check matrix, a storage medium, a computer program product and a related device, and the construction method of the check matrix comprises the steps: generating a basis matrix, and enabling the offset differences of adjacent blocks located in the same row in the basis matrix to be equal; through a progressive edge growth algorithm, according to the sequence of the corresponding priorities from high to low, determining effective check nodes from the plurality of check nodes according to the ring length, the approximate ring external information degree, the external information degree, the ring number and the row weight corresponding to the check nodes in sequence; blocks with the same row number and the same column number corresponding to the effective check nodes in the basis matrix are determined as effective blocks; and setting the blocks except the valid blocks in the basis matrix as invalid blocks to obtain a check matrix for checking the low-density parity check code. According to the scheme, the hardware structure for decoding the low-density parity check code based on the check matrix can be simplified, and the cost of hardware shift in the decoding process of the low-density parity check code is reduced.

Methods, systems, and techniques for detecting errors in qubits within a quantum computing system. In at least one embodiment, at least one quantum check operator is used to couple data qubits with syndrome qubits, a parity-check code is used to couple the syndrome qubits with measure qubits, and the measure qubits are measured to determine whether any errors are present in the data qubits. In at least one embodiment, codewords are coupled to one or more ancilla qubits based at least in part on a binary matrix associated with one or more non-Calderbank-Shor-Steane (“non-CSS”) quantum codes, and the one or more ancilla qubits are used to obtain information about any errors present in the codewords.

The application relates to the field of wireless communication chip data flow scheduling, and discloses a campus teaching service system and method applying 5G messages, which comprises a baseband buffer state monitoring module, a low-density parity check code decoding module, a physical layer resource mapping module and a baseband resource arbitration scheduling module. According to the number of unconfirmed transport blocks and the reserved bandwidth indicator, the system adjusts and reduces the modulation and coding strategy order of multimedia data flow through the baseband resource arbitration scheduling module, and synchronously adjusts the maximum iteration number of the low-density parity check code decoding module. When the core temperature change rate is greater than or equal to 0.5 DEG C / s, the temperature sampling compensation module is used to calculate the phase adjustment step, rewrite the time sequence generator register to finely adjust the starting time boundary of the air interface time slot, correct the clock phase temperature drift under high load, feed forward to eliminate the sudden load, avoid the risk of buffer queue overflow, in-situ repair the control time sequence retreat caused by heat dissipation, and guarantee the deterministic transmission of the baseband chip.

One or more systems, devices, computer program products and / or computer-implemented methods of use provided herein relate to decoding quantum low-density parity check (qLDPC) codes. For example, a system can comprise a memory that can store computer executable components and a processor that can execute the computer executable components stored in the memory. The computer executable components can comprise an error correction component that corrects, via a decoder, qubit errors for qLDPC code, wherein correcting qubit errors for the qLDPC code via the decoder can comprise: obtaining a set of local defect networks in a syndrome by matching defects on symmetries of the qLDPC code, wherein the symmetries comprise a subset of checks of the qLDPC code such that each qubit error creates an even number of defects; and locally correcting one or more of the set of local defect networks.

Aspects of the disclosure provide a memory system. For example, the memory system can include a memory device configured to store data and one or more parity check codes. The memory system can further include a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule. The memory system can further include a codec coupled to the memory device and the randomizer. The codec can be configured to generate the one or more parity check codes according to the pseudo-randomized numbers and the data. The parity check codes are to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect.

The invention relates to continuous variable quantum key distribution, in particular to a continuous variable quantum key distribution post-processing system based on an FPGA (field programmable gate array), which comprises the following steps: a receiving end Bob quantifies a continuous Gaussian variable Y into five-level bit tags L1-L5, calls a low-density parity check code encoder to encode L4 and L5, respectively generates syndromes S4 and S5, and sends the L1-L3, the S4 and the S5 to a sending end Alice; the sending end Alice calls a low-density parity check code decoder to decode and recover the S4 and the S5 to obtain bit tags L '4 and L' 5 through a multi-stage decoding process based on a related variable X held by the sending end Alice and the received L1-L3, S4 and S5, the sending end Alice shares a consistent correction key with the receiving end Bob, and the sending end Alice and the receiving end Bob generate a final security key through privacy amplification by using the correction key; according to the invention, the defects of extremely low throughput, low efficiency and high integration complexity can be effectively overcome.

Provided are an operation method of a device in a wireless communication system, and a device using same. The method comprises: generating a plurality of transport blocks; segmenting each of the plurality of transport blocks to generate at least one code block for each transport block; generating parity code blocks by encoding code blocks included in two or more transport blocks among the plurality of transport blocks; and transmitting the plurality of transport blocks and the parity code blocks to a receiver. Here, the encoding is performed by an outer code encoder that receives a plurality of source blocks and outputs a plurality of parity blocks, and information indicating to which source block, among the plurality of source blocks, each of the code blocks is mapped is provided to the receiver.

A fault detection circuit checks configuration registers, performs a configuration register test on a set of registers, reads settings of the configuration registers, and compares the read settings with expected settings. The fault detection circuit includes parity calculator units configured to receive a subset of bits stored in the configuration register. A parity code of said subset of bits is calculated. Capture units receive parity codes output from parity calculator units as captured parity codes. A controller then, for each parity calculation unit and capture unit: issues a parity calculation control signal enabling the calculation of the parity code; issues a capture control signal to enable holding of the parity code value as captured parity code; receives and compares the captured parity code with a previous captured parity code; and signals a fault if the comparison indicates a change in the value of the captured parity code.

The application provides a high-dimensional lossy source decoding method and device for automatic driving, in which n-dimensional source data from a vehicle-mounted sensor is input into a lossy source encoder network to obtain a k-dimensional quaternary sequence; based on a check matrix of a pre-stored original pattern low-density parity check code, algebraic reconstruction is performed on the k-dimensional quaternary sequence on an integer ring to generate an n-dimensional code word satisfying a check constraint; the n-dimensional code word is centrally encoded to map discrete quaternary symbols therein into a continuous numerical sequence centered on zero; and the continuous numerical sequence is input into a pre-trained deep decoder network to obtain a reconstructed Gaussian floating point sequence for environmental perception of automatic driving. Therefore, the scheme provided in the embodiments of the application effectively improves the decoding efficiency and data reconstruction quality in an automatic driving system.

Some examples of the techniques described herein may provide schemes to organize shaped payload bits, non-shaped payload bits, and parity bits to allow an increased quantity of bits to be shaped for enhanced performance. Interleaving may be utilized in some aspects to enhance robustness to burst errors. For instance, interleaving schemes for enhancing bit orderings and interleaving are provided. In some approaches, permutation and row-column interleaving may be performed with a quantity of rows. Some approaches may utilize circular rotation and row-column interleaving with a quantity of rows. In some examples, permutation with alphabet-based row-column interleaving with fixed rows may be performed. Some aspects may include permutation and row-column interleaving with a quantity of rows when punctured columns are shaped. In some approaches for modulation mapping, each set of bits may be mapped to a quadrature amplitude modulation (QAM) symbol.

The present disclosure relates to a fault detection unit for checking configuration registers and a fault detection method thereof. A fault detection circuit checks configuration registers, performs a configuration register test on a set of registers, reads the settings of the configuration registers, compares the read settings to expected settings. The fault detection circuit includes a parity calculator unit configured to receive a subset of bits stored in a configuration register. A parity code is calculated for the subset of bits. A capture unit receives the parity code output from the parity calculator unit as a captured parity code. A controller then for each parity calculation unit and capture unit: issues a parity calculation control signal to enable calculation of a parity code; issues a capture control signal to enable holding of a parity code value as a captured parity code; receives the captured parity code and compares it to a previously captured parity code; signals a fault if the comparison indicates a change in the value of the captured parity code.

The invention discloses an agricultural product traceability method and system based on a digital signature, and relates to the related field of a product traceability technology.The method comprises the steps that agricultural product information is collected in real time in multiple links of agricultural product production, and the agricultural product information is preliminarily encrypted through an attribute encryption algorithm based on a ciphertext strategy; generating an agricultural product batch identification code for traceability query, and performing digital signature on the encrypted agricultural product information in combination with a quasi-cyclic density parity check code and an elliptic curve algorithm; constructing an agricultural product information traceability query system, inputting an agricultural product identification code by a consumer and a supervision department, verifying the correctness of a digital signature, decrypting the encrypted agricultural product information by using an attribute decryption key, and querying the agricultural product information; when the agricultural product has a quality problem, a link responsibility tracing algorithm is used to carry out responsibility degree evaluation on a responsibility subject of each link, and a basis is provided for responsibility tracing. According to the method, digital signature and responsibility tracing are combined, and the safety guarantee level of agricultural product quality is improved.

The present invention relates to a transmission method using LDPC codes with row-orthogonal structure and a device therefor. A method for encoding a quasi-cyclic low density parity check (LDPC) code according to an embodiment of the present invention can include the steps of generating a multi-edge LDPC code matrix including a high-rate code matrix and a single parity check code matrix; and encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix is formed by concatenating a first matrix having a non-row-orthogonal structure matrix and a second matrix having a pure row-orthogonal structure.

Provided are an operation method of a device in a wireless communication system, and a device using same. The method comprises: generating a plurality of transport blocks; generating code blocks by segmenting the respective plurality of transport blocks; generating aligned code blocks by performing zero padding on a group of code blocks included in mutually different transport blocks among the plurality of transport blocks; generating a parity code block by encoding the aligned code blocks; and transmitting the plurality of transport blocks and the parity code block to a base station, wherein the aligned code blocks all have the same bit length through the zero padding, and the zero padding minimizes the overlapping of the positions of zero-padded bits in mutually different aligned code blocks.

An access point apparatus is configured to communicate with a station apparatus using a plurality of links. The access point apparatus includes a transmitter configured to transmit a plurality of Physical Protocol Data Units (PPDUs) soliciting a plurality of response frames and a receiver configured to receive the plurality of response frames, the plurality of response frames being received on the plurality of links. At least one of the plurality of PPDUs is encoded by using a Low-Density Parity Check Code (LDPC), at least one resource unit (RU) is allocated to the station apparatus, the at least one RU including a group of subcarriers, and in a case of an operation on a pair of non-Simultaneously Transmission and Reception (STR) links, an end time of each of the plurality of PPDUs is aligned.

Provided are an operation method of a device in a wireless communication system, and a device using the method. The method comprises: generating a plurality of transport blocks; performing segmentation of the plurality of transport blocks so as to generate at least one code block for each transport block; performing encoding on code blocks included in two or more transport blocks among the plurality of transport blocks so as to generate parity code blocks; generating a parity codeword including A parity code blocks (A being a natural number) among the parity code blocks; and transmitting the plurality of transport blocks and the parity codeword, wherein a value of A is indicated for each parity codeword.

An operation method of a device in a wireless communication system, and a device using the method are provided. The method comprises: generating a first transmission block and a second transmission block; segmenting the first transmission block so as to generate at least one code block; segmenting the second transmission block so as to generate at least one code block; generating a parity code block on the basis of the first transmission block and the second transmission block; and transmitting the first transmission block, the second transmission block and the parity code block to a base station, wherein the parity code block is generated by encoding a first code block included in the first transmission block and a second code block included in the second transmission block.

A transmission method for feedback information about a transport block of a device in a wireless communication system, and a device using the method are provided. The device according to the method receives a plurality of transport blocks and at least one parity code block included in a transport block group, decodes the plurality of transport blocks on the basis of the at least one parity code block, and transmits feedback information related to the plurality of transport blocks, wherein a feedback time point at which the feedback information is transmitted is related to a time domain window in which the plurality of transport blocks can be received.