41 results about "Parity check code" patented technology

An integrated circuit includes data terminals 0 to 11; an ECC encoder circuit configured to operate an H matrix on transmission data to be transmitted to the data terminals 0 to 11 to generate a transmission parity code, the transmission parity code corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity code received through the data terminals 0 to 11 to detect and correct an error in the reception data. A data portion of the H matrix is divided into 24 groups, each of the 24 groups includes a group matrix portion and a non-group matrix portion, the group matrix portion is used by k group matrices that circulate in the 24 groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups is shifted.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

A quantum computational method is provided. The quantum computational method includes providing a physical quantum system (100) comprising constituents (50). The quantum computational method includes performing an encoded quantum computation on the physical quantum system. Performing the encoded quantum computation includes preparing at least a portion of the physical quantum system in an initial quantum state. Performing the encoded quantum computation includes evolving at least a portion of the physical quantum system to a final quantum state. Performing the encoded quantum computation includes measuring at least a portion of the physical quantum system to provide a read-out. During at least a portion of the encoded quantum computation, the quantum state of at least a portion of the quantum system is an encoded quantum state corresponding to a quantum error-correction code. The quantum error-correction code is a parity code that encodes logical qubits (10) into code qubits (20). The code qubits include parity qubits, wherein each parity qubit represents the parity of an associated subset of logical qubits. Each code qubit is physically implemented in a corresponding subsystem (50, 350) of the physical quantum system, wherein the subsystem comprises one or more constituents. During a first portion of the encoded quantum computation, the code qubits include a first code qubit duplication set (1350, 1450, 1550, 1651-1653, 1750) associated with a first logical qubit. The first code qubit duplication set includes at least three code qubits, wherein either (a) each code qubit in the first code qubit duplication set is a parity qubit representing the parity of a same first subset of logical qubits that includes the first logical qubit or (b) each code qubit in the first code qubit duplication set is a data qubit representing a quantum state of the first logical qubit. The quantum computational method further includes performing a first sequence of physical quantum operations on the physical quantum system during the first portion of the encoded quantum computation. The first sequence of physical quantum operations acts at least on the subsystems of the physical quantum system corresponding to the code qubits in the first code qubit duplication set. The first sequence of physical quantum operations is an encoded realization, via the parity code, of a first logical quantum operation (501-505, 1310, 1410, 1310, 1510, 1610, 1710, 1810) acting at least on the first logical qubit.

A quantum computational method is provided. The quantum computational method includes providing a physical quantum system (100) comprising constituents (50). The quantum computational method includes performing an encoded quantum computation on the physical quantum system. Performing the encoded quantum computation includes preparing at least a portion of the physical quantum system in an initial quantum state. Performing the encoded quantum computation includes evolving at least a portion of the physical quantum system to a final quantum state. Performing the encoded quantum computation includes measuring at least a portion of the physical quantum system to provide a read-out. During at least a portion of the encoded quantum computation, the quantum state of at least a portion of the quantum system is an encoded quantum state corresponding to a quantum error-correction code. The quantum error-correction code is a parity code that encodes logical qubits (10) into code qubits (20). The code qubits include parity qubits, wherein each parity qubit represents the parity of an associated subset of logical qubits. Each code qubit is physically implemented in a corresponding subsystem (50, 350) of the physical quantum system, wherein the subsystem comprises one or more constituents. During a first portion of the encoded quantum computation, the code qubits include a first code qubit duplication set (1350, 1450, 1550, 1651-1653, 1750) associated with a first logical qubit. The first code qubit duplication set includes at least three code qubits, wherein either (a) each code qubit in the first code qubit duplication set is a parity qubit representing the parity of a same first subset of logical qubits that includes the first logical qubit or (b) each code qubit in the first code qubit duplication set is a data qubit representing a quantum state of the first logical qubit. The quantum computational method further includes performing a first sequence of physical quantum operations on the physical quantum system during the first portion of the encoded quantum computation. The first sequence of physical quantum operations acts at least on the subsystems of the physical quantum system corresponding to the code qubits in the first code qubit duplication set. The first sequence of physical quantum operations is an encoded realization, via the parity code, of a first logical quantum operation (501-505, 1310, 1410, 1310, 1510, 1610, 1710, 1810) acting at least on the first logical qubit.

The invention discloses a parity check code updating method, a computer readable storage medium and a solid state disk. The parity check code updating method comprises the following steps: acquiring a new write instruction; writing the write-in data corresponding to the new write-in instruction into the data block of the corresponding strip, and changing the flag bit of the strip into a first state so as to mark the parity check bit of the corresponding strip to be in a failure state; after the data is written, detecting whether the current state of the strip meets a preset condition for updating the parity check bit or not; if yes, reading data in the strip, calculating a corresponding parity check code, updating the parity check code obtained through calculation to the parity check bit of the strip, and changing the flag bit of the strip into the second state so as to mark the parity check bit of the corresponding strip to be in an effective state. In the data writing process, calculation of parity check codes is not carried out, so that the burden of real-time writing is greatly reduced, and the problem of write amplification and energy consumption are effectively reduced.

The objective is to obtain a method for decoding a multi-variable low-density parity check code that can reduce the amount of memory in the memory device constituting the decoding circuit for the multi-variable low-density parity check code, and also reduce the amount of computation required. [Solution] The decoding method for a multi-variable low-density parity check code involves performing row operations and column operations on the result of binary expansion of the Galois field elements that constitute the check matrix in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field.

The application discloses a code length adaptive parity check polar encoding construction method, which is based on a polarization channel, has a low front channel reliability, a high rear reliability and a serial decoding characteristic of a classical polarization decoding scheme SCL, and designs a polar encoding method based on channel reliability and inserting a specified parity check code number of the code length adaptively. The method comprises the following steps: firstly, a channel polarization weight value is obtained based on a Gaussian channel to measure the channel reliability, the polarization weight value is inverted and added to the maximum polarization weight value in the channel for conversion, and then the first insertion of PC code is performed at the position of half PC code number. Finally, the second insertion of PC code is performed based on the remaining PC code number, the information bit length of PC code check and the converted polarization weight value, so that the parity check code with the code length adaptivity and the front dense and rear sparse characteristics is constructed. When SCL decoding is performed at the decoding end, the effective distribution of the parity check code in the information bit is utilized to effectively improve the saving probability of the decoding correct branch and improve the decoding performance.

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Decoding low-density parity check (LDPC) codes in a communication system includes identifying a first set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold. A second set of indices that includes the first set of indices, indices of shortening VNs, and indices of single parity check (SPC) VNs is created. LDPC decoding proceeds by iteratively updating check-to-variable (C2V) messages and variable-to-check (V2C) messages, with updates for a VN being skipped when an index of the respective VN belongs to the second set of indices.

The application relates to the fields of integrated circuits and chip design, and provides a customized logic circuit and design method for peripheral interfaces, which comprises a clock generation module for generating clock signals required by different peripheral interface IPs according to a main clock signal; a synchronous reset module for generating reset signals required by different peripheral interface IPs according to a main reset signal; a self-defined register read-write module for connecting detection signals of the peripheral interface IPs to a state register, reading the state register through a bus, connecting control signals of the peripheral interface IPs to a to-be-configured register, and performing a configuration operation on the register inside the peripheral interface IP through the bus; and a parity check module for generating parity check codes on data links at outputs and inputs of the peripheral interface, and comparing the parity check codes. The application can save a chip design period and accelerate the integration time of a high-speed peripheral interface IP of an SoC chip.

The embodiment of the invention provides a construction method of a check matrix, a storage medium, a computer program product and a related device, and the construction method of the check matrix comprises the steps: generating a basis matrix, and enabling the offset differences of adjacent blocks located in the same row in the basis matrix to be equal; through a progressive edge growth algorithm, according to the sequence of the corresponding priorities from high to low, determining effective check nodes from the plurality of check nodes according to the ring length, the approximate ring external information degree, the external information degree, the ring number and the row weight corresponding to the check nodes in sequence; blocks with the same row number and the same column number corresponding to the effective check nodes in the basis matrix are determined as effective blocks; and setting the blocks except the valid blocks in the basis matrix as invalid blocks to obtain a check matrix for checking the low-density parity check code. According to the scheme, the hardware structure for decoding the low-density parity check code based on the check matrix can be simplified, and the cost of hardware shift in the decoding process of the low-density parity check code is reduced.

Methods, systems, and techniques for detecting errors in qubits within a quantum computing system. In at least one embodiment, at least one quantum check operator is used to couple data qubits with syndrome qubits, a parity-check code is used to couple the syndrome qubits with measure qubits, and the measure qubits are measured to determine whether any errors are present in the data qubits. In at least one embodiment, codewords are coupled to one or more ancilla qubits based at least in part on a binary matrix associated with one or more non-Calderbank-Shor-Steane (“non-CSS”) quantum codes, and the one or more ancilla qubits are used to obtain information about any errors present in the codewords.

The application relates to the field of wireless communication chip data flow scheduling, and discloses a campus teaching service system and method applying 5G messages, which comprises a baseband buffer state monitoring module, a low-density parity check code decoding module, a physical layer resource mapping module and a baseband resource arbitration scheduling module. According to the number of unconfirmed transport blocks and the reserved bandwidth indicator, the system adjusts and reduces the modulation and coding strategy order of multimedia data flow through the baseband resource arbitration scheduling module, and synchronously adjusts the maximum iteration number of the low-density parity check code decoding module. When the core temperature change rate is greater than or equal to 0.5 DEG C / s, the temperature sampling compensation module is used to calculate the phase adjustment step, rewrite the time sequence generator register to finely adjust the starting time boundary of the air interface time slot, correct the clock phase temperature drift under high load, feed forward to eliminate the sudden load, avoid the risk of buffer queue overflow, in-situ repair the control time sequence retreat caused by heat dissipation, and guarantee the deterministic transmission of the baseband chip.

The invention relates to the field of integrated circuits and the field of chip design, and provides a customized logic circuit facing a peripheral interface and a design method.The circuit comprises a clock generation module used for generating clock signals needed by different peripheral interface IPs according to a main clock signal; the synchronous reset module is used for generating reset signals required by different peripheral interface IPs according to the main reset signal; the self-defined register read-write module is used for connecting a detection signal of the peripheral interface IP to a state register, reading the state register through a bus, connecting a control signal of the peripheral interface IP to a register to be configured, and performing configuration operation on the register in the peripheral interface IP through the bus; and the parity check module is used for generating parity check codes on the data links at the output and input positions of the peripheral interface and comparing the parity check codes, so that the chip design period can be saved, and the integration time of the high-speed peripheral interface IP of the SoC chip is shortened.

One or more systems, devices, computer program products and / or computer-implemented methods of use provided herein relate to decoding quantum low-density parity check (qLDPC) codes. For example, a system can comprise a memory that can store computer executable components and a processor that can execute the computer executable components stored in the memory. The computer executable components can comprise an error correction component that corrects, via a decoder, qubit errors for qLDPC code, wherein correcting qubit errors for the qLDPC code via the decoder can comprise: obtaining a set of local defect networks in a syndrome by matching defects on symmetries of the qLDPC code, wherein the symmetries comprise a subset of checks of the qLDPC code such that each qubit error creates an even number of defects; and locally correcting one or more of the set of local defect networks.

Aspects of the disclosure provide a memory system. For example, the memory system can include a memory device configured to store data and one or more parity check codes. The memory system can further include a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule. The memory system can further include a codec coupled to the memory device and the randomizer. The codec can be configured to generate the one or more parity check codes according to the pseudo-randomized numbers and the data. The parity check codes are to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect.

Decoding low-density parity check (LDPC) codes in a communication system includes identifying a first set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold. A second set of indices that includes the first set of indices, indices of shortening VNs, and indices of single parity check (SPC) VNs is created. LDPC decoding proceeds by iteratively updating check-to-variable (C2V) messages and variable-to-check (V2C) messages, with updates for a VN being skipped when an index of the respective VN belongs to the second set of indices.

The present invention provides a coding method, device, medium and program product for a P-LDPC code. The method includes: S1 converting the original film image matrices of multiple P-LDPC codes into test units; S2 defining a mean shift function; S3 calculating the maximum value of the mean shift function to obtain a first initial centroid; S4 calculating a first distortion value of the first initial centroid; S5 calculating a second distortion value of a second test unit closest to the first initial centroid; S6 comparing the first distortion value with the second distortion value; if the second distortion value is less than or equal to the first distortion value, the second test unit is used as the first initial centroid, and it is determined whether the second distortion value is less than a threshold value. If so, the original film image matrix reconstructed by the first initial centroid is output; if not, the process goes to step S3; if the second distortion value is greater than the first distortion value, the test unit closest to the first initial centroid is selected from other test units as the second test unit, and the process goes to step S5. The above scheme reduces the coding design complexity of the original film image low-density parity check code.

The invention relates to continuous variable quantum key distribution, in particular to a continuous variable quantum key distribution post-processing system based on an FPGA (field programmable gate array), which comprises the following steps: a receiving end Bob quantifies a continuous Gaussian variable Y into five-level bit tags L1-L5, calls a low-density parity check code encoder to encode L4 and L5, respectively generates syndromes S4 and S5, and sends the L1-L3, the S4 and the S5 to a sending end Alice; the sending end Alice calls a low-density parity check code decoder to decode and recover the S4 and the S5 to obtain bit tags L '4 and L' 5 through a multi-stage decoding process based on a related variable X held by the sending end Alice and the received L1-L3, S4 and S5, the sending end Alice shares a consistent correction key with the receiving end Bob, and the sending end Alice and the receiving end Bob generate a final security key through privacy amplification by using the correction key; according to the invention, the defects of extremely low throughput, low efficiency and high integration complexity can be effectively overcome.

The invention provides a low-density parity check code decoding method and device, equipment and a storage medium, and the method comprises the steps: receiving to-be-decoded data, and initializing the reliability of all variable nodes; for each check node, obtaining the minimum value, the second minimum value, the second minimum value and the minimum value position of the absolute value of the variable node transmission information of other connected variable nodes; the current calculation position is matched with the minimum value position, and a second minimum value or a minimum value is selected as an updating reference value; determining a normalization factor according to the updated reference value and the like; calculating verification node transmission information according to the updated reference value and the normalization factor, and updating the reliability of the related variable node; and when the reliability of all variable nodes meets a set condition, generating a decoding result. Therefore, by introducing the second minimum value, the adaptive dynamic adjustment of the normalization factor is realized, the operation is simplified, the decoding performance is ensured, and the cost is reduced.

An LDPC decoder includes a parity check code storage block and a plurality of computing engines. The parity check code storage block is configured to store a parity check code matrix. The parity check code matrix includes a plurality of columns. Each of the columns includes a plurality of submatrices. The parity check code storage block includes a plurality of column group storage blocks. Each of the column group storage blocks is configured to store a column group including one or more of the columns. The column group storage block which stores the column group including one or more of the columns is disposed closer to the center of the parity check code storage block. The computing engines are disposed on two sides of the parity check code storage block.

Provided are an operation method of a device in a wireless communication system, and a device using same. The method comprises: generating a plurality of transport blocks; segmenting each of the plurality of transport blocks to generate at least one code block for each transport block; generating parity code blocks by encoding code blocks included in two or more transport blocks among the plurality of transport blocks; and transmitting the plurality of transport blocks and the parity code blocks to a receiver. Here, the encoding is performed by an outer code encoder that receives a plurality of source blocks and outputs a plurality of parity blocks, and information indicating to which source block, among the plurality of source blocks, each of the code blocks is mapped is provided to the receiver.

The invention provides a space coupling LDPC (Low Density Parity Check) code sliding window decoding method based on jump type backtracking and redecoding. The method comprises the following steps: step 1, obtaining a space coupling LDPC code; 2, carrying out side information initialization on a decoding window according to a code word sequence of the space coupling low-density parity check code; step 3, carrying out iterative decoding; 4, calculating the output log-likelihood ratio of the target symbol after the iteration is completed, and carrying out decoding judgment; step 5, activating a jump type backtracking retranslation protocol; and step 6, after the decoding of the current judgment window is completed, the window slides to the next window position towards the lower right corner along the diagonal of the check matrix, and the steps 3-5 are repeated until the decoding window slides out of the matrix. According to the method, error information in a previous window can be prevented from being transmitted to a subsequent window through a coupling structure of the SC-LDPC code, the error propagation phenomenon is relieved, and the sliding window decoding performance is improved.

A fault detection circuit checks configuration registers, performs a configuration register test on a set of registers, reads settings of the configuration registers, and compares the read settings with expected settings. The fault detection circuit includes parity calculator units configured to receive a subset of bits stored in the configuration register. A parity code of said subset of bits is calculated. Capture units receive parity codes output from parity calculator units as captured parity codes. A controller then, for each parity calculation unit and capture unit: issues a parity calculation control signal enabling the calculation of the parity code; issues a capture control signal to enable holding of the parity code value as captured parity code; receives and compares the captured parity code with a previous captured parity code; and signals a fault if the comparison indicates a change in the value of the captured parity code.

The application provides a high-dimensional lossy source decoding method and device for automatic driving, in which n-dimensional source data from a vehicle-mounted sensor is input into a lossy source encoder network to obtain a k-dimensional quaternary sequence; based on a check matrix of a pre-stored original pattern low-density parity check code, algebraic reconstruction is performed on the k-dimensional quaternary sequence on an integer ring to generate an n-dimensional code word satisfying a check constraint; the n-dimensional code word is centrally encoded to map discrete quaternary symbols therein into a continuous numerical sequence centered on zero; and the continuous numerical sequence is input into a pre-trained deep decoder network to obtain a reconstructed Gaussian floating point sequence for environmental perception of automatic driving. Therefore, the scheme provided in the embodiments of the application effectively improves the decoding efficiency and data reconstruction quality in an automatic driving system.

Some examples of the techniques described herein may provide schemes to organize shaped payload bits, non-shaped payload bits, and parity bits to allow an increased quantity of bits to be shaped for enhanced performance. Interleaving may be utilized in some aspects to enhance robustness to burst errors. For instance, interleaving schemes for enhancing bit orderings and interleaving are provided. In some approaches, permutation and row-column interleaving may be performed with a quantity of rows. Some approaches may utilize circular rotation and row-column interleaving with a quantity of rows. In some examples, permutation with alphabet-based row-column interleaving with fixed rows may be performed. Some aspects may include permutation and row-column interleaving with a quantity of rows when punctured columns are shaped. In some approaches for modulation mapping, each set of bits may be mapped to a quadrature amplitude modulation (QAM) symbol.

The present disclosure relates to a fault detection unit for checking configuration registers and a fault detection method thereof. A fault detection circuit checks configuration registers, performs a configuration register test on a set of registers, reads the settings of the configuration registers, compares the read settings to expected settings. The fault detection circuit includes a parity calculator unit configured to receive a subset of bits stored in a configuration register. A parity code is calculated for the subset of bits. A capture unit receives the parity code output from the parity calculator unit as a captured parity code. A controller then for each parity calculation unit and capture unit: issues a parity calculation control signal to enable calculation of a parity code; issues a capture control signal to enable holding of a parity code value as a captured parity code; receives the captured parity code and compares it to a previously captured parity code; signals a fault if the comparison indicates a change in the value of the captured parity code.

The invention provides a high-dimensional lossy information source decoding method and device for automatic driving, and the method comprises the steps: inputting n-dimensional information source data from a vehicle-mounted sensor into a lossy information source encoder network, and obtaining a k-dimensional quaternary sequence; on the basis of a pre-stored check matrix of protograph low-density parity check codes, algebraic reconstruction is carried out on the k-dimensional quaternary sequence on an integer ring, and n-dimensional code words meeting check constraints are generated; performing centralized coding on the n-dimensional code word, and mapping a discrete quaternary symbol in the n-dimensional code word into a continuous numerical sequence taking zero as a center; and inputting the continuous numerical sequence into a pre-trained deep decoder network to obtain a reconstructed Gaussian floating point sequence for automatic driving to perform environment perception. Therefore, by utilizing the scheme provided by the embodiment of the invention, the decoding efficiency and the data reconstruction quality in the automatic driving system are effectively improved.

The invention discloses an agricultural product traceability method and system based on a digital signature, and relates to the related field of a product traceability technology.The method comprises the steps that agricultural product information is collected in real time in multiple links of agricultural product production, and the agricultural product information is preliminarily encrypted through an attribute encryption algorithm based on a ciphertext strategy; generating an agricultural product batch identification code for traceability query, and performing digital signature on the encrypted agricultural product information in combination with a quasi-cyclic density parity check code and an elliptic curve algorithm; constructing an agricultural product information traceability query system, inputting an agricultural product identification code by a consumer and a supervision department, verifying the correctness of a digital signature, decrypting the encrypted agricultural product information by using an attribute decryption key, and querying the agricultural product information; when the agricultural product has a quality problem, a link responsibility tracing algorithm is used to carry out responsibility degree evaluation on a responsibility subject of each link, and a basis is provided for responsibility tracing. According to the method, digital signature and responsibility tracing are combined, and the safety guarantee level of agricultural product quality is improved.

The present invention relates to a transmission method using LDPC codes with row-orthogonal structure and a device therefor. A method for encoding a quasi-cyclic low density parity check (LDPC) code according to an embodiment of the present invention can include the steps of generating a multi-edge LDPC code matrix including a high-rate code matrix and a single parity check code matrix; and encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix is formed by concatenating a first matrix having a non-row-orthogonal structure matrix and a second matrix having a pure row-orthogonal structure.