81 results about "Parity check code" patented technology

The invention relates to a multi-dimensional transmission data compression sensing method and system for urban emergency rescue, and the method comprises the steps: obtaining multi-modal data, carrying out the normalization processing and sparse representation, and obtaining the sparse coefficient of each modal; constructing a block diagonal random matrix for each modal sparse coefficient to perform independent compression sampling, generating a low-dimensional observation value before coding, and performing arithmetic coding and low-density parity check code error correction coding to generate an anti-interference code stream; and performing low-density parity check code decoding and arithmetic decoding on the anti-interference code stream to obtain a decoded low-dimensional observation value, performing iteration by using an orthogonal matching pursuit algorithm, recovering sparse coefficients of each mode, performing reconstruction to obtain text, image and audio features, and projecting the text, image and audio features to a shared semantic space to obtain a shared semantic space. And calculating a joint semantic weight through a cross-modal attention mechanism, and generating a multi-modal fusion result with consistent semantics. The method disclosed by the invention provides an efficient, robust and semantic collaborative end-to-end solution for urban emergency rescue.

The invention provides an OFDM signal receiving and processing system and method suitable for an NAVDAT system. According to the method, the characteristics that NAVDAT system signals have synchronous headers, pilot frequencies and the like are fully considered, firstly, the synchronous headers are used for carrying out correlation operation on received data to search a frame starting point, and a signal frame to be demodulated and decoded is obtained in combination with a constant false alarm detection algorithm; and subsequently, carrying out symbol synchronization to determine the FFT window position. Secondly, in combination with a discrete pilot signal, estimating an integral multiple frequency offset error, namely coarse synchronization, and further realizing estimation of a decimal multiple frequency offset error, namely fine synchronization, so as to realize frequency synchronization. And then, channel estimation is carried out by using the pilot signal and adopting a least square method to obtain the channel frequency response of the pilot, the frequency response of the complete signal is obtained through interpolation, and the rough estimation result is further processed through the designed RCAFCN network to obtain accurate channel estimation, so that the original OFDM signal is recovered. And finally, extracting a data part in the OFDM signal according to a frame structure, realizing soft demodulation through a log-likelihood ratio mode, decoding data of a signaling part by using a polarization code, and decoding data of a service part by using a low-density parity check code, thereby realizing complete demodulation and decoding. The method provided by the invention can effectively reduce inter-symbol interference and inter-carrier interference existing in OFDM signals, compensate channel distortion, reduce noise influence, improve decoding precision, improve communication quality, realize optimization of NAVDAT system baseband processing, and guarantee sailing safety of ships on the sea by combining with an existing marine broadcast system.

The invention discloses a data error correction method and device based on low-density parity check, equipment and a medium, and relates to the technical field of data error correction, and the method comprises the steps: reading data to be corrected from a data memory, and carrying out the pre-verification of the data to be corrected and a verification matrix of a preset low-density parity check code, and obtaining a pre-verification result; based on the pre-verification result, determining a first error position set in a code word position set; performing bit flipping operation on code words indicated by the first error position set to complete pre-error correction; and inputting the code word after pre-error correction processing into a low density parity check decoder for decoding, outputting data after error correction, pre-detecting the error position of the code word, and performing bit flipping on the code word at the error position, thereby reducing the number of error bits entering LDPC decoding, and improving the decoding efficiency. Therefore, the number of error bits does not exceed the decoding capability limit of hard decoding, the probability that the system enters soft decoding is reduced, and the decoding throughput rate of the system is ensured.

The embodiment of the invention provides a coding and decoding method and device and a storage medium, relates to the technical field of communication, and can reduce the storage space requirement of coding. The method comprises the steps that a parity check matrix is determined, the dimension of the parity check matrix is determined based on the dimension of a binary extension matrix, the binary extension matrix is obtained by hashing an index matrix based on a lifting factor, and the lifting factor is determined based on the order of a binary basic matrix, an information bit sequence and a non-binary low-density parity check code NB-LDPC code; and according to the parity check matrix or a generation matrix corresponding to the parity check matrix, performing NB-LDPC coding on the information bit sequence to obtain a coding sequence.

The invention belongs to the technical field of quantum communication, and particularly relates to a discrete variable quantum key distribution data coordination method and system based on a code rate adaptive multi-system LDPC code. Aiming at the defect of performance bottleneck of an existing discrete variable quantum key distribution system adopting a binary low-density parity check code in a long-distance and high-noise environment, the invention provides a discrete variable quantum key distribution data coordination method. The method comprises the following steps: preparing and transmitting a quantum state; screening data; error rate estimation and eavesdropping detection; data coordination based on symbol-level code rate adaptation and / or bit-level code rate adaptation; and confidentiality enhancement. According to the method disclosed by the invention, the construction and storage pressure of the system on error correction codes with different code rates is obviously reduced, the robustness of the system under a complex channel condition is enhanced, and efficient and unconditionally safe key distribution is ensured; the eavesdropping attack can be effectively resisted, and the communication security is ensured.

The invention provides a decoding method of a low-density parity check code, electronic equipment and a storage medium, and relates to the technical field of communication. The method comprises the following steps: acquiring a processor model of a user terminal, and matching system computing power information corresponding to the processor model; obtaining a first case decoding time corresponding to a low density parity check (LDPC) decoding test case; and obtaining the maximum number of iterations according to the system computing power information and the first case decoding time, and performing LDPC decoding based on the maximum number of iterations when the to-be-decoded data is received. According to the LDPC decoding method and device, the maximum number of iterations is cooperatively determined in combination with the two aspects of system computing power information and use case decoding time, LDPC decoding is carried out through the maximum number of iterations, the requirement of a communication system for communication performance is met, the error rate of LDPC decoding is reduced to a certain extent, and therefore the number of retransmission times of data is reduced.

The invention relates to the technical field of communication, in particular to a low-density parity check code generation method and device, computer equipment and a storage medium. The low-density parity check code generation method comprises the following steps: dividing a to-be-processed check matrix of a low-density parity check code into an information bit matrix and a check bit matrix; performing row transformation and rearrangement on the information bit matrix and the check bit matrix based on a preset row index, and performing column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, and solving the matrix equation to obtain each target check bit value in the second check bit matrix; and generating a target codeword of the low-density parity check code based on each information bit in the first information bit matrix and the target check bit value. The invention provides a low-density parity check code generation method which is higher in efficiency, wider in application range and lower in cost.

An integrated circuit includes data terminals 0 to 11; an ECC encoder circuit configured to operate an H matrix on transmission data to be transmitted to the data terminals 0 to 11 to generate a transmission parity code, the transmission parity code corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity code received through the data terminals 0 to 11 to detect and correct an error in the reception data. A data portion of the H matrix is divided into 24 groups, each of the 24 groups includes a group matrix portion and a non-group matrix portion, the group matrix portion is used by k group matrices that circulate in the 24 groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups is shifted.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

A quantum computational method is provided. The quantum computational method includes providing a physical quantum system (100) comprising constituents (50). The quantum computational method includes performing an encoded quantum computation on the physical quantum system. Performing the encoded quantum computation includes preparing at least a portion of the physical quantum system in an initial quantum state. Performing the encoded quantum computation includes evolving at least a portion of the physical quantum system to a final quantum state. Performing the encoded quantum computation includes measuring at least a portion of the physical quantum system to provide a read-out. During at least a portion of the encoded quantum computation, the quantum state of at least a portion of the quantum system is an encoded quantum state corresponding to a quantum error-correction code. The quantum error-correction code is a parity code that encodes logical qubits (10) into code qubits (20). The code qubits include parity qubits, wherein each parity qubit represents the parity of an associated subset of logical qubits. Each code qubit is physically implemented in a corresponding subsystem (50, 350) of the physical quantum system, wherein the subsystem comprises one or more constituents. During a first portion of the encoded quantum computation, the code qubits include a first code qubit duplication set (1350, 1450, 1550, 1651-1653, 1750) associated with a first logical qubit. The first code qubit duplication set includes at least three code qubits, wherein either (a) each code qubit in the first code qubit duplication set is a parity qubit representing the parity of a same first subset of logical qubits that includes the first logical qubit or (b) each code qubit in the first code qubit duplication set is a data qubit representing a quantum state of the first logical qubit. The quantum computational method further includes performing a first sequence of physical quantum operations on the physical quantum system during the first portion of the encoded quantum computation. The first sequence of physical quantum operations acts at least on the subsystems of the physical quantum system corresponding to the code qubits in the first code qubit duplication set. The first sequence of physical quantum operations is an encoded realization, via the parity code, of a first logical quantum operation (501-505, 1310, 1410, 1310, 1510, 1610, 1710, 1810) acting at least on the first logical qubit.

The invention relates to an ultrahigh-dimensional continuous variable quantum key distribution (CV-QKD) information negotiation method based on matrix cross rotation, which is characterized in that after quantum state transmission, basis screening and parameter estimation are completed, an associated Gaussian sequence with the length of N is generated, and due to the existence of quantum channel noise, the quality of an extracted key is possibly obviously reduced. To this end, multi-dimensional information negotiation becomes a critical step for correcting codeword errors in order to establish a shared key between two communicating parties and to leak key information as little as possible. According to the invention, the dimensionality of CV-QKD information negotiation is significantly improved based on matrix cross rotation, and efficient transmission of quantum keys is realized in combination with low-density parity check codes.

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

A quantum computational method is provided. The quantum computational method includes providing a physical quantum system (100) comprising constituents (50). The quantum computational method includes performing an encoded quantum computation on the physical quantum system. Performing the encoded quantum computation includes preparing at least a portion of the physical quantum system in an initial quantum state. Performing the encoded quantum computation includes evolving at least a portion of the physical quantum system to a final quantum state. Performing the encoded quantum computation includes measuring at least a portion of the physical quantum system to provide a read-out. During at least a portion of the encoded quantum computation, the quantum state of at least a portion of the quantum system is an encoded quantum state corresponding to a quantum error-correction code. The quantum error-correction code is a parity code that encodes logical qubits (10) into code qubits (20). The code qubits include parity qubits, wherein each parity qubit represents the parity of an associated subset of logical qubits. Each code qubit is physically implemented in a corresponding subsystem (50, 350) of the physical quantum system, wherein the subsystem comprises one or more constituents. During a first portion of the encoded quantum computation, the code qubits include a first code qubit duplication set (1350, 1450, 1550, 1651-1653, 1750) associated with a first logical qubit. The first code qubit duplication set includes at least three code qubits, wherein either (a) each code qubit in the first code qubit duplication set is a parity qubit representing the parity of a same first subset of logical qubits that includes the first logical qubit or (b) each code qubit in the first code qubit duplication set is a data qubit representing a quantum state of the first logical qubit. The quantum computational method further includes performing a first sequence of physical quantum operations on the physical quantum system during the first portion of the encoded quantum computation. The first sequence of physical quantum operations acts at least on the subsystems of the physical quantum system corresponding to the code qubits in the first code qubit duplication set. The first sequence of physical quantum operations is an encoded realization, via the parity code, of a first logical quantum operation (501-505, 1310, 1410, 1310, 1510, 1610, 1710, 1810) acting at least on the first logical qubit.

The invention discloses a parity check code updating method, a computer readable storage medium and a solid state disk. The parity check code updating method comprises the following steps: acquiring a new write instruction; writing the write-in data corresponding to the new write-in instruction into the data block of the corresponding strip, and changing the flag bit of the strip into a first state so as to mark the parity check bit of the corresponding strip to be in a failure state; after the data is written, detecting whether the current state of the strip meets a preset condition for updating the parity check bit or not; if yes, reading data in the strip, calculating a corresponding parity check code, updating the parity check code obtained through calculation to the parity check bit of the strip, and changing the flag bit of the strip into the second state so as to mark the parity check bit of the corresponding strip to be in an effective state. In the data writing process, calculation of parity check codes is not carried out, so that the burden of real-time writing is greatly reduced, and the problem of write amplification and energy consumption are effectively reduced.

The objective is to obtain a method for decoding a multi-variable low-density parity check code that can reduce the amount of memory in the memory device constituting the decoding circuit for the multi-variable low-density parity check code, and also reduce the amount of computation required. [Solution] The decoding method for a multi-variable low-density parity check code involves performing row operations and column operations on the result of binary expansion of the Galois field elements that constitute the check matrix in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field.

The invention provides a distributed parity check code-based polar code SCSPL decoding algorithm, which comprises the following steps of: firstly, constructing a key set according to Hamming weight in combination with error distribution of channel error frequency, then executing a distributed parity check scheme on information bits in the key set, pruning a path which does not pass the check, and finally, carrying out decoding on the path which does not pass the check; if no path passes the distributed parity check, decoding is terminated in advance, a new key set is constructed, a re-decoding scheme based on shift pruning is executed, and when the last information bit is decoded, CRC check is executed, and the path passing the CRC check is output. According to the algorithm, invalid decoding attempts can be avoided, and the average decoding complexity is effectively reduced.

The application discloses a code length adaptive parity check polar encoding construction method, which is based on a polarization channel, has a low front channel reliability, a high rear reliability and a serial decoding characteristic of a classical polarization decoding scheme SCL, and designs a polar encoding method based on channel reliability and inserting a specified parity check code number of the code length adaptively. The method comprises the following steps: firstly, a channel polarization weight value is obtained based on a Gaussian channel to measure the channel reliability, the polarization weight value is inverted and added to the maximum polarization weight value in the channel for conversion, and then the first insertion of PC code is performed at the position of half PC code number. Finally, the second insertion of PC code is performed based on the remaining PC code number, the information bit length of PC code check and the converted polarization weight value, so that the parity check code with the code length adaptivity and the front dense and rear sparse characteristics is constructed. When SCL decoding is performed at the decoding end, the effective distribution of the parity check code in the information bit is utilized to effectively improve the saving probability of the decoding correct branch and improve the decoding performance.

The present invention relates to the technical field of satellite remote control information processing, and particularly relates to a method, system, storage medium and electronic device for batch generating remote control instructions of a satellite. The method includes: respectively determining the fixed characters of each four-byte basic instruction code; splicing any four-byte basic instruction code and the fixed characters corresponding to the four-byte basic instruction code to obtain the instruction valid data corresponding to the four-byte basic instruction code, performing exclusive OR and parity check on the instruction valid data corresponding to the four-byte basic instruction code, generating two-byte parity check codes corresponding to the four-byte basic instruction code, and performing splicing to obtain the valid test instruction corresponding to the four-byte basic instruction code until the valid test instructions corresponding to each four-byte basic instruction code are obtained. It can batch generate valid test instructions, greatly improving the efficiency of instruction generation and also solving the problem of instruction version control caused by frequent changes in the technical state.

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Decoding low-density parity check (LDPC) codes in a communication system includes identifying a first set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold. A second set of indices that includes the first set of indices, indices of shortening VNs, and indices of single parity check (SPC) VNs is created. LDPC decoding proceeds by iteratively updating check-to-variable (C2V) messages and variable-to-check (V2C) messages, with updates for a VN being skipped when an index of the respective VN belongs to the second set of indices.

The application relates to the fields of integrated circuits and chip design, and provides a customized logic circuit and design method for peripheral interfaces, which comprises a clock generation module for generating clock signals required by different peripheral interface IPs according to a main clock signal; a synchronous reset module for generating reset signals required by different peripheral interface IPs according to a main reset signal; a self-defined register read-write module for connecting detection signals of the peripheral interface IPs to a state register, reading the state register through a bus, connecting control signals of the peripheral interface IPs to a to-be-configured register, and performing a configuration operation on the register inside the peripheral interface IP through the bus; and a parity check module for generating parity check codes on data links at outputs and inputs of the peripheral interface, and comparing the parity check codes. The application can save a chip design period and accelerate the integration time of a high-speed peripheral interface IP of an SoC chip.

The invention provides a signal decoding method and system, a computer readable storage medium, electronic equipment and a computer program product, and relates to the technical field of communication, and the method comprises the steps: obtaining a received signal, and carrying out the modulation and demodulation of the received signal, and obtaining soft bit information; the received signal is a signal generated through finite field linear block code coding and low-density parity check coding cascade coding; performing belief propagation iterative decoding of new air interface low-density parity check on the soft bit information to obtain a code word corresponding to a low-density parity check mother code; performing bit flipping hard decision decoding on the codeword corresponding to the low-density parity check mother code to obtain a finite field linear block code codeword; and performing finite field linear block code hard decision decoding on the finite field linear block code codeword to obtain information bits after receiving signal decoding. According to the method, the success rate of finite field linear block code hard decision decoding can be increased, an error code platform in a short code scene is remarkably reduced, and decoding time delay is effectively reduced.

The embodiment of the invention provides a construction method of a check matrix, a storage medium, a computer program product and a related device, and the construction method of the check matrix comprises the steps: generating a basis matrix, and enabling the offset differences of adjacent blocks located in the same row in the basis matrix to be equal; through a progressive edge growth algorithm, according to the sequence of the corresponding priorities from high to low, determining effective check nodes from the plurality of check nodes according to the ring length, the approximate ring external information degree, the external information degree, the ring number and the row weight corresponding to the check nodes in sequence; blocks with the same row number and the same column number corresponding to the effective check nodes in the basis matrix are determined as effective blocks; and setting the blocks except the valid blocks in the basis matrix as invalid blocks to obtain a check matrix for checking the low-density parity check code. According to the scheme, the hardware structure for decoding the low-density parity check code based on the check matrix can be simplified, and the cost of hardware shift in the decoding process of the low-density parity check code is reduced.

Methods, systems, and techniques for detecting errors in qubits within a quantum computing system. In at least one embodiment, at least one quantum check operator is used to couple data qubits with syndrome qubits, a parity-check code is used to couple the syndrome qubits with measure qubits, and the measure qubits are measured to determine whether any errors are present in the data qubits. In at least one embodiment, codewords are coupled to one or more ancilla qubits based at least in part on a binary matrix associated with one or more non-Calderbank-Shor-Steane (“non-CSS”) quantum codes, and the one or more ancilla qubits are used to obtain information about any errors present in the codewords.

The application relates to the field of wireless communication chip data flow scheduling, and discloses a campus teaching service system and method applying 5G messages, which comprises a baseband buffer state monitoring module, a low-density parity check code decoding module, a physical layer resource mapping module and a baseband resource arbitration scheduling module. According to the number of unconfirmed transport blocks and the reserved bandwidth indicator, the system adjusts and reduces the modulation and coding strategy order of multimedia data flow through the baseband resource arbitration scheduling module, and synchronously adjusts the maximum iteration number of the low-density parity check code decoding module. When the core temperature change rate is greater than or equal to 0.5 DEG C / s, the temperature sampling compensation module is used to calculate the phase adjustment step, rewrite the time sequence generator register to finely adjust the starting time boundary of the air interface time slot, correct the clock phase temperature drift under high load, feed forward to eliminate the sudden load, avoid the risk of buffer queue overflow, in-situ repair the control time sequence retreat caused by heat dissipation, and guarantee the deterministic transmission of the baseband chip.

The present invention specifically relates to an improved polar code EPC‑MS‑SCL decoding method based on an enhanced parity check code. The present invention belongs to the technical field of channel coding. The method performs segmentation processing on the information sequence in the polar code encoding stage, adds an enhanced parity check code at the end of each segment, and the decoder only performs path splitting when decoding elements in the search set (SS). The remaining elements directly perform hard decision decoding, and immediately verify the segment after decoding a sequence. Only the path that passes the verification is retained, which reduces the competition of the wrong path for the correct path, increases the probability that the correct path is retained until the end of decoding, and reduces the number of decoding lists, so that the decoding complexity is lower. Simulation results show that the improved polar code EPC‑MS‑SCL decoding method proposed in the present invention has obvious decoding performance improvement and reduced decoding complexity compared with the decoding method based on the path splitting strategy assisted polar code serial cancellation list (PSS‑SS‑SCL).

A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

The invention relates to the field of integrated circuits and the field of chip design, and provides a customized logic circuit facing a peripheral interface and a design method.The circuit comprises a clock generation module used for generating clock signals needed by different peripheral interface IPs according to a main clock signal; the synchronous reset module is used for generating reset signals required by different peripheral interface IPs according to the main reset signal; the self-defined register read-write module is used for connecting a detection signal of the peripheral interface IP to a state register, reading the state register through a bus, connecting a control signal of the peripheral interface IP to a register to be configured, and performing configuration operation on the register in the peripheral interface IP through the bus; and the parity check module is used for generating parity check codes on the data links at the output and input positions of the peripheral interface and comparing the parity check codes, so that the chip design period can be saved, and the integration time of the high-speed peripheral interface IP of the SoC chip is shortened.

One or more systems, devices, computer program products and / or computer-implemented methods of use provided herein relate to decoding quantum low-density parity check (qLDPC) codes. For example, a system can comprise a memory that can store computer executable components and a processor that can execute the computer executable components stored in the memory. The computer executable components can comprise an error correction component that corrects, via a decoder, qubit errors for qLDPC code, wherein correcting qubit errors for the qLDPC code via the decoder can comprise: obtaining a set of local defect networks in a syndrome by matching defects on symmetries of the qLDPC code, wherein the symmetries comprise a subset of checks of the qLDPC code such that each qubit error creates an even number of defects; and locally correcting one or more of the set of local defect networks.

The invention provides a wireless communication method, a wireless transmitting device and a wireless receiving device. The wireless communication method is executed by a wireless transmitting device and comprises the following steps of: framing; a scrambling step; the channel coding step comprises at least one of the following steps: carrying out first SBCC coding on the SFD scrambling sequence to obtain an SFD coding sequence; performing second SBCC coding on the Header scrambling sequence to obtain a Header coding sequence, and performing binary convolutional coding (BCC) or low density parity check code (LDPC) on the scrambled service bit sequence; a symbol modulation step: performing symbol modulation on the bit sequence output in the channel coding step to obtain a modulation symbol sequence; a barker code spread spectrum step to obtain a spread spectrum symbol sequence; a front-end processing step; and a transmitting step. According to the scheme of the invention, channel coding can be carried out on at least one of the SFD, the Header and the PSDU in the 802.11 b frame to obtain the channel coding gain, so that the wireless access performance is improved, and forward compatibility with 802.11 equipment is realized.

Aspects of the disclosure provide a memory system. For example, the memory system can include a memory device configured to store data and one or more parity check codes. The memory system can further include a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule. The memory system can further include a codec coupled to the memory device and the randomizer. The codec can be configured to generate the one or more parity check codes according to the pseudo-randomized numbers and the data. The parity check codes are to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect.