468 results about "Parity check code" patented technology

A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x¹⁰+x³+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x⁶+1.

The invention discloses a quasi-cyclic low-density parity-check code decoder which comprises an initializing unit used for receiving the log-likelihood ratio of code word information from a communication channel, a decoding unit used for calculating the update information between a close-by variable node and a check node according to a message transmission rule, a decoding convergence judging unit used for judging the finish of decoding according to the convergence of the update information of the variable node after each iteration or whether the maximum predetermined iteration time is reached, and a hard decision unit used for implementing hard decision according to the symbol of the variable code information after decoding and obtaining code words. The invention also discloses a decoding method of a quasi-cyclic low-density parity-check code which comprises the steps of initializing each non-zero position in a check matrix H, iterative process, and trying to judge. The invention can accelerate the convergence rate of decoding, reduce the performance loss caused by quantification and lower the complexity of realization of the decoder.