459 results about "Parity check code" patented technology

The disclosed technology provides a less resource intensive way to decode a parity check code using a modified min-sum algorithm. For a particular parity check constraint that includes n variable nodes, an LDPC decoder can compute soft information for one of the variable nodes based on combinations of soft information from other variable nodes, wherein each combination includes soft information from at most a number d of other variable nodes. In one embodiment, soft information from one of the other variable nodes is used in a combination only if it corresponds to a non-most-likely value for the other variable node.

A disk drive is disclosed comprising a disk and a head actuated over the disk. The disk comprises a plurality of tracks, wherein each track comprises a plurality of data sectors including a parity sector, the parity sector comprising at least a P0 parity codeword and a P1 parity codeword. A plurality of data sectors are read from the disk (including the parity sector) to generate a plurality of data codewords CW0-CWn. The data sectors are decoded using an error correction code (ECC) decoder. When a single data codeword in CW0-CWn is unrecoverable using the ECC decoder, the single data codeword is recovered using the P0 parity codeword. When two data codewords in CW0-CWn are unrecoverable using the ECC decoder, the two data codewords are recovered using the P0 and P1 parity codewords.

The invention discloses a polarization code and multi-bit even parity check code cascaded error correction coding method. The method comprises the steps: a transmitting end encoder utilizes a multi-bit even parity check code as an outer code, and utilizes a polarization code as an inner code; a receiving end decoder decodes by utilizing a modified successive cancellation list (SCL) decoding algorithm. On the aspect of error correction performance, comparing with the prior art utilizing middle-short code length non-cascaded polarization codes of the SCL decoding algorithm, the polarization code and multi-bit even parity check code cascaded error correction coding method has the advantages that frame error rate performance of a system can be remarkably improved, and a maximum likelihood bound (ML Bound), which cannot be broken through by the SCL decoding algorithm, can be remarkably broken through. On the aspect of engineering realization, according to the polarization code and multi-bit even parity check code cascaded error correction coding method, the outer code utilizes the multi-bit even parity check code, which is simple to code; the modified SCL decoding algorithm is utilized to decode, bit decision and even parity check are combined to be carried out in a decoding process, and compared with the original SCL decoding algorithm, the method provided by the invention does not increase the decoding complexity, and facilitates the engineering realization.

A method and apparatus perform forward error correction in a wireless communication device in a wireless communication network. Application layer forward error correction (AL-FEC) capability information is transmitted during a capabilities exchange. A set of source packets are reshaped to k equal-sized source symbols. Systematic packets for the source symbols and at least one parity packet is encoded using a single parity check (SPC) AL-FEC code on the k source symbols. A header of each encoded packet includes a parity packet indicator. The encoded packets are processed in a media access control (MAC) layer and a physical (PHY) layer for transmission.

An LDPC code encoding apparatus includes: a code matrix generator for generating and transmitting a parity-check matrix comprising a combination of square matrices having a unique value on each row and column thereof; an encoding means encoding block LDPC codes according to the parity-check matrix received from the code matrix generator; and a codeword selector for puncturing the encoded result of the encoding means to generate an LDPC codeword. The code matrix generator divides an information word to be encoded into block matrices having a predetermined length to generate a vector information word. The encoding means encodes the block LDPC codes using the parity-check matrix divided into the block matrices and a Tanner graph divided into smaller graphs in correspondence to the parity-check matrix.

An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For a rate 3/5 code, the approach provides a degree profile that yields reduced memory requirements for storage of the edge values without significantly affecting the performance with respect to an “unmodified” rate 3/5 code. The relevant parameters for the reduced memory LDPC codes are as follows: q=72, n_ldpc=64800, k_ldpc=n_BCH=38880, k_BCH=38688. The above approach has particular application in digital video broadcast services over satellite.

This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.

A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x¹⁰+x³+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x⁶+1.

An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For ⅓ rate, the relevant parameters are as follows: q=120, n_ldpc=64,800, k_ldpc=n_BCH=21600, k_BCH=21408 (12 bit error correcting BCH). For ¼ rate, the LDPC code has the following relevant parameters: q=135, n_ldpc=64,800, k_ldpc=n_BCH=16200, k_BCH=16008 (12 bit error correcting BCH). For ⅖ rate, the following parameters exist: q=108, n_ldpc=64800, k_ldpc=n_BCH=25920, k_BCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.

An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of 3/5 utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.

A higher code rate Low-Density Parity Check (LDPC) matrix may be designed by concatenating additional matrices to a π-rotation parity check matrix. The concatenated matrix may be selected such that the resultant LDPC matrix exhibits good expansion characteristics to enable the LDPC matrix to be used with variable block length codes. The codes may be designed by generating an ensemble of available codes, encoding them with information vectors of weight 1 and 2 and discarding codes with a low minimum distance. The approximate upper bounds for the remaining codes are then calculated and a small set of codes with the lowest bound under high signal to noise ratio is selected. The girth distributions for the remaining codes are then calculated and the code that has the minimum number of short cycles is selected. The selected code is concatenated to the original v-rotation parity check matrix.

The invention discloses a low-complexity polarization code decryption SCL algorithm based on segmented verification assistance, and the algorithm selects a parity check code, repeatedly uses the parity check code in a decryption process, and achieves the performances of SCL-CRC24. Moreover, compared with a conventional scheme, the algorithm is better in low signal to noise ratio anti-noise performance and error rate. In addition, the spatial complexity of the algorithm is lower than that of the SCL-CRC24, the time complexity is greatly reduced, and the decoding speed is greatly improved. Compared with a CRC-24 verification algorithm sacrificing multiple information bits, the algorithm employs a parity check method, enables verification elements to be distributed in the information bits, is repeatedly used in the decoding process, and is lower in time complexity than the prior art.

The Hamming distance of an array of storage devices is increased by generating a parity check matrix based on column equations that are formed using an orthogonal parity code and includes a higher-order multiplier that changes each column. The higher order multiplier is selected to generate a finite basic field of a predetermined number of elements. The array has M rows and N columns, such that M is greater than or equal to three and N is greater than or equal to three. Row 1 through row M-2 of the array each have n-p data storage devices and p parity storage devices. Row M-1 of the array has n-(p+1) data storage devices and (p+1) parity storage devices. Lastly, row M of the array has N parity storage devices.

The method includes following steps: (1) based on inputted K bits information packet, encoder for low-density parity check code crates code word in NFIR bits LDPC HARQ parent code; the code word includes bit information packet, expanded check bit packet, and remaining check bit packet after deletion; the created code word is sent to HARQ buffer; (2) rearranging bits of code word of LDPC HARQ parent code in HARQ buffer, and keeping sequence of information bits and expanded check bits unchanged, and changing sequence of remaining check bits; (3) selecting bits code word in sequence from rearranged code word of HARQ parent code, i.e. first transmission starts up from first system bits, and then, start position of each transmission follows close to position of ending the previous transmission so as to generate binary sequence of HARQ packet.

The invention discloses a quasi-cyclic low-density parity-check code decoder which comprises an initializing unit used for receiving the log-likelihood ratio of code word information from a communication channel, a decoding unit used for calculating the update information between a close-by variable node and a check node according to a message transmission rule, a decoding convergence judging unit used for judging the finish of decoding according to the convergence of the update information of the variable node after each iteration or whether the maximum predetermined iteration time is reached, and a hard decision unit used for implementing hard decision according to the symbol of the variable code information after decoding and obtaining code words. The invention also discloses a decoding method of a quasi-cyclic low-density parity-check code which comprises the steps of initializing each non-zero position in a check matrix H, iterative process, and trying to judge. The invention can accelerate the convergence rate of decoding, reduce the performance loss caused by quantification and lower the complexity of realization of the decoder.

Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder (200) for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (202), which further include a plurality of interconnected nodes. A memory can be interconnected with the nodes to store intermediate log likelihood ratio (LLR) values based on channel LLR values. Thus, LLR values having successively improved accuracy relative to the channel LLR values can be output from each processor, and eventually used to decision information bits. In some embodiments, the memory is a random access memory (RAM) device that is adapted to store the intermediate LLR values in a circular buffer. Additionally, a storage device such as a read-only memory (ROM) device can be used to generate a predetermined plurality of addresses for reading and writing LLR values.

A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.

A method is provided for puncturing a low density parity check (LDPC) code decoded by a parity check matrix that is expressed by a factor graph including a check node and a bit node, being connected to each other at an edge, and includes a parity part having a dual diagonal matrix with a single 3-weight column and the remaining columns being 2-weight columns. The method includes generating a puncturing pattern such that bits of the LDPC code are punctured in an order of a bit mapped to a column with a higher weight from among the columns constituting the parity part; and puncturing the LDPC code according to the generated puncturing pattern.