36 results about "Routing congestion" patented technology

A dynamic grid allocation system for power distribution in the development of integrated circuits in the sub-five-nanometer range, wherein the system comprises the following: a placement processor unit configured to receive a synthesized netlist comprising a variety of standard cells and macros, each associated with switching activity data derived from simulation or synthesis activity profiles, and to generate a spatial cell placement arrangement by grouping cells into microzones based on activity correlation, time sensitivity, and connection proximity; a power density calculation unit coupled to the placement processor unit and configured to calculate the local power density and instantaneous current demand for each microzone based on the spatial distribution of switching operations, capacity load, and effective switching frequencies; a dynamic network generation unit coupled to the power density calculation unit and configured to generate a multilayer power distribution network with variable network topology, where the width, spacing, via density and metal layer assignment of the power network are adaptively determined as continuous functions of the localized power density and power demand calculated for each microzone; a topology control processor configured to monitor voltage drop and electromigration data obtained from signoff analyses or predictive models in real time and dynamically adjust the power grid topology parameters to ensure compliance with predefined reliability thresholds for voltage drop and electromigration; a predictive current modeling unit configured to receive historical switching and voltage data, train a predictive model for transient current peaks, and provide predictive power boost instructions to the dynamic grid generation unit before power integrity violations occur; and A feedback synchronization controller is communicatively connected to the placement processor unit and the topology control processor, whereby the feedback synchronization controller continuously exchanges updated power density information and placement constraints, so that cell placement and network topology adapt together in real time, thereby minimizing routing congestion, ensuring a uniform voltage distribution, and guaranteeing compliance with electromigration and IR drop regulations under various activity conditions.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

An interconnect fabric in an integrated circuit (IC) device can be hierarchically partitioned into a set of peripheral sub-fabrics and a glue sub-fabric coupled to each of the peripheral sub-fabrics based on the physical design information associated with the IC device. Each of the peripheral sub-fabrics and the glue sub-fabric can be implemented using 2:1 hierarchical multiplexers based on an agglomerative clustering scheme. Physically aware design of the hierarchical multiplexer tree along with the optimal placement of the 2:1 multiplexers can provide smaller overall wire length and reduced routing congestion in the interconnect.

The invention relates to a load capacitance optimization method and system based on dichotomy and dynamic variable control. When load capacitance reduction processing is carried out on each load capacitance violation signal line, the method comprises the following steps: extracting load capacitance basic characteristics of the load capacitance violation signal line, and determining load capacitance formation characteristics of the load capacitance violation signal line based on the extracted load capacitance basic characteristics, and selecting a buffer insertion state corresponding to a load capacitance forming characteristic based on the load capacitance forming characteristic of the current load capacitance violation signal line, and performing buffer insertion processing on the current load capacitance violation signal line based on the selected buffer insertion state. According to the method, the forming state of the heavy-load capacitor can be accurately positioned, the buffer is inserted and arranged according to the forming state of the heavy-load capacitor, and the risks of time sequence violation, wiring congestion and power consumption exceeding are avoided while the load capacitance is reduced.

The invention discloses a BGA simultaneous escape wiring method based on shared node and combined congestion negotiation, and belongs to the technical field of electronic design automation. The method comprises the following steps: constructing a directed graph representing a wiring space, and determining a starting point and an ending point of each to-be-wired network; adopting a bidirectional Dijkstra algorithm to carry out parallel path search on all the networks; dividing the line network into a single line network and a conflict line network containing shared nodes; the conflicting networks are grouped, so that the networks in the group only share nodes with one another; on the basis of a network quality evaluation model, selecting one network from each group to remove the network, and dynamically updating the cost value of wiring nodes; and iteratively executing the steps of searching, grouping, clearing and cost adjustment until all the wire nets are single wire nets, and outputting a final wiring result. According to the method, wiring congestion can be effectively reduced, path bypassing is avoided, and the success rate, the wiring quality and the algorithm convergence efficiency of BGA packaging and escape wiring are remarkably improved.

The invention relates to the technical field of logistics transportation, and discloses a transmission line motion direction control method, which comprises the following steps: S1, when materials reach a fork on a transmission line, a transmission line control module sends a route request to an upper scheduling module; s2, the upper scheduling module dynamically generates a next section of conveying route according to the busy state of the current transmission line, the task end point of the material and the task priority; and S3, the transmission line control module receives the next section of carrying route, controls a movement mechanism of the transmission line to carry the materials to the end point of the stage, and then feeds back a completion signal to the upper scheduling module. According to the invention, the busy state of each node of the transmission line is obtained in real time through the upper scheduling module, and the next optimal conveying route is dynamically calculated and generated in combination with the task end point and priority of the material, so that the problem of route congestion and even blockage caused by excessive goods in a traditional fixed route mode is solved, and the congestion nodes can be intelligently avoided.

The embodiment of the invention discloses an information interaction method and device. According to the embodiment of the invention, after a congestion hotspot analysis instruction is received, congestion hotspot analysis is carried out on a to-be-tested gate-level netlist to determine at least one combinational logic congestion hotspot, and a to-be-modified code statement is determined in a register transfer-level code according to the combinational logic congestion hotspot; and modifying each to-be-modified code statement into a target code statement, and regenerating a target gate-level netlist according to the modified register transfer-level code. Wherein the to-be-modified code statement only supports to be converted into a combinational logic structure in the logic synthesis process, and the target code statement supports to be converted into a multiplexer structure in the logic synthesis process. Therefore, the embodiment of the invention can support a user to analyze and solve the wiring congestion problem in the logic synthesis process, so that the chip design efficiency is improved, and the negative effects of the wiring congestion problem solving process on the power consumption, the performance and the area of the formed chip are reduced.

The application discloses a kind of sideband signal communication configuration circuit for on-chip network mounting IP, belong to chip design field, comprising: low-speed protocol communication configuration interface module, AXB sideband communication interface module, on-chip network module.First, the request of reading and writing sideband signal register based on low-speed protocol of external equipment is received, protocol is converted into the request package of on-chip network form, is sent to each routing node by on-chip network module, then utilizes protocol decoding bypass mainband communication interface, enters the AXB sideband communication interface module of current node, connects the configuration bus of IP, controls the reading and writing request of IP sideband signal register, then when reading and writing request succeeds, original road returns reading and writing response to external equipment.The application can effectively improve the wiring congestion of large scale on-chip network, timing bottleneck, increase the bandwidth of data path and configuration path, reduce kernel address occupation, while also beneficial to the rapid expansion integration of on-chip network.

The invention discloses a sideband signal communication configuration circuit for a network-on-chip mounting IP, which belongs to the field of chip design and comprises a low-speed protocol communication configuration interface module, an AXB sideband communication interface module and a network-on-chip module. The method comprises the following steps: firstly, receiving a low-speed protocol-based sideband signal register read-write request of external equipment, converting a protocol into a request packet oriented to an on-chip network form, sending the request packet to each routing node through an on-chip network module, decoding a bypass main band communication interface, entering an AXB sideband communication interface module of the current node and connecting a configuration bus of an IP (Internet Protocol) by utilizing the protocol, and finally, carrying out routing on the AXB sideband communication interface module. And a read-write request of the IP sideband signal register is controlled, and then when the read-write request succeeds, a read-write response is returned to the external equipment along the original path. According to the method, the wiring congestion and the time sequence bottleneck when the scale of the network-on-chip is relatively large can be effectively improved, the bandwidths of a data path and a configuration path are increased, the occupation of a kernel address is reduced, and meanwhile, the method is also beneficial to rapid expansion and integration of the network-on-chip.

The application relates to the field of integrated circuit design and test technology, and discloses a scan chain port layout optimization method, device and electronic equipment. The core of the method comprises the following steps: an intelligent nearest matching step of a scan chain port and a scan chain, in which a nearest unassigned scan chain is searched as a candidate by sequentially selecting a scan chain port, and it is judged whether the scan chain is matched according to a preset distance constraint threshold, so that a first matching relationship is established; and a step of performing dynamic port rearrangement on the unassigned ports and scan chains that are not successfully matched to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of the scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and the robustness of the design process and the convergence of the test timing are improved.

A switching fabric uses traffic congestion information to inform its opportunistic use of non-minimal routes. An ingress port of a network switch collects traffic congestion information from the egress ports of the network switch. The traffic congestion information includes minimal and non-minimal route congestion metrics for the egress ports. Candidate egress ports for forwarding a packet to a destination node are identified. One of the candidate egress ports is selected based on the traffic congestion information. The selection process is biased to prefer some candidate egress ports over others. Particularly, the candidate egress ports that provide non-minimal routes to the destination node and have high minimal route congestion metrics are disfavored by the selection process.

The present disclosure relates to multi-path routing of a switch fabric. The switch fabric uses traffic congestion information to inform its timely use of non-minimal routes. An ingress port of a network switch collects traffic congestion information from egress ports of the network switch. The traffic congestion information includes minimal and non-minimal route congestion metrics for the egress ports. Candidate egress ports are identified for forwarding a packet to a destination node. One of the candidate egress ports is selected in accordance with the traffic congestion information. The selection process favors selecting some candidate egress ports over others. In particular, non-minimal routes to the destination node and candidate egress ports having high minimal route congestion metrics are disfavored by the selection process.

The invention relates to the technical field of integrated circuit design and testing, and discloses a scan chain port layout optimization method and device and electronic equipment. The method comprises the following steps: sequentially selecting scan chain ports, searching an unallocated scan chain with the shortest physical distance as a candidate, and judging whether the unallocated scan chain is matched or not according to a preset distance constraint threshold value, so as to establish a first matching relationship; and executing dynamic port rearrangement on the ports which are not successfully matched and the scan chain to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of a scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and robustness of a design process and convergence of a test time sequence are improved.

A semiconductor integrated circuit (IC) device is presented that includes a transistor with a gate, a plurality of channels, and a source / drain (S / D) region. A backside contact, that is asymmetric to the S / D region, is in direct contact with a backside of the S / D region. A bottom isolation region is in direct contact with the backside contact and in direct contact with the gate. A bottommost inner spacer is below a bottommost channel of the plurality of channels and in direct contact with the bottom isolation region. The of the bottom isolation region may enable the asymmetry of the backside contact which may lessen routing congestion from the associated backside contact to a backside BEOL network.

The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

A method, a system, and non-transitory computer readable medium for power and ground (P / G) routing for an integrated circuit (IC) design are provided. The method includes generating input features for a machine-learning (ML) model based on IR drop and routing congestion analysis for a P / G network for the IC design, and modifying a set of P / G vias or a set of P / G wires in the P / G network according to modifications identified by the ML model. The ML model comprises a feature extractor pre-trained using a plurality of images of P / G vias and P / G wires.

One or more embodiments of the invention provide an LDPC decoder-oriented soft information processing method and related equipment. The method comprises the following steps: mapping a lifting factor of an input code block to obtain a mapping lifting factor according to the width of an input bus of a decoder and a maximum lifting factor allowed by a communication protocol; according to the mapping lifting factor, the input code block is expanded into a rearrangement code block, and the width of the rearrangement code block is a multiple of the width of the input bus; and storing the rearranged code block into a decoder memory, wherein data only containing the same input code block is stored each time. According to the invention, the data input time delay can be effectively reduced, and the communication transmission efficiency is improved. In addition, the problem of wiring congestion can be effectively relieved.

The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

The invention relates to the technical field of data processing systems, in particular to a logistics warehouse management system based on an intelligent algorithm, and the system comprises a collection module, a preliminary screening module, a first screening module, a second screening module, a final screening module and an adjustment module. Through multi-layer screening and dynamic adjustment, efficient selection and optimization of a storage transportation path are realized, various key parameters such as loading and unloading complexity, order emergency degree, channel blockage rate, obstacle avoidance frequency and deceleration frequency can be comprehensively considered, and conjoint analysis is carried out based on change characteristics of the key parameters in time and space, so that the accuracy of the storage transportation path is improved. The blocking rate and the deceleration frequency always fluctuate synchronously, the loading and unloading complexity and the obstacle avoidance frequency have cooperative influence, and the order emergency degree preferentially drives the path screening sequence. The problems of high route congestion rate and low response speed in a complex and changeable scene due to excessive dependence on static threshold judgment and manual decision are effectively solved.

The application belongs to the technical field of integrated circuits, and discloses a layout method of a programmable logic device. The method comprises the following steps: S10, differentiating circuit networks into first-type networks and second-type networks according to fan-out values of the circuit networks, obtaining loads and driving units of the first-type networks, and obtaining loads of the second-type networks; S20, setting the loads and the driving units into a plurality of groups according to a result of global layout; S30, obtaining weights of the loads and the driving units in each group; and S40, placing the loads and the driving units of each group in turn according to an arbitrary sequence according to the result of the global layout, and determining a placement sequence of the loads and the driving units of each group according to the weights of the loads and the driving units. The layout method provided by the application places loads or driving units of the same circuit network in the same programmable logic unit or in the same row or the same column of the programmable logic unit, thereby reducing wiring congestion between layout resources.

This application relates to a communication management method, apparatus, computer device, and storage medium based on the APB bus. The method includes: receiving an address signal sent by the microcontroller through the APB master interface and determining whether the address signal is valid; in response to the valid address signal, segmenting the address signal using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller; and in response to a control command from the microcontroller, performing read / write operations on the target register through the target APB slave interface. This method enables the selection of the APB slave interface through APB handshake signals and address segmentation, reducing APB bus wiring congestion, lowering the latency of the MCU accessing the APB slave interface, and avoiding access conflicts between multiple APB slave interfaces.

The invention provides a test circuit design method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, and the method comprises the steps: carrying out the layout and wiring according to a gate-level netlist of an integrated circuit, obtaining an initial layout of the integrated circuit, and carrying out the design of a test circuit according to the distribution conditions of functional units and metal wires in the initial layout; according to the method, an initial layout is divided into a plurality of sub-regions, a register of any function unit in the integrated circuit belongs to the same sub-region or different sub-regions, and for each sub-region, an EDT circuit is added to the register belonging to the sub-region in a gate-level netlist. According to the technical scheme, the situation of layout wiring congestion and even conflicts caused by insertion of the EDT circuit can be effectively avoided, so that repeated execution of operations such as layout wiring is avoided, the design efficiency of the test circuit is effectively improved, and the overall design period of an integrated circuit is shortened.

This invention discloses a collaborative method for logic structure partitioning and netlist optimization in multi-core FPGAs, belonging to the fields of electronic design automation and integrated circuits. This invention introduces physical partitioning constraints during the logic synthesis stage, establishing an interconnect-aware synthesis cost function that integrates area, timing, and cross-core interconnect costs. The method includes: pre-partitioning the netlist and anchoring its locations using a hypergraph partitioning algorithm; real-time selection and optimization operators based on dynamically adjusted interconnect penalty coefficients during logic transformation; implementation of suppression mechanisms for high interconnect cost operations; and active logic cloning and topology reconstruction for long-distance cross-core paths. This invention breaks the traditional boundaries between logic synthesis and physical partitioning, effectively reducing the number of cross-core interconnects at the source through closed-loop iteration of micro-optimization and macro-constraints, significantly reducing the risk of wiring congestion, and improving the operating frequency and performance of multi-core FPGA systems.

The present disclosure provides a data processing method, device, electronic device, storage medium and program product, relating to the technical field of chip design, the method comprising: buffering an input valid signal based on a global clock buffer corresponding to a field programmable gate array to obtain a first signal, enabling each module of a data processing device within a first time interval based on the first signal; processing the to-be-processed data based on a data grouping module and a message padding module to obtain first data, and transmitting the first data to an iterative calculation module; performing iterative operation processing on the first data based on each sub-function included in a first function in the iterative calculation module to obtain an output result corresponding to the to-be-processed data. In this way, the path of the input valid signal is optimized by the global clock buffer, which is quickly transmitted to each module of the data processing device, reduces the congestion of wiring, optimizes the timing path, and improves the operating frequency and operation performance.

The application relates to the chip technical field and provides a clock control path timing optimization method, equipment, medium and program product.The method comprises the following steps: according to the physical size and target frequency of a target circuit module, a plurality of registers are inserted on the clock control path of the target circuit module to construct a pipeline chain; the last-stage register of the pipeline chain is fixed at a target position; a clock network is constructed under the premise of maintaining the position of the last-stage register fixed, and in the process of constructing the clock network, timing constraints between clock gate units controlled by the last-stage register are shielded; after the clock network is constructed, physical connection between the clock gate units and the last-stage register is established, and timing optimization is performed on the clock control path between the last-stage register and the clock gate units.The application avoids power consumption surge, wiring congestion and violation risks caused by excessively long paths, and significantly improves the timing convergence rate and resource utilization rate of a high-performance chip in a sign-in stage.

The invention provides a data processing method and device, an electronic device, a storage medium and a program product, and relates to the technical field of chip design, the method comprises the following steps: buffering an input effective signal based on a global clock buffer corresponding to a field programmable gate array to obtain a first signal, enabling each module of the data processing device to start in a first time interval based on the first signal; processing the to-be-processed data based on the data grouping module and the message filling module to obtain first data, and transmitting the first data to an iterative calculation module; and performing iterative operation processing on the first data based on each sub-function included in the first function in the iterative calculation module to obtain an output result corresponding to the to-be-processed data. Therefore, the path for inputting the effective signal is optimized through the global clock buffer, so that the effective signal is quickly transmitted to each module of the data processing device, the wiring congestion is reduced, the time sequence path is optimized, and the operation frequency and the operation performance are improved.

The invention relates to the technical field of layout optimization in integrated circuit physical design, in particular to a staged preview collaborative optimization method for collaborative layout of macro cells and standard cells, and aims to solve the problems of poor collaboration, low overlap repair efficiency and high wiring congestion risk in mixed layout of the macro cells and the standard cells. According to the technical scheme, the method comprises the steps that firstly, a component neighborhood is constructed based on modularity and pairing weight, a neighborhood mode is dynamically switched through a differential evolution operator to generate a rehearsal population, and high-quality individuals are maintained through a double-end queue file; two-stage collaborative optimization is adopted, and adaptability optimization and typed overlap repair (only corresponding types of units are moved) are executed for macro units and standard units; the effect is evaluated through a combined cost function containing a line length and overlapping area weighted item, when any one condition of evaluation budget, overlapping standard reaching or too low improvement rate is met, termination is carried out, and local search optimization is disturbed through a tail end weight at the global optimal position. The layout quality and optimization efficiency can be improved, and the method is suitable for chip back-end layout design, power-assisted balance time sequence performance and wiring feasibility.

The present application relates to the technical field of data processing system, especially to a logistics warehouse management system based on intelligent algorithm, which comprises a collection module, a preliminary screening module, a first screening module, a second screening module, a final screening module and an adjustment module. Through multi-layer screening and dynamic adjustment, the present application realizes efficient selection and optimization of warehouse transportation path, can comprehensively consider multiple key parameters such as loading and unloading complexity, order urgency, channel congestion rate, obstacle avoidance frequency and deceleration frequency, and carry out joint analysis based on their time and space variation characteristics. Congestion rate and deceleration frequency often present synchronous fluctuation, and there is a synergistic effect between loading and unloading complexity and obstacle avoidance frequency, and order urgency preferentially drives path screening sequence, effectively solving the problem of high route congestion rate and low response speed when facing complex and variable scenes due to excessive reliance on static threshold judgment and artificial decision.

The present invention relates to a load capacitance optimization method and system based on dichotomy and dynamic variable control. The method comprises: when performing load capacitance reduction processing on each load capacitance violation signal line, extracting the basic characteristics of the load capacitance of the load capacitance violation signal line, and determining the load capacitance formation characteristics of the load capacitance violation signal line based on the extracted basic characteristics of the load capacitance, selecting a buffer insertion state corresponding to the load capacitance formation characteristics based on the load capacitance formation characteristics of the current load capacitance violation signal line, and performing buffer insertion processing on the current load capacitance violation signal line based on the selected buffer insertion state. The present invention can accurately locate the formation state of large load capacitance, and perform buffer insertion layout according to the formation state of large load capacitance, while reducing the load capacitance, avoiding the risks of timing violations, wiring congestion and excessive power consumption.

The application provides a wiring congestion prediction method and device, equipment and a storage medium, and belongs to the chip design field. The method comprises the following steps: acquiring layout basic data of a chip, wherein the layout basic data comprises pin information, pin network information and wiring resource information; determining the rectangular uniform line density and the total pin wiring line length of each grid unit wiring of the chip according to the pin information and the pin network information; and determining the wiring congestion information of the chip according to the rectangular uniform line density, the total pin wiring line length and the wiring resource information of each grid unit wiring, wherein the wiring congestion information comprises the congestion level of each grid unit. According to the rectangular uniform line density, the total pin wiring line length and the wiring resource information, the wiring congestion information of the chip can be accurately determined.