4 results about "Routing congestion" patented technology

The application discloses a kind of sideband signal communication configuration circuit for on-chip network mounting IP, belong to chip design field, comprising: low-speed protocol communication configuration interface module, AXB sideband communication interface module, on-chip network module.First, the request of reading and writing sideband signal register based on low-speed protocol of external equipment is received, protocol is converted into the request package of on-chip network form, is sent to each routing node by on-chip network module, then utilizes protocol decoding bypass mainband communication interface, enters the AXB sideband communication interface module of current node, connects the configuration bus of IP, controls the reading and writing request of IP sideband signal register, then when reading and writing request succeeds, original road returns reading and writing response to external equipment.The application can effectively improve the wiring congestion of large scale on-chip network, timing bottleneck, increase the bandwidth of data path and configuration path, reduce kernel address occupation, while also beneficial to the rapid expansion integration of on-chip network.

This invention discloses a collaborative method for logic structure partitioning and netlist optimization in multi-core FPGAs, belonging to the fields of electronic design automation and integrated circuits. This invention introduces physical partitioning constraints during the logic synthesis stage, establishing an interconnect-aware synthesis cost function that integrates area, timing, and cross-core interconnect costs. The method includes: pre-partitioning the netlist and anchoring its locations using a hypergraph partitioning algorithm; real-time selection and optimization operators based on dynamically adjusted interconnect penalty coefficients during logic transformation; implementation of suppression mechanisms for high interconnect cost operations; and active logic cloning and topology reconstruction for long-distance cross-core paths. This invention breaks the traditional boundaries between logic synthesis and physical partitioning, effectively reducing the number of cross-core interconnects at the source through closed-loop iteration of micro-optimization and macro-constraints, significantly reducing the risk of wiring congestion, and improving the operating frequency and performance of multi-core FPGA systems.

The application provides a wiring congestion prediction method and device, equipment and a storage medium, and belongs to the chip design field. The method comprises the following steps: acquiring layout basic data of a chip, wherein the layout basic data comprises pin information, pin network information and wiring resource information; determining the rectangular uniform line density and the total pin wiring line length of each grid unit wiring of the chip according to the pin information and the pin network information; and determining the wiring congestion information of the chip according to the rectangular uniform line density, the total pin wiring line length and the wiring resource information of each grid unit wiring, wherein the wiring congestion information comprises the congestion level of each grid unit. According to the rectangular uniform line density, the total pin wiring line length and the wiring resource information, the wiring congestion information of the chip can be accurately determined.