18 results about "Routing congestion" patented technology

The invention discloses a BGA simultaneous escape wiring method based on shared node and combined congestion negotiation, and belongs to the technical field of electronic design automation. The method comprises the following steps: constructing a directed graph representing a wiring space, and determining a starting point and an ending point of each to-be-wired network; adopting a bidirectional Dijkstra algorithm to carry out parallel path search on all the networks; dividing the line network into a single line network and a conflict line network containing shared nodes; the conflicting networks are grouped, so that the networks in the group only share nodes with one another; on the basis of a network quality evaluation model, selecting one network from each group to remove the network, and dynamically updating the cost value of wiring nodes; and iteratively executing the steps of searching, grouping, clearing and cost adjustment until all the wire nets are single wire nets, and outputting a final wiring result. According to the method, wiring congestion can be effectively reduced, path bypassing is avoided, and the success rate, the wiring quality and the algorithm convergence efficiency of BGA packaging and escape wiring are remarkably improved.

The application discloses a kind of sideband signal communication configuration circuit for on-chip network mounting IP, belong to chip design field, comprising: low-speed protocol communication configuration interface module, AXB sideband communication interface module, on-chip network module.First, the request of reading and writing sideband signal register based on low-speed protocol of external equipment is received, protocol is converted into the request package of on-chip network form, is sent to each routing node by on-chip network module, then utilizes protocol decoding bypass mainband communication interface, enters the AXB sideband communication interface module of current node, connects the configuration bus of IP, controls the reading and writing request of IP sideband signal register, then when reading and writing request succeeds, original road returns reading and writing response to external equipment.The application can effectively improve the wiring congestion of large scale on-chip network, timing bottleneck, increase the bandwidth of data path and configuration path, reduce kernel address occupation, while also beneficial to the rapid expansion integration of on-chip network.

The invention discloses a sideband signal communication configuration circuit for a network-on-chip mounting IP, which belongs to the field of chip design and comprises a low-speed protocol communication configuration interface module, an AXB sideband communication interface module and a network-on-chip module. The method comprises the following steps: firstly, receiving a low-speed protocol-based sideband signal register read-write request of external equipment, converting a protocol into a request packet oriented to an on-chip network form, sending the request packet to each routing node through an on-chip network module, decoding a bypass main band communication interface, entering an AXB sideband communication interface module of the current node and connecting a configuration bus of an IP (Internet Protocol) by utilizing the protocol, and finally, carrying out routing on the AXB sideband communication interface module. And a read-write request of the IP sideband signal register is controlled, and then when the read-write request succeeds, a read-write response is returned to the external equipment along the original path. According to the method, the wiring congestion and the time sequence bottleneck when the scale of the network-on-chip is relatively large can be effectively improved, the bandwidths of a data path and a configuration path are increased, the occupation of a kernel address is reduced, and meanwhile, the method is also beneficial to rapid expansion and integration of the network-on-chip.

The application relates to the field of integrated circuit design and test technology, and discloses a scan chain port layout optimization method, device and electronic equipment. The core of the method comprises the following steps: an intelligent nearest matching step of a scan chain port and a scan chain, in which a nearest unassigned scan chain is searched as a candidate by sequentially selecting a scan chain port, and it is judged whether the scan chain is matched according to a preset distance constraint threshold, so that a first matching relationship is established; and a step of performing dynamic port rearrangement on the unassigned ports and scan chains that are not successfully matched to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of the scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and the robustness of the design process and the convergence of the test timing are improved.

The present disclosure relates to multi-path routing of a switch fabric. The switch fabric uses traffic congestion information to inform its timely use of non-minimal routes. An ingress port of a network switch collects traffic congestion information from egress ports of the network switch. The traffic congestion information includes minimal and non-minimal route congestion metrics for the egress ports. Candidate egress ports are identified for forwarding a packet to a destination node. One of the candidate egress ports is selected in accordance with the traffic congestion information. The selection process favors selecting some candidate egress ports over others. In particular, non-minimal routes to the destination node and candidate egress ports having high minimal route congestion metrics are disfavored by the selection process.

The invention relates to the technical field of integrated circuit design and testing, and discloses a scan chain port layout optimization method and device and electronic equipment. The method comprises the following steps: sequentially selecting scan chain ports, searching an unallocated scan chain with the shortest physical distance as a candidate, and judging whether the unallocated scan chain is matched or not according to a preset distance constraint threshold value, so as to establish a first matching relationship; and executing dynamic port rearrangement on the ports which are not successfully matched and the scan chain to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of a scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and robustness of a design process and convergence of a test time sequence are improved.

A semiconductor integrated circuit (IC) device is presented that includes a transistor with a gate, a plurality of channels, and a source / drain (S / D) region. A backside contact, that is asymmetric to the S / D region, is in direct contact with a backside of the S / D region. A bottom isolation region is in direct contact with the backside contact and in direct contact with the gate. A bottommost inner spacer is below a bottommost channel of the plurality of channels and in direct contact with the bottom isolation region. The of the bottom isolation region may enable the asymmetry of the backside contact which may lessen routing congestion from the associated backside contact to a backside BEOL network.

The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

This application relates to a communication management method, apparatus, computer device, and storage medium based on the APB bus. The method includes: receiving an address signal sent by the microcontroller through the APB master interface and determining whether the address signal is valid; in response to the valid address signal, segmenting the address signal using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller; and in response to a control command from the microcontroller, performing read / write operations on the target register through the target APB slave interface. This method enables the selection of the APB slave interface through APB handshake signals and address segmentation, reducing APB bus wiring congestion, lowering the latency of the MCU accessing the APB slave interface, and avoiding access conflicts between multiple APB slave interfaces.

This invention discloses a collaborative method for logic structure partitioning and netlist optimization in multi-core FPGAs, belonging to the fields of electronic design automation and integrated circuits. This invention introduces physical partitioning constraints during the logic synthesis stage, establishing an interconnect-aware synthesis cost function that integrates area, timing, and cross-core interconnect costs. The method includes: pre-partitioning the netlist and anchoring its locations using a hypergraph partitioning algorithm; real-time selection and optimization operators based on dynamically adjusted interconnect penalty coefficients during logic transformation; implementation of suppression mechanisms for high interconnect cost operations; and active logic cloning and topology reconstruction for long-distance cross-core paths. This invention breaks the traditional boundaries between logic synthesis and physical partitioning, effectively reducing the number of cross-core interconnects at the source through closed-loop iteration of micro-optimization and macro-constraints, significantly reducing the risk of wiring congestion, and improving the operating frequency and performance of multi-core FPGA systems.

The present disclosure provides a data processing method, device, electronic device, storage medium and program product, relating to the technical field of chip design, the method comprising: buffering an input valid signal based on a global clock buffer corresponding to a field programmable gate array to obtain a first signal, enabling each module of a data processing device within a first time interval based on the first signal; processing the to-be-processed data based on a data grouping module and a message padding module to obtain first data, and transmitting the first data to an iterative calculation module; performing iterative operation processing on the first data based on each sub-function included in a first function in the iterative calculation module to obtain an output result corresponding to the to-be-processed data. In this way, the path of the input valid signal is optimized by the global clock buffer, which is quickly transmitted to each module of the data processing device, reduces the congestion of wiring, optimizes the timing path, and improves the operating frequency and operation performance.

The application relates to the chip technical field and provides a clock control path timing optimization method, equipment, medium and program product.The method comprises the following steps: according to the physical size and target frequency of a target circuit module, a plurality of registers are inserted on the clock control path of the target circuit module to construct a pipeline chain; the last-stage register of the pipeline chain is fixed at a target position; a clock network is constructed under the premise of maintaining the position of the last-stage register fixed, and in the process of constructing the clock network, timing constraints between clock gate units controlled by the last-stage register are shielded; after the clock network is constructed, physical connection between the clock gate units and the last-stage register is established, and timing optimization is performed on the clock control path between the last-stage register and the clock gate units.The application avoids power consumption surge, wiring congestion and violation risks caused by excessively long paths, and significantly improves the timing convergence rate and resource utilization rate of a high-performance chip in a sign-in stage.

The invention relates to the technical field of layout optimization in integrated circuit physical design, in particular to a staged preview collaborative optimization method for collaborative layout of macro cells and standard cells, and aims to solve the problems of poor collaboration, low overlap repair efficiency and high wiring congestion risk in mixed layout of the macro cells and the standard cells. According to the technical scheme, the method comprises the steps that firstly, a component neighborhood is constructed based on modularity and pairing weight, a neighborhood mode is dynamically switched through a differential evolution operator to generate a rehearsal population, and high-quality individuals are maintained through a double-end queue file; two-stage collaborative optimization is adopted, and adaptability optimization and typed overlap repair (only corresponding types of units are moved) are executed for macro units and standard units; the effect is evaluated through a combined cost function containing a line length and overlapping area weighted item, when any one condition of evaluation budget, overlapping standard reaching or too low improvement rate is met, termination is carried out, and local search optimization is disturbed through a tail end weight at the global optimal position. The layout quality and optimization efficiency can be improved, and the method is suitable for chip back-end layout design, power-assisted balance time sequence performance and wiring feasibility.

The present application relates to the technical field of data processing system, especially to a logistics warehouse management system based on intelligent algorithm, which comprises a collection module, a preliminary screening module, a first screening module, a second screening module, a final screening module and an adjustment module. Through multi-layer screening and dynamic adjustment, the present application realizes efficient selection and optimization of warehouse transportation path, can comprehensively consider multiple key parameters such as loading and unloading complexity, order urgency, channel congestion rate, obstacle avoidance frequency and deceleration frequency, and carry out joint analysis based on their time and space variation characteristics. Congestion rate and deceleration frequency often present synchronous fluctuation, and there is a synergistic effect between loading and unloading complexity and obstacle avoidance frequency, and order urgency preferentially drives path screening sequence, effectively solving the problem of high route congestion rate and low response speed when facing complex and variable scenes due to excessive reliance on static threshold judgment and artificial decision.

The application provides a wiring congestion prediction method and device, equipment and a storage medium, and belongs to the chip design field. The method comprises the following steps: acquiring layout basic data of a chip, wherein the layout basic data comprises pin information, pin network information and wiring resource information; determining the rectangular uniform line density and the total pin wiring line length of each grid unit wiring of the chip according to the pin information and the pin network information; and determining the wiring congestion information of the chip according to the rectangular uniform line density, the total pin wiring line length and the wiring resource information of each grid unit wiring, wherein the wiring congestion information comprises the congestion level of each grid unit. According to the rectangular uniform line density, the total pin wiring line length and the wiring resource information, the wiring congestion information of the chip can be accurately determined.

The application provides a mixed test system, method, electronic equipment and storage medium of a multi-core heterogeneous system-level chip, the mixed test system comprising: a serial control network component, at least one protocol conversion gateway device, a local test distribution network controller and a plurality of data network encapsulators; the protocol conversion gateway device comprising a bus slave interface, a storage buffer unit and a flow control state machine. Through the mixed test system architecture of the serial control network component configuration, the protocol conversion gateway device multiplexing and the local test distribution dedicated network, the inherent contradictions of the prior art in time, cost and contention are cooperatively solved in the multi-core heterogeneous system-level chip, the flexibility and scalability of testing the multi-core heterogeneous system-level chip are improved, the hardware cost and wiring congestion are significantly reduced, the bus contention is eliminated, the test efficiency is improved and the time cost of parallel testing is reduced.

The invention provides a hybrid test system and method for a multi-core heterogeneous system-on-chip, electronic equipment and a storage medium. The hybrid test system comprises a serial control network component, at least one protocol conversion gateway device, a local test distribution network controller and a plurality of data network encapsulators, the protocol conversion gateway device comprises a bus slave interface, a storage buffer unit and a flow control state machine. Through a hybrid test system architecture of serial control network component configuration, protocol conversion gateway device multiplexing and local test distribution private network, inherent contradictions in the aspects of time, overhead and contention in the prior art are collaboratively solved in a multi-core heterogeneous system-on-chip; compared with the prior art, the method has the advantages that the flexibility and expandability of testing the multi-core heterogeneous system-on-chip are improved, the hardware overhead and wiring congestion are remarkably reduced, the bus contention is eliminated, the testing efficiency is improved, and the time overhead of parallel testing is reduced.

The invention belongs to the field of integrated circuit fault-tolerant design, and discloses an interconnection high-efficiency on-chip automatic repair circuit and method based on multidirectional shift, the circuit comprises a repair array formed by function interconnection and redundancy interconnection, the redundancy interconnection is arranged at a diagonal position, and the function interconnection is connected with the redundancy interconnection. And the functional interconnection displaces step by step from the two sides to the central diagonal direction to form a multidirectional repair path. Each interconnection node corresponds to one repair unit and comprises an input module, a signal switching module, a fault state storage module and an output module. According to the repairing method, a bidirectional step-by-step propulsion mode is adopted, repairing requests are initiated to redundant interconnection from the two sides of the array, signal switching and path selection are achieved through combinational logic according to preset priorities, and pipeline parallel processing is supported. According to the method, complete on-chip automatic repair is achieved, the fault aggregation effect is effectively handled, the repair rate and the redundant resource utilization rate are improved, meanwhile, wiring congestion and long-path delay are avoided, and the method is suitable for improving the reliability of the high-performance chip particle integrated chip.