99results about How to "Reduce parasitism" patented technology

This invention relates to a micromachined capacitive microphone having a shallowly corrugated diaphragm that is anchored at one or more locations on the support has a plurality of dimples to support itself and rest freely on the perforated backplate. The diaphragm whose ends are not anchored is bounded by the taps of edge rail. Also disclosed includes: a fixed perforated backplate having one or more regions; an adjustable cantilever formed by the diaphragm, the support and the backplate; a plurality of dimples maintaining vertical separation between diaphragm and backplate; and the patterning of conductor electrodes carried by diaphragm and backplate.

Improved microelectromechanical systems (MEMS), processes and apparatus using thermocompression bonding are disclosed. For example, process embodiments are disclosed in which wafer-scale as well as die-scale thermocompression bonding is utilized to encapsulate MEMS and/or to provide electrical interconnections with MEMS. Apparatus embodiments include apparatus for performing thermocompression bonding and bonded hybrid structures manufactured in accordance with the process embodiments. Devices having various substrate bonding and/or sealing configurations variously offer the advantage of reduced size, higher manufacturing yields, reduced costs, improved reliability, improved compatibility with existing semiconductor manufacturing process and/or greater versatility of applications.

A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.

Structure and method for fabrication of a leadless chip carrier have been disclosed. A disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die. The disclosed embodiment also comprises a printed circuit board attached to a bottom surface of the substrate. The disclosed embodiment further comprises at least one via in the substrate, which provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via also electrically connects a substrate bond pad and the printed circuit board. The substrate bond pad is further connected to the signal bond pad of the semiconductor die by a signal bonding wire. The at least one via further provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.

A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.

A MMIC amplifier is directly connected to the balanced feed points at the aperture of an antenna to eliminate the distance between electronics coupled to the antenna and the antenna itself, such that interfaces, components and connection lines which introduce losses and parasitic effects that degrade system performance are eliminated due the direct connection. Expanding the aperture of the antenna to accommodate the direct connection of a MMIC amplifier to balanced feed points of an antenna has been found to have no deleterious effects on antenna performance. Moreover, when coupling the MMIC amplifier to an unbalanced coaxial line, any associated ripple is minimized due to the direct connection.

The invention discloses a gradually-appoximant analog-digital converter. A capacitor array is integrated in the gradually-appoximant analog-digital converter. The gradually-appoximant analog-digital converter is characterized in that a capacitor of the capacitor array comprises three stages: the highest position to the fifth position of the output end of a first digital signal are set as a first stage; the fourth position and the third position are set as the second stage; the second position and the lowest position are set as the third stage, i.e. the capacitor at the seventh position of a first capacitor is selected as unit capacitor; the mth capacitor higher than the seventh position is formed by connecting 2m-7 unit capacitors in parallel; capacitors at the sixth position and the fifth position are respectively formed by connecting two and four unit capacitors in series; the connecting mode of the second stage and the third stage is the same as the connecting mode at the fifth position and the sixth position; various capacitors at various stages are connected in parallel; and three unit capacitors are connected between two adjacent capacitor arrays in series. By improving a structural mode for connecting the capacitor arrays in grade, the invention can effectively reduce the number of capacitors, reduce the capacitor area and improve the match precision, thereby realizing low power consumption, high matching degree, low parasitism and compromise among low area of the analog-digital converter.

The present invention discloses a duck cultivation method using rice fields. The method comprises the following steps: selecting small and medium-sized ducks with exuberant vitality, wide adaptability and crude feed tolerance; carrying out centralized brooding of ducklings under good breeding management condition; feeding the ducklings with feed until the duck weight reaches 75 g or more; timely dispersing the ducklings to a rice field in an appropriate density in conjunction with rice growth time; and feeding the ducklings with reasonable feed at a specified time point. The duck cultivation method disclosed by the present invention can effectively control the damage of pests in the rice field, promotes ecological balance, controls pesticide pollution, ensures good agricultural environment, promotes rice yield increase, reduces agricultural cost and increases framer income, so that pollution-free and safe rice and duck meat are simultaneously produced in limited space of the rice field.

Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

Reducing, suppressing or canceling series parasitic inductance and/or resistive effects that affect the frequency response of components, elements and/or circuits in an electronic circuit or system that exhibit capacitance is disclosed. Noise generated by series parasitic inductance and/or parasitic resistance of the components, the physical orientation of the components, and/or the layout of components, devices and/or conductive tracks (board traces) on printed circuit boards within an electronic circuit or system is reduced, suppressed or canceled. The reduction, suppression or cancellation is achieved by adding a voltage source in series with a part or component of the electronic circuit or system that exhibits capacitance, the current source being adapted to deliver a compensating voltage of roughly equal magnitude and roughly opposite phase to parasitic voltage associated with the part or component.

A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

The invention discloses a top electrode structure of a bulk acoustic wave resonator and a manufacturing process, and the manufacturing process comprises the steps: preparing a substrate with a cavity,and sequentially manufacturing a bottom electrode layer and a piezoelectric layer, which cover the cavity, on the substrate; manufacturing a dielectric isolation layer on the piezoelectric layer, sothat the dielectric isolation layer covers part of the upper surface of the top of the piezoelectric layer; and manufacturing a top electrode layer on the dielectric isolation layer and the piezoelectric layer, the dielectric isolation layer being covered with the top electrode layer, and at least one side of the top electrode layer extending to the edge of the projection area of the cavity on thepiezoelectric layer. The dielectric isolation layer enhances the mechanical reliability and used for buffering when the stress change of the device layer is increased, and parasitic and reflected transverse waves of radio-frequency signals can be reduced. The mass load layer can form abrupt change of acoustic impedance at the edge of the top electrode layer, increase impedance of the parallel resonator, greatly weaken parasitic resonance, reduce pseudo-resonance and achieve the purpose of improving Q value.