3results about How to "Reduce parasitism" patented technology

The utility model relates to the technical field of plant cultivation, and discloses a parasitic plant aerial fog cultivation, parasitism and collection integrated device which comprises a carrying box, the carrying box is black, three opening and closing doors capable of being independently opened are arranged on the front face of the carrying box from top to bottom, and an aerial fog cultivation layer, a parasitism layer and an atomization layer are sequentially arranged in the carrying box from top to bottom; an illumination assembly is embedded in the top of the aerosol culture layer, and a plant fixing assembly is arranged at the bottom; a parasitic component is embedded in the bottom of the parasitic layer; a nutrient solution storage pool is arranged in the atomization layer, a fogging device is arranged in the nutrient solution storage pool and connected with a timing aerial fog regulator, the nutrient solution storage pool is communicated with a pipeline, and a switch valve is arranged at the tail end of the pipeline.

This invention provides a coupler and an RF front-end module. The coupler includes a substrate and input waveguides, switching waveguides, coupling waveguides, isolation waveguides, transition waveguides, and output port lines formed on the substrate. The substrate includes a high-resistivity silicon substrate, an oxide buried insulating layer, a first metal layer, a second metal layer, and a third metal layer stacked sequentially. The input waveguides, coupling waveguides, isolation waveguides, and output port lines are spaced apart and formed on the third metal layer, while the switching waveguides and transition waveguides are spaced apart and formed on the second metal layer. This invention enables the coupler to have low parasitics, high narrowband, stable sampling, and low power consumption.

The present application relates to a successive approximation ADC, chip and analog-to-digital conversion method based on common-mode voltage. The method includes: a DAC capacitor array; the DAC capacitor array includes a positive capacitor array, a negative capacitor array, a random number generator and a common-mode voltage generating circuit, the upper plates of each capacitor in the positive capacitor array and the negative capacitor array are connected in parallel and connected to the common-mode voltage generating circuit; the positive capacitor array and the negative capacitor array include a high-order capacitor array and a low-order capacitor array, the high-order capacitor array includes a number of thermometer-weighted high-order capacitors, the low-order capacitor array includes a number of binary-weighted low-order capacitors, and the high-order capacitor array is connected to the random number generator; the lower plates of the high-order capacitor and the low-order capacitor are respectively connected to the reference voltage, the differential input voltage or the ground through a three-way gate switch. The use of this method can reduce the power consumption of the SAR ADC and reduce the impact of mismatch.