Top electrode structure of bulk acoustic wave resonator and manufacturing process
A bulk acoustic wave resonator and manufacturing process technology, applied to electrical components, impedance networks, etc., can solve problems such as adverse effects of shear waves
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Embodiment 1
[0056] like Figure 4 As shown, S2 includes the following sub-steps:
[0057] S21, making a mask 8 on the piezoelectric layer 3 in a region where the dielectric isolation layer 5 does not need to be arranged;
[0058] S22, making a dielectric isolation layer 5 through spin coating, exposure and development processes; and
[0059] S23 , removing the mask 8 .
[0060] In a specific example, such as Figures 2e-2g As shown, the mask 8 is made by CVD, photolithography and etching processes, wherein the material of the mask 8 is SiO 2 . The mask 8 is made on the piezoelectric layer 3 in the area where the dielectric isolation layer 5 does not need to be arranged. On this basis, the dielectric isolation layer 5 is fabricated by spin coating, exposure and development processes, and then the dielectric isolation layer 5 is baked to cure the dielectric isolation layer 5 . In a preferred embodiment, the material of the dielectric isolation layer 5 includes PI, and the baking tempe...
Embodiment 2
[0064] After making the dielectric isolation layer 5 and removing the mask 8 in S22 and S23 in Embodiment 1, as Figure 2k As shown, a second mask 10 is formed on the dielectric isolation layer 5 to protect the dielectric isolation layer 5 . The function of the second mask 10 is to ensure the stability of the dielectric isolation layer 5 . In a preferred embodiment, the material of the second mask 10 is SiO 2 , with a thickness of 10-20nm. The specific thickness of the second mask 10 can be adjusted according to device processing conditions and device requirements. In a preferred embodiment, after the dielectric isolation layer 5 is cured, the height of the upper surface of the dielectric isolation layer 5 is lower than the upper surface of the piezoelectric layer 3 . At this time, after the second mask 10 is made on the dielectric isolation layer 5, the upper surface of the second mask 10 is almost at the same level as the upper surface of the piezoelectric layer 3, and th...
Embodiment 3
[0066] like Figure 2m-2q As shown, on the basis of step S1, the manufacturing process of the dielectric isolation layer 5 is changed, and step S2 may specifically include the following sub-steps:
[0067] making a mask 8 on the piezoelectric layer 3;
[0068] Fabricate a dielectric isolation layer 5 on the mask 8 by spin coating, exposure and development processes; and
[0069] The mask 8 is removed from the regions where the dielectric isolation layer 5 is not applied by an etching process.
[0070] In a specific embodiment, a mask 8 is formed on the piezoelectric layer 3 by a CVD process, wherein the material of the mask 8 includes SiO 2 , the thickness of the mask 8 is 10-20nm. The specific thickness of the mask 8 can be adjusted according to device processing conditions and device requirements. At this time, the function of the mask 8 is to protect the material of the piezoelectric layer 3 from being corroded by the developing solution. The dielectric isolation layer...
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