289 results about "Dielectric isolation" patented technology

Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.

A method for forming a semiconductor device structure is provided. The method includes providing a substrate and a nanostructure stack. The method includes forming a first gate stack and a second gate stack wrapped around the nanostructure stack. The method includes forming a first source / drain structure in the nanostructure stack and between the first gate stack and the second gate stack. The method includes removing the second gate stack, the nanostructure stack and the fin under the second gate stack to form a trench passing through the nanostructure stack and the fin. The method includes forming a dielectric isolation structure in the trench. The method includes removing the first gate stack and the first nanostructure. The method includes forming a third gate stack wrapped around the second nanostructure. The method includes forming a first contact structure over the first source / drain structure.

A semiconductor device is provided that includes a multilayered insulator region located between stacked FETs. The multilayered insulator region is referred to herein as a multi-dielectric material middle isolation structure. The multi-dielectric material middle isolation structure includes a middle dielectric isolation structure having a middle dielectric isolation spacer located at two opposing ends of, or surrounding, the middle dielectric isolation structure. The middle dielectric isolation spacer protects the middle dielectric isolation structure during processing of the stacked FETs such that no damage to the middle dielectric isolation structure and the semiconductor channel regions of the stacked FETs is observed.

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for controlling electric leakage between a parasitic channel and a source / drain region and improving the electrical performance of the gate-all-around transistor. The ring gate transistor comprises a semiconductor substrate, an active structure, a gate stack structure and a dielectric isolation structure. The active structure is disposed on the semiconductor substrate. The active structure comprises source / drain regions and a channel region located between the source / drain regions. The channel region includes at least one layer of nanostructure disposed over the semiconductor substrate. And the gate stack structure surrounds the periphery of each layer of nano structure. The dielectric isolation structure is arranged between the source / drain region and the semiconductor substrate, and the dielectric isolation structure extends to the part between the gate stack structure and the semiconductor substrate along the distribution direction of the source / drain region. The manufacturing method of the gate-all-around transistor is used for manufacturing the gate-all-around transistor.

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

The invention discloses a metasurface structure for realizing terahertz up-conversion luminescence, and belongs to the technical field of optics, the metasurface structure comprises a silicon dioxide substrate, a metal microstructure unit and a quantum dot luminescent material, and is innovatively provided with a dielectric isolation layer and a surface plasma enhancement layer, the dielectric isolation layer reduces the quenching effect of metal on quantum dots, and the surface plasma enhancement layer enhances the surface plasma on the quantum dots. The surface plasma enhancement layer enhances a local electric field. The metasurface structure for realizing terahertz up-conversion luminescence can effectively improve the terahertz visible light up-conversion efficiency, realizes high-sensitivity and quick-response terahertz detection at room temperature, improves the detection sensitivity, simplifies a detection system, has a wide application prospect in the fields of biomedicine, security inspection, communication and the like, and has a wide application prospect in the fields of biomedicine, security inspection, communication and the like. And the practical application development of the terahertz technology is promoted.

An antenna assembly, which includes one or more radiating element arrays and at least one dielectric isolator for the one or more radiating element arrays, wherein, the dielectric isolator is configured to tune the phase of a coupling signal between the radiating elements so as to at least partially eliminate coupling interference between the radiating elements. As a result, the radiation pattern of the antenna can be improved. The present disclosure also provides a base station antenna having the antenna assembly.

The invention discloses a terahertz metasurface capable of realizing independent control of amplitude and phase. The terahertz metasurface comprises a terahertz transparent substrate; the metasurface unit array is periodically arranged in a first direction, and each metasurface unit comprises a first structural layer which is of a dielectric resonance structure and is used for providing a phase regulation and control function; the second structural layer is a thin film formed by an adjustable absorption material and is used for providing an amplitude regulation and control function; the second structure layer is provided with an independent electrode for adjusting the transmission amplitude; a first dielectric isolation layer is arranged between the terahertz transparent substrate and the first structure layer and is used for reducing an electromagnetic coupling effect; the first structural layer and the second structural layer are stacked in the vertical direction through a three-dimensional processing technology, a second dielectric isolation layer is arranged between the first structural layer and the second structural layer, and the second dielectric isolation layer is a silicon dioxide SiO2 or silicon nitride Si3N4 film with the thickness D ranging from 100nm to 1000nm.

A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

According to the monolithic integrated MEMS micro differential pressure chip, a plurality of first injection regions (10), a second injection region (11), an all-dielectric isolation structure (6), a collector region (8), a base region (9), an emitter region (7) and a buried layer (1) are arranged on a first SOI silicon wafer, and correspondingly matched metal leads (13) are arranged on the second injection region (11), the collector region (8), the base region (9) and the emitter region (7). A second double-parabolic silicon wafer (5) is connected to the first SOI silicon wafer, and the monolithic integrated MEMS micro differential pressure chip is prepared through photoetching, injection, annealing, etching, film forming and sputtering processes. The invention has the advantages of simple structure, convenience in preparation and the like, and provides an efficient and economical solution for manufacturing a high-performance and high-reliability MEMS pressure chip.

A method includes forming a plurality of semiconductor regions, forming a plurality of gate stacks, wherein the plurality of gate stacks are on first portions of the plurality of semiconductor regions, and etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks. The plurality of openings include a first opening in a first gate stack, and a second opening in a second gate stack. The first opening and the second opening are immediately neighboring each other and have an overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. The plurality of semiconductor regions are etched to extend the plurality of openings downwardly to be between dielectric isolation regions, followed by filling the plurality of openings to form fin isolation regions. The gate isolations are spaced part from the fin isolation regions.

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to suppress parasitic channel electric leakage and improve the working performance of the gate-all-around transistor. The ring gate transistor comprises a semiconductor substrate, an active structure, a gate stack structure, an inner side wall and a dielectric isolation structure. The active structure is disposed on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region located between the source region and the drain region, and the two ends, in the length direction, of the channel region make contact with the source region and the drain region respectively. The gate stack structure surrounds the periphery of the channel region. The inner side walls are arranged between the gate stack structure and the source region and between the gate stack structure and the drain region. And the dielectric isolation structure is arranged below the active structure and is used for isolating the semiconductor substrate from the source region, the drain region and part of the gate stack structure. At least the part, located below the channel region, in the dielectric isolation structure is integrally continuous with the inner side wall located at the bottom layer. The manufacturing method of the gate-all-around transistor is used for manufacturing the gate-all-around transistor.

The invention belongs to the technical field of frequency selective surface radomes, and particularly relates to a frequency selective surface-based low-frequency wave-transparent and high-frequency reflection device and a satellite radome, which sequentially comprise a first low-pass layer, a first dielectric isolation layer, a first band-stop layer, a second dielectric isolation layer and a second low-pass layer from top to bottom, the first low-pass layer and the second low-pass layer are the same in structure, and each of the first low-pass layer and the second low-pass layer comprises first metal patch patterns which are periodically arranged; each first metal patch pattern is composed of four square ring patterns and a cross-shaped pattern, and the four ends of the cross-shaped pattern are connected with the four square ring patterns respectively; and the first band stop layer comprises second metal patch patterns which are periodically arranged. The novel low-pass layer / band-stop layer pattern multilayer structure is constructed, the effects of ultra-wideband low-frequency wave transmission and high-frequency reflection are achieved under the condition that the thickness is sacrificed, the problem that in-band ultra-wideband wave transmission and out-of-band ultra-wideband reflection are difficult to give consideration to in-band ultra-wideband wave transmission and out-of-band ultra-wideband reflection at the same time in existing frequency selection is effectively solved, and then normal work of a satellite antenna housing is guaranteed.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

A semiconductor structure includes a backside gate extension extending from a frontside gate region through a dielectric isolation layer, a backside gate contact partially disposed on the backside gate extension, and a backside interconnect connected to the backside gate extension by the backside gate contact.

A method includes forming a metal post over a first redistribution structure; attaching a first device die to the first redistribution structure, the first device die comprising a through via embedded in a semiconductor substrate; encapsulating the metal post and the first device die in an encapsulant, a first top surface of the encapsulant being level with a second top surface of the semiconductor substrate; recessing the second top surface to expose the through via; forming a dielectric isolation layer around the through via; forming a dielectric layer over the dielectric isolation layer; etching the dielectric layer to form a first opening and a second opening in the dielectric layer; forming a first metal via in the first opening and a second metal via in the second opening; and forming a second redistribution structure over the dielectric layer.

A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.

A semiconductor structure includes a first set of vertically stacked contacts, a second set of vertically stacked contacts, a first set of stacked transistor devices associated with the first set of vertically stacked contacts, and a second set of stacked transistor devices associated with the second set of vertically stacked contacts. The second set of stacked transistor devices is adjacent to the first set of stacked transistor devices, and a dielectric isolation pillar is disposed between the first set of vertically stacked contacts and the second set of vertically stacked contacts.

The invention provides an improved trench super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) which comprises an epitaxial N-type substrate layer, P columns, N columns, an interlayer insulating layer, a body region, a source region, a metal layer, grid polycrystalline silicon, a grid oxide dielectric layer and a dielectric isolation layer, wherein the P columns and the N columns are arranged on the epitaxial N-type substrate layer in a staggered manner; the grid polycrystalline silicon, the grid oxide dielectric layer and the dielectric isolation layer are arranged on the source region; and the P column is a combined P column formed by a P-type layer formed by deep trench injection and P-type epitaxial filling. According to the improved groove super-junction MOSFET provided by the invention, the mixed P column is formed by the bottom formed by injection and the P layer formed on the side wall and the subsequently filled P epitaxial layer, and the P column and the original N-type epitaxial layer form the PN junction, so that the original PN junction is reserved, the advantage that the groove is easy to fill is combined, the product stability is greatly weakened by the factors of process fluctuation, and the product quality is improved. The method is suitable for large-scale production of a production line, and the product cost performance is high.

The invention discloses a multi-layer resistive film frequency selective surface composite wave-absorbing device with high bearing and wave-absorbing integrated functional characteristics. The composite wave absorbing device sequentially comprises a mechanical bearing layer composed of a wave-transparent dielectric plate subjected to impedance modification and a dielectric isolation layer from top to bottom. The wave-absorbing functional layer is formed by arranging three layers of resistive film frequency selective surfaces, three layers of dielectric isolation layers and six layers of wave-transparent dielectric plates at intervals; and the total reflection bottom plate is formed by a carbon fiber plate or a metal plate. According to the invention, a layer of resistive film frequency selective surface is embedded in the wave-transparent dielectric plate, so that the wave-absorbing bandwidth can be effectively expanded while the high-bearing mechanical property is ensured; a layer of wave-transparent dielectric plate is laid on the upper portion and the lower portion of the frequency selective surface of each resistive film in the wave-absorbing functional layer so as to further reinforce the mechanical bearing characteristic of the composite wave-absorbing device.

A semiconductor device includes a dielectric isolation bar disposed in a region between an n-type active region and a p-type active region. The dielectric isolation bar has a first tapered portion disposed within a contact where the contact connects to the n-type active region or the p-type active region and a second tapered portion that cuts through portions of a buried power rail layer, wherein the dielectric isolation bar electrically isolates a lateral portion of the contact from surrounding structures and separates portions of the buried power rail layer.

The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is on top of the first transistor. The second gate is electrically coupled to the second transistor. A dielectric isolation layer is between the first gate and the second gate. The first conductive contact is electrically coupled to the first gate. The second conductive contact is electrically coupled to the second gate. Control of the first gate through the first conductive contact is independent of control of the second gate through the second conductive contact.

The invention provides a field effect transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a bottom dielectric isolation layer at the bottom of the field effect transistor by adopting a mode of bonding a first bonding layer and a second bonding layer; the top source electrode, the top drain electrode, the top channel structure, the bottom source electrode, the bottom drain electrode and the bottom channel structure are arranged on one side of the bottom dielectric isolation layer, an intermediate dielectric layer is arranged between the top channel structure and the bottom channel structure, the top channel structure and the bottom channel structure comprise laminated layers formed by a plurality of nanosheets, and the grid electrode surrounds the nanosheets. The insulating medium located at the bottom of the channel structure is formed in the mode that the first bonding layer and the second bonding layer are bonded, the middle medium layer serves as the insulating medium between the top channel structure and the bottom channel structure, the problem of substrate parasitic electric leakage of the field effect transistor under a short channel is solved, and the performance of the field effect transistor is improved.

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers. The alternating stacks are laterally spaced apart among one another by backside isolation assemblies. At least one of the backside isolation assemblies generally extends along a first horizontal direction with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction. At least one of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction. Memory stack structures vertically extend through a respective one of the alternating stacks. Each of the backside isolation assemblies includes a respective laterally alternating sequence of backside dielectric isolation walls and backside dielectric support pillar structures.

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

The invention provides a multichannel electromyographic strain bimodal electronic skin and a neural signal decomposition method, and belongs to the technical field of sensors. The multi-channel electromyographic strain bimodal electronic skin comprises six layers of composite structures, and the six layers of composite structures are a stretchable flexible substrate layer, a multi-channel strain sensing layer, a dielectric isolation layer, a stretchable circuit, a multi-channel electromyographic sensing layer and a viscous packaging layer in sequence. The device has the flexible stretchable characteristic, reliable contact between the electronic skin and the skin can be guaranteed during large-amplitude motion, dual-mode detection of human body electromyographic signal-resistance type stress changes can be achieved, a motion-artifact-free fusion signal processing algorithm based on multi-channel dual-mode signals is further provided, and multi-mode fusion signals without motion artifacts are obtained.

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

The invention relates to a preparation method of a piezoresistive high-temperature pressure sensor based on a TSV (Through Silicon Via) of a silicon column. The preparation method comprises the following steps: 1, preparing an annular isolation groove filled with polycrystalline silicon on a low-resistance double-parabolic silicon wafer; 2, preparing a TSV silicon column and a bonding boss on the double-polished silicon wafer; 3, preparing a P-type voltage dependent resistor and an inner lead on the top layer silicon of the SOI silicon wafer; 4, preparing a closed annular groove at the periphery of the SOI silicon wafer, and preparing a semi-closed annular groove at the corresponding position of the TSV silicon column; 5, aligning and bonding the double-polished silicon wafer and the SOI silicon wafer; 6, preparing a TSV cap layer metal electrode from the bonded P-type double-polished silicon wafer; and 7, preparing a pressure sensitive film structure on the lower surface of the bonded SOI silicon wafer. The high-temperature pressure sensor has the beneficial effects that the TSV silicon column process, the dielectric isolation piezoresistive process and the thermal expansion buffer tank process suitable for the high-temperature working environment form an all-silicon structure of the high-temperature pressure sensor, the thermal stress matching is good, and the influence of high-temperature stress on the device performance can be effectively reduced.

A semiconductor structure that includes the top field-effect transistor (FET) on a portion of the bottom FET. The semiconductor structure includes the middle dielectric isolation where the middle dielectric isolation is over the top surface of the gate of the bottom FET. The isolation layer connects the sidewalls of adjacent portions of the middle dielectric isolation. The isolation layer vertically separates one or more top source / drains of the top FET from one or more bottom source / drains of the bottom FET. A first air gap is over the middle portion of the bottom source / drain and between the middle portion of the bottom source / drain and the middle portion of the isolation. A second air gap is below the middle portion of the top source / drain and between the middle portion of the top source / drain and the middle portion of the isolation layer.