99 results about "Dielectric isolation" patented technology

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

A semiconductor structure includes a first set of vertically stacked contacts, a second set of vertically stacked contacts, a first set of stacked transistor devices associated with the first set of vertically stacked contacts, and a second set of stacked transistor devices associated with the second set of vertically stacked contacts. The second set of stacked transistor devices is adjacent to the first set of stacked transistor devices, and a dielectric isolation pillar is disposed between the first set of vertically stacked contacts and the second set of vertically stacked contacts.

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

The invention discloses a stretch-resistant bending-resistant cable and temperature control type production equipment thereof, and relates to the technical field of stretch-resistant bending-resistant cables and temperature control type production equipment thereof.The cable is segmented in the axial direction, a pixelated heating ring belt base body is arranged outside a main conductor bundle in each segment, a fan-shaped cavity is formed in the base body, and Bi-Sn arc segment pixels are embedded in the fan-shaped cavity; the two layers of flexible printed electrode sleeves form an A-layer axial bus and a B-layer axial bus, the A-layer axial bus and the B-layer axial bus are connected with the arc section only in the section in a penetrating welding hole mode, and no middle hole exists outside the section and electrical interruption is achieved. And the dielectric isolation film realizes interlayer insulation. And the gating target section and the angle belt are connected in parallel for heating, so that the Bi-Sn is subjected to phase change softening and then is cured for shape locking, and local thermal shaping and peak clipping stress are completed. And an elastic encapsulating layer, a mechanical bearing and balancing base layer and a temperature bar code residual stress sheath are coated outside, and are matched with weaving and an outer sheath to prolong the fatigue life. The production equipment comprises an extrusion station, an embedding station, a rolling and welding station, a bar code writing station, an online detection station and a take-up section cutting station, and machine vision alignment ensures in-section conduction and inter-section isolation.

Provided is a semiconductor device. The semiconductor device includes: a semiconductor substrate, a first gate-all-around transistor, a second gate-all-around transistor, an insulation layer, and first and second dielectric isolation layers. The insulation layer is arranged between a source / drain region of the first gate-all-around transistor and a source / drain region of the second gate-all-around transistor. The first dielectric isolation layers and the second dielectric isolation layers are alternately stacked between a channel region of the first gate-all-around transistor and a channel region of the second gate-all-around transistor. A gate stack structure of the first gate-all-around transistor and / or a gate stack structure of the second gate-all-around transistor is located at a periphery of alternately stacked first and second dielectric isolation layers. Film layers located at bottom and top layers in alternately stacked first and second dielectric isolation layers are both first dielectric isolation layer.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

A deep trench structure may be formed to include a doped polysilicon core and dielectric isolation layers on the sidewalls of the doped polysilicon core. The deep trench structure may be provided as a deep trench isolation structure that laterally surrounds transistors in a semiconductor device. Additionally and / or alternatively, the deep trench structure may be included in a high-voltage transistor as a vertical drain region that extends into a semiconductor layer of a semiconductor device.

The invention discloses a laser resonant cavity based on distributed resonance feedback and a laser. The laser resonant cavity comprises a gain material layer; the first coating buffer layer is arranged above the gain material layer, a first contact layer is arranged above the first coating buffer layer, the first coating buffer layer is etched to form a waveguide ridge with the middle protruding, dielectric isolation layers are arranged on the surface layers of etching remaining areas on the two sides of the waveguide ridge, and the top surfaces of the dielectric isolation layers are planes; a first metal electrode is arranged above the first contact layer; the second coating buffer layer is arranged below the gain material layer, and a second contact layer is arranged below the second coating buffer layer; a second metal electrode is arranged below the second contact layer; and the periodic local resonance array layer is arranged around the gain material layer. According to the invention, a laser design scheme with narrow linewidth, low threshold, high output power and stable single-frequency characteristics can be realized, and external echoes are immune.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

The application discloses a P epitaxial BCD-on-SOI integration technology and a complementary bipolar transistor device. The integration steps are as follows: forming a DTI deep trench isolation region; forming an N-type side well N+ of an external collector region of a DTI deep trench full isolation NPN transistor on an insulating layer silicon; forming a P-type side well P+ of an external collector region of a DTI deep trench full isolation longitudinal PNP transistor on an insulating layer silicon; forming a complementary NPN-PNP bipolar transistor structure; completing device-metal interlayer planarization; completing a through-hole tungsten plug structure processing; sputtering an aluminum copper film layer and completing metal wire etching processing. The device comprises a P-type base silicon wafer, an N-type buried layer, a P-type buried layer, an insulating silicon dioxide buried layer, a P-type device layer, a dielectric isolation groove region, an N-type epitaxial layer, a P-type epitaxial layer, an N-type side well injection region, a P-type side well injection region, a gate dielectric layer, a polycrystalline thin film, an oxide thin film, a tungsten plug and a metal thin film layer. The application improves the speed and precision of a high-performance circuit of a P epitaxial BCD-on-SOI process.

The method includes: forming a fin above a substrate, the fin including a lower nanostructure, an upper nanostructure, a pseudo-nanostructure, and a dielectric isolation layer disposed between the lower and upper nanostructures; forming a source / drain region adjacent to the fin; forming a groove laterally adjacent to the fin; removing the pseudo-nanostructure from the fin; forming a gate dielectric around the lower and upper nanostructures; dispensing a directional self-assembly (DSA) material into the groove; exposing the DSA material to a selected environment, wherein the polymer molecules of the DSA material are substantially aligned in the groove; performing a curing process on the lower portion of the DSA material; performing a first etching process to remove the uncured upper portion of the DSA material; doping a dipole dopant into the upper gate dielectric; and forming a gate electrode around the lower and upper nanostructures. Embodiments of this application also relate to methods for forming semiconductor structures.

The invention provides a dielectric isolation limiting device, which comprises a dielectric shielding body, the dielectric shielding body is a plate-shaped entity with a predetermined geometric extension surface, and the dielectric shielding body defines a first surface and a second surface which are arranged back to back; the first surface and the second surface are both provided with positioning protrusions, and the positioning protrusions on the two sides are coaxially and correspondingly arranged on the dielectric shielding body. In the application of a circuit breaker, the devices arranged in pairs are embedded into shell positioning holes through bulges on one sides to realize outer side anchoring, and bulges on the other sides extend into the inner side of a static contact arc striking angle and are propped against each other to form a rigid mechanical supporting structure crossing a contact area. The structure stability, the electrical insulation performance and the arc extinguishing efficiency of the circuit breaker under the high breaking working condition are remarkably improved.

This invention discloses a complete set of high-current, wide-power-range, all-dielectric-isolated BCD-on-SOI integrated technology and ESD-protected VDMOS devices. The integration steps are as follows: 1) Forming an N-type buried layer and a P-type buried layer on the surface of the substrate silicon wafer. 2) Forming a DTI deep trench isolation region. 3) Forming a vertical DMOS drain-side-well N+-N-type buried layer interconnect structure. 4) Forming an insulating silicon top-side-well P+-P-type buried layer interconnect structure. 5) Forming an ESD-protected vertical DMOS device structure. 6) Completing the planarization of the device-metal inter-dielectric layer. 7) Completing the through-hole tungsten plug structure fabrication. 8) Sputtering aluminum-copper film layers and completing the metal interconnect etching process. The device includes a P-type substrate silicon wafer, an N-type buried layer, a P-type buried layer, an insulating silicon dioxide buried layer, a P-type device layer, a dielectric isolation trench region, an N-type epitaxial layer, a P-type epitaxial layer, a gate dielectric layer, a polycrystalline thin film, an oxide thin film, a tungsten plug, and a metal thin film layer. This invention solves the integration problem of high-current vertical DMOS with BCD-on-SOI process, as well as the challenge of high-density standard device integration, thereby improving the circuit reliability of the process.

The application relates to the technical field of semiconductor and MEMS devices, in particular to a monolithic integration method of dielectric isolation bipolar IC and piezoresistive MEMS devices. A buried layer of a bipolar IC circuit is prepared on the upper surface of a second silicon base; then a single crystal silicon epitaxial layer is grown on the upper surface of the second silicon base; a circuit function area (including an NPN area and a PNP area) is prepared on the single crystal silicon epitaxial layer corresponding to the area of the bipolar IC circuit; an isolation groove penetrating through the single crystal silicon epitaxial layer and the second silicon base is formed by adopting an etching process, so that the NPN area and the PNP area in the bipolar IC circuit form isolated islands respectively; polycrystalline silicon is used to fill the isolation groove; a piezoresistor is prepared on the upper surface of the single crystal silicon epitaxial layer, and metal wires connecting the NPN area, the PNP area and the piezoresistor are prepared respectively. The application overcomes the problems of device thickness and stress mismatch, conflict of material resistivity requirements, and metal pollution control difficulty faced by IC-MEMS preparation.

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET). includes forming a bottom source / drain (S / D) recess through fin-shaped columns from a top S / D recess into a substrate, wherein each of the fin-shaped columns comprises a bottom high germanium (Ge) layer on the substrate and a stack of alternating channel layers and sacrificial layers over the bottom high Ge layer, forming an S / D epitaxial (epi) layer within the bottom S / D recess, selectively removing the bottom high Ge layer to the sacrificial layers, and forming a bottom cavity between the substrate and the stack of alternating channel layers and sacrificial layers, and forming a bottom dielectric layer in the bottom cavity.

A semiconductor structure includes a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions; and a gate adjacent the at least one channel region. A bottom dielectric isolation region is located inward of the gate. First and second bottom silicon regions are respectively located inward of the first and second source-drain regions. A back side contact projects through the second bottom silicon region into the second source-drain region.

A three-dimensional stacked field-effect transistor including a silicon substrate; a partial bottom dielectric isolation layer on the silicon substrate; a punch through stopper layer on the silicon substrate and on opposite sides of the partial bottom dielectric isolation layer; a first transistor on the partial bottom dielectric isolation layer and the punch through stopper layer; and a second transistor stacked on the first transistor. Each of the first transistor and the second transistor includes a channel, a source region on one side of the channel, and a drain region on another side of the channel. The partial bottom dielectric isolation layer is below the channel of the first transistor. The punch through stopper layer is below the source region and the drain region of the first transistor.

The present disclosure provides an integrated circuit structure and a method of fabricating the same. The dielectric isolation structure can reduce capacitive coupling and crosstalk between conductive features. The method includes forming a first conductive structure on a substrate; forming a first dielectric structure on the first conductive structure; converting sidewall portions of the first conductive structure into a first dielectric portion; removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure; forming an interlayer dielectric (ILD) layer such that sidewalls of the first dielectric structure are covered by the ILD layer; forming a strengthening column in the ILD layer, the strengthening column being removable by energy; forming a capping dielectric layer on the strengthening column; and performing a thermal treatment process to convert the strengthening column into a dielectric isolation structure having a spacer layer surrounding an air gap.

A semiconductor device includes a first field effect transistor stacked on a second field effect transistor. The first field effect transistor has a metallic source / drain region. A second source / drain region of the second field effect transistor is separated from the metallic source / drain region by a middle dielectric isolation layer. A through contact passes through the middle dielectric isolation layer to connect the metallic source / drain region to the second source / drain region.

The invention discloses a semiconductor structure and a forming method thereof. The drift region is located in the substrate; the body region is located in the substrate on one side of the drift region; the channel gate part is located at the tops of the body region and part of the drift region; the source electrode is located in the body region on one side of the channel grid electrode part, and the top surface of the source electrode is exposed out of the body region; the drain electrode is located in the drift region on the other side of the channel gate part, and the drain electrode and the channel gate part are spaced; the first dielectric isolation structure is located in a drift region where the drain electrode and the channel grid electrode part are spaced; the one or more layers of second dielectric isolation structures are located in the drift region at the bottom of the first dielectric isolation structure, and the second dielectric isolation structures are provided with non-straight interface contours in the direction parallel to the channel grid electrode part; and the field plate gate part is located at the top of the first dielectric isolation structure, and the field plate gate part is spaced from the channel gate part. The breakdown voltage of the semiconductor structure can be increased, and meanwhile the device frequency of the semiconductor structure is remarkably improved.

The invention relates to the technical field of semiconductors and MEMS devices, in particular to a monolithic integration method of a dielectric isolation bipolar IC and a piezoresistive MEMS device. A bipolar IC circuit buried layer is prepared on the upper surface of a second silicon substrate; growing a monocrystalline silicon epitaxial layer on the upper surface of the second silicon substrate; preparing a circuit functional region (including an NPN region and a PNP region) in a region corresponding to the bipolar IC circuit on the monocrystalline silicon epitaxial layer; an isolation groove penetrating through the monocrystalline silicon epitaxial layer and the second silicon substrate is formed by adopting an etching process, so that an NPN region and a PNP region in the bipolar IC circuit respectively form isolation islands; filling the isolation groove with polycrystalline silicon; and preparing a piezoresistor and metal wires respectively connected with the NPN region, the PNP region and the piezoresistor on the upper surface of the monocrystalline silicon epitaxial layer. According to the invention, the problems of mismatch of device thickness and stress, conflict of material resistivity requirements, difficulty in metal pollution control and the like in IC-MEMS preparation are solved.

A stacked field effect transistor structure includes a lower field effect transistor with a lower first drain-source region, a lower second drain-source region, and at least one lower nanosheet channel region interconnecting the lower drain-source regions. An upper field effect transistor has an upper first drain-source region, an upper second drain-source region, and at least one upper nanosheet channel region interconnecting the upper drain-source regions. A high-K metal gate structure surrounds at least a portion of the lower and upper nanosheet channel regions. A middle dielectric isolation region separates the upper and lower field effect transistors. Gate spacers are on sides of the gate structure, which includes gate metal, and high-K liner material on the lower and upper nanosheet channel regions, and in a first wall region extending up the gate spacers next to the lower field effect transistor no further than the middle dielectric isolation region.

A vertically stacked 3D nanosheet field effect transistor component includes a bottom nanosheet device, a middle dielectric isolation region coupled to the bottom nanosheet device, and a top nanosheet device coupled to the middle dielectric isolation region. The middle dielectric isolation region can include at least one embedded stressor mechanically coupled to at least one of the bottom nanosheet device and the top nanosheet device that imparts an embedded stressor originated stress in at least one of the bottom nanosheet device and the top nanosheet device. At least one of the bottom nanosheet device and the top nanosheet device include at least one interlayer originated stress. The stress(es) impart device performance boost(s) for at least one of the bottom nanosheet device and the top nanosheet device.

The invention discloses a multi-stage multi-branch differential broadband power divider based on polyimide support bridges. The power divider comprises a differential signal input unit, a plurality of differential signal output units, a multi-stage multi-branch differential impedance conversion unit and a plurality of polyimide support bridge structures, the differential signal input unit comprises an input differential pair, and the differential signal output unit comprises multiple paths of output differential pairs which are symmetrically arranged about a center line; a multi-stage multi-branch differential impedance conversion unit is arranged between the input differential pair and each path of output differential pair; the differential impedance conversion section realizes stepped differential impedance conversion based on cascaded differential impedance conversion lines; a thin-film resistor is arranged at the joint of every two adjacent differential impedance conversion nodes, and absorption and cancellation paths are provided for signals reflected by the output ports; dielectric isolation between the microstrip lines is achieved through the polyimide supporting bridge structure. Through the optimization design and the integration technology, the device has the advantages of being small in size, high in anti-interference capacity and large in working bandwidth.

The method of manufacturing a semiconductor device includes: forming a fin including first sacrificial layers and channel layers alternately stacked, and second and third sacrificial layers alternately stacked; a material of one of the second and third sacrificial layers including silicon or silicon germanium, and a material of the other one including silicon germanium or germanium; a difference in germanium content between the second and third sacrificial layers being less than 15%, and the second sacrificial layer being doped with an etching auxiliary agent; forming a mask straddling the fin; selectively removing the second sacrificial layers under an accelerated etching effect of the etching auxiliary agent to form a first dielectric filling region; forming first middle dielectric isolation layers in the first dielectric filling region; and removing the first sacrificial layers, the channel layers, the first middle dielectric isolation layers, and the third sacrificial layer not covered by the mask.

The invention relates to the technical field of semiconductors, in particular to a trench MOSFET integrated with a temperature sensor and a testing method, the trench MOSFET mainly comprises a metal layer, a doped substrate layer and a doped epitaxial layer which are sequentially arranged from bottom to top, and a doped buried layer, a polysilicon gate layer and a first silicon dioxide layer are arranged on the left side of the upper portion of the doped epitaxial layer; a doped well region layer, a first doped source region layer, a second doped source region layer and a source metal layer are arranged in the middle of the upper part of the doped epitaxial layer, and an electrical isolation layer, a second silicon dioxide layer, a first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer are arranged on the right side of the upper part of the doped epitaxial layer. According to the invention, through dielectric isolation of the electrical isolation layer and the second silicon dioxide layer, the temperature sensor is not interfered by a main device, and the precision of the sensor is guaranteed.

A semiconductor structure including a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor, where at least one vertical surface of the first top contact is substantially flush with at least one vertical surface of the isolation region, and where at least one vertical surface of the second top contact is substantially flush with the at least one vertical surface of the isolation region.

In a method for forming a dielectric isolation structure or container, ion implantation is performed to form a buried implant region in a base semiconductor material. Trenches are formed in the base semiconductor material that access the buried implant region. The buried implant region is removed by etching via the trenches to form a lateral undercut region connected with the trenches. The lateral undercut region and the trenches are filled with dielectric material to form a dielectric bottom region and annular dielectric sidewall of the dielectric isolation structure. By forming of the trenches and the filling of the trenches in two or more iterations, with the removal of the buried implant region being performed after one of these iterations, detachment and self-collapse of the contained portion of base semiconductor material is avoided.

The application discloses a MEMS pressure and temperature integrated sensor with electromagnetic interference resistance and a preparation method thereof. The sensor is sequentially provided with silicon-on-insulator, a first interlayer, a polysilicon protective layer, a second interlayer and a metal protective layer from bottom to top. The buried oxygen layer of the silicon-on-insulator realizes dielectric isolation of a sensing unit and a silicon substrate; a P-type piezoresistor of a device layer forms a Wheatstone bridge through a metal lead wire to constitute a pressure sensing unit; and a metal thin film resistor of the first interlayer constitutes a temperature sensing unit. The polysilicon protective layer is connected with the device layer in an equipotential manner to form a Faraday cage type closed electromagnetic shielding cavity, and the metal protective layer is provided with an array of air holes matched with air holes, which is used for pressure conduction and electromagnetic protection. The application improves the measurement stability in a complex electromagnetic environment through multiple electromagnetic interference resistance designs, realizes device miniaturization through an integrated structure, and can realize batch production based on a mature MEMS process.