166 results about "Dielectric isolation" patented technology

Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.

A semiconductor device is provided that includes a multilayered insulator region located between stacked FETs. The multilayered insulator region is referred to herein as a multi-dielectric material middle isolation structure. The multi-dielectric material middle isolation structure includes a middle dielectric isolation structure having a middle dielectric isolation spacer located at two opposing ends of, or surrounding, the middle dielectric isolation structure. The middle dielectric isolation spacer protects the middle dielectric isolation structure during processing of the stacked FETs such that no damage to the middle dielectric isolation structure and the semiconductor channel regions of the stacked FETs is observed.

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

An antenna assembly, which includes one or more radiating element arrays and at least one dielectric isolator for the one or more radiating element arrays, wherein, the dielectric isolator is configured to tune the phase of a coupling signal between the radiating elements so as to at least partially eliminate coupling interference between the radiating elements. As a result, the radiation pattern of the antenna can be improved. The present disclosure also provides a base station antenna having the antenna assembly.

The invention discloses a terahertz metasurface capable of realizing independent control of amplitude and phase. The terahertz metasurface comprises a terahertz transparent substrate; the metasurface unit array is periodically arranged in a first direction, and each metasurface unit comprises a first structural layer which is of a dielectric resonance structure and is used for providing a phase regulation and control function; the second structural layer is a thin film formed by an adjustable absorption material and is used for providing an amplitude regulation and control function; the second structure layer is provided with an independent electrode for adjusting the transmission amplitude; a first dielectric isolation layer is arranged between the terahertz transparent substrate and the first structure layer and is used for reducing an electromagnetic coupling effect; the first structural layer and the second structural layer are stacked in the vertical direction through a three-dimensional processing technology, a second dielectric isolation layer is arranged between the first structural layer and the second structural layer, and the second dielectric isolation layer is a silicon dioxide SiO2 or silicon nitride Si3N4 film with the thickness D ranging from 100nm to 1000nm.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

A semiconductor structure includes a first set of vertically stacked contacts, a second set of vertically stacked contacts, a first set of stacked transistor devices associated with the first set of vertically stacked contacts, and a second set of stacked transistor devices associated with the second set of vertically stacked contacts. The second set of stacked transistor devices is adjacent to the first set of stacked transistor devices, and a dielectric isolation pillar is disposed between the first set of vertically stacked contacts and the second set of vertically stacked contacts.

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers. The alternating stacks are laterally spaced apart among one another by backside isolation assemblies. At least one of the backside isolation assemblies generally extends along a first horizontal direction with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction. At least one of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction. Memory stack structures vertically extend through a respective one of the alternating stacks. Each of the backside isolation assemblies includes a respective laterally alternating sequence of backside dielectric isolation walls and backside dielectric support pillar structures.

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

A semiconductor structure that includes the top field-effect transistor (FET) on a portion of the bottom FET. The semiconductor structure includes the middle dielectric isolation where the middle dielectric isolation is over the top surface of the gate of the bottom FET. The isolation layer connects the sidewalls of adjacent portions of the middle dielectric isolation. The isolation layer vertically separates one or more top source / drains of the top FET from one or more bottom source / drains of the bottom FET. A first air gap is over the middle portion of the bottom source / drain and between the middle portion of the bottom source / drain and the middle portion of the isolation. A second air gap is below the middle portion of the top source / drain and between the middle portion of the top source / drain and the middle portion of the isolation layer.

The invention discloses a stretch-resistant bending-resistant cable and temperature control type production equipment thereof, and relates to the technical field of stretch-resistant bending-resistant cables and temperature control type production equipment thereof.The cable is segmented in the axial direction, a pixelated heating ring belt base body is arranged outside a main conductor bundle in each segment, a fan-shaped cavity is formed in the base body, and Bi-Sn arc segment pixels are embedded in the fan-shaped cavity; the two layers of flexible printed electrode sleeves form an A-layer axial bus and a B-layer axial bus, the A-layer axial bus and the B-layer axial bus are connected with the arc section only in the section in a penetrating welding hole mode, and no middle hole exists outside the section and electrical interruption is achieved. And the dielectric isolation film realizes interlayer insulation. And the gating target section and the angle belt are connected in parallel for heating, so that the Bi-Sn is subjected to phase change softening and then is cured for shape locking, and local thermal shaping and peak clipping stress are completed. And an elastic encapsulating layer, a mechanical bearing and balancing base layer and a temperature bar code residual stress sheath are coated outside, and are matched with weaving and an outer sheath to prolong the fatigue life. The production equipment comprises an extrusion station, an embedding station, a rolling and welding station, a bar code writing station, an online detection station and a take-up section cutting station, and machine vision alignment ensures in-section conduction and inter-section isolation.

Provided is a semiconductor device. The semiconductor device includes: a semiconductor substrate, a first gate-all-around transistor, a second gate-all-around transistor, an insulation layer, and first and second dielectric isolation layers. The insulation layer is arranged between a source / drain region of the first gate-all-around transistor and a source / drain region of the second gate-all-around transistor. The first dielectric isolation layers and the second dielectric isolation layers are alternately stacked between a channel region of the first gate-all-around transistor and a channel region of the second gate-all-around transistor. A gate stack structure of the first gate-all-around transistor and / or a gate stack structure of the second gate-all-around transistor is located at a periphery of alternately stacked first and second dielectric isolation layers. Film layers located at bottom and top layers in alternately stacked first and second dielectric isolation layers are both first dielectric isolation layer.

The present invention discloses a method for manufacturing a semiconductor device, which relates to the field of semiconductor technology and is used to improve the yield of semiconductor devices. The method for manufacturing a semiconductor device includes: forming a fin structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes a first sacrificial layer and a channel layer alternately stacked, and a second sacrificial layer and a third sacrificial layer alternately stacked. Next, a mask structure is formed across the fin structure. Next, the second sacrificial layer is selectively removed to form a first dielectric filling region. A first middle dielectric isolation layer is formed in the first dielectric filling region. Next, the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer not covered by the mask structure are removed. Next, a first source region and a first drain region are respectively formed on both sides of the remaining first sacrificial layer and the channel layer located below the remaining first middle dielectric isolation layer. Next, an insulating layer is formed on the first source region and the first drain region.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

A deep trench structure may be formed to include a doped polysilicon core and dielectric isolation layers on the sidewalls of the doped polysilicon core. The deep trench structure may be provided as a deep trench isolation structure that laterally surrounds transistors in a semiconductor device. Additionally and / or alternatively, the deep trench structure may be included in a high-voltage transistor as a vertical drain region that extends into a semiconductor layer of a semiconductor device.

The invention discloses a laser resonant cavity based on distributed resonance feedback and a laser. The laser resonant cavity comprises a gain material layer; the first coating buffer layer is arranged above the gain material layer, a first contact layer is arranged above the first coating buffer layer, the first coating buffer layer is etched to form a waveguide ridge with the middle protruding, dielectric isolation layers are arranged on the surface layers of etching remaining areas on the two sides of the waveguide ridge, and the top surfaces of the dielectric isolation layers are planes; a first metal electrode is arranged above the first contact layer; the second coating buffer layer is arranged below the gain material layer, and a second contact layer is arranged below the second coating buffer layer; a second metal electrode is arranged below the second contact layer; and the periodic local resonance array layer is arranged around the gain material layer. According to the invention, a laser design scheme with narrow linewidth, low threshold, high output power and stable single-frequency characteristics can be realized, and external echoes are immune.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

A method includes forming a metal post over a first redistribution structure; attaching a first device die to the first redistribution structure, the first device die comprising a through via embedded in a semiconductor substrate; encapsulating the metal post and the first device die in an encapsulant, a first top surface of the encapsulant being level with a second top surface of the semiconductor substrate; recessing the second top surface to expose the through via; forming a dielectric isolation layer around the through via; forming a dielectric layer over the dielectric isolation layer; etching the dielectric layer to form a first opening and a second opening in the dielectric layer; forming a first metal via in the first opening and a second metal via in the second opening; and forming a second redistribution structure over the dielectric layer.

The application discloses a P epitaxial BCD-on-SOI integration technology and a complementary bipolar transistor device. The integration steps are as follows: forming a DTI deep trench isolation region; forming an N-type side well N+ of an external collector region of a DTI deep trench full isolation NPN transistor on an insulating layer silicon; forming a P-type side well P+ of an external collector region of a DTI deep trench full isolation longitudinal PNP transistor on an insulating layer silicon; forming a complementary NPN-PNP bipolar transistor structure; completing device-metal interlayer planarization; completing a through-hole tungsten plug structure processing; sputtering an aluminum copper film layer and completing metal wire etching processing. The device comprises a P-type base silicon wafer, an N-type buried layer, a P-type buried layer, an insulating silicon dioxide buried layer, a P-type device layer, a dielectric isolation groove region, an N-type epitaxial layer, a P-type epitaxial layer, an N-type side well injection region, a P-type side well injection region, a gate dielectric layer, a polycrystalline thin film, an oxide thin film, a tungsten plug and a metal thin film layer. The application improves the speed and precision of a high-performance circuit of a P epitaxial BCD-on-SOI process.

A semiconductor structure includes a substrate and a stacked structure including channel layers interleaved with a metal gate structure. The semiconductor structure also includes an isolation feature disposed between the stacked structure and the substrate, where a bottommost portion of the metal gate structure directly contacts the isolation feature. The semiconductor structure further includes a source / drain feature disposed adjacent the stacked structure and an inner spacer disposed between the metal gate structure and the source / drain feature.

This invention discloses a method for manufacturing a three-dimensional memory and the three-dimensional memory itself, relating to the field of semiconductor manufacturing technology, to solve the problem of high thermal budget in existing technologies for forming single-crystal semiconductor channels. The method for manufacturing the three-dimensional memory includes: providing a substrate, the substrate comprising a substrate, a stacked structure, a semiconductor active layer, and an inter-electrode dielectric layer; a through-hole is provided within the stacked structure, and the semiconductor active layer fills the bottom of the through-hole; a cylindrical induction structure and a semiconductor structure are formed on the sidewalls of the through-hole; the induction structure and the semiconductor structure are sequentially disposed on the semiconductor active layer along the thickness direction of the substrate; a second type of dielectric isolation layer is filled within the through-hole; the semiconductor structure and the induction structure are subjected to induced annealing to crystallize and modify the semiconductor structure into a single-crystal semiconductor layer; after induced annealing, the induction structure is located on top of the single-crystal semiconductor layer. The method for manufacturing a three-dimensional memory provided by this invention is used to form a single-crystal semiconductor channel with a lower thermal budget.

The method includes: forming a fin above a substrate, the fin including a lower nanostructure, an upper nanostructure, a pseudo-nanostructure, and a dielectric isolation layer disposed between the lower and upper nanostructures; forming a source / drain region adjacent to the fin; forming a groove laterally adjacent to the fin; removing the pseudo-nanostructure from the fin; forming a gate dielectric around the lower and upper nanostructures; dispensing a directional self-assembly (DSA) material into the groove; exposing the DSA material to a selected environment, wherein the polymer molecules of the DSA material are substantially aligned in the groove; performing a curing process on the lower portion of the DSA material; performing a first etching process to remove the uncured upper portion of the DSA material; doping a dipole dopant into the upper gate dielectric; and forming a gate electrode around the lower and upper nanostructures. Embodiments of this application also relate to methods for forming semiconductor structures.

The invention provides a dielectric isolation limiting device, which comprises a dielectric shielding body, the dielectric shielding body is a plate-shaped entity with a predetermined geometric extension surface, and the dielectric shielding body defines a first surface and a second surface which are arranged back to back; the first surface and the second surface are both provided with positioning protrusions, and the positioning protrusions on the two sides are coaxially and correspondingly arranged on the dielectric shielding body. In the application of a circuit breaker, the devices arranged in pairs are embedded into shell positioning holes through bulges on one sides to realize outer side anchoring, and bulges on the other sides extend into the inner side of a static contact arc striking angle and are propped against each other to form a rigid mechanical supporting structure crossing a contact area. The structure stability, the electrical insulation performance and the arc extinguishing efficiency of the circuit breaker under the high breaking working condition are remarkably improved.

This invention discloses a complete set of high-current, wide-power-range, all-dielectric-isolated BCD-on-SOI integrated technology and ESD-protected VDMOS devices. The integration steps are as follows: 1) Forming an N-type buried layer and a P-type buried layer on the surface of the substrate silicon wafer. 2) Forming a DTI deep trench isolation region. 3) Forming a vertical DMOS drain-side-well N+-N-type buried layer interconnect structure. 4) Forming an insulating silicon top-side-well P+-P-type buried layer interconnect structure. 5) Forming an ESD-protected vertical DMOS device structure. 6) Completing the planarization of the device-metal inter-dielectric layer. 7) Completing the through-hole tungsten plug structure fabrication. 8) Sputtering aluminum-copper film layers and completing the metal interconnect etching process. The device includes a P-type substrate silicon wafer, an N-type buried layer, a P-type buried layer, an insulating silicon dioxide buried layer, a P-type device layer, a dielectric isolation trench region, an N-type epitaxial layer, a P-type epitaxial layer, a gate dielectric layer, a polycrystalline thin film, an oxide thin film, a tungsten plug, and a metal thin film layer. This invention solves the integration problem of high-current vertical DMOS with BCD-on-SOI process, as well as the challenge of high-density standard device integration, thereby improving the circuit reliability of the process.

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first source / drain (S / D) electrically connected to a backside contact on a backside. A device may include a second S / D electrically connected to a frontside contact on a frontside. A device may include a channel comprising a bottom dielectric isolation (BDI) between the first S / D and the second S / D. A device may include a backside interlayer dielectric (BILD) protruding past the BDI into direct contact with the second S / D. A device may include a residual silicon between the BILD and the backside contact.

A semiconductor structure is provided including a backside source / drain contact structure that contacts a source / drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source / drain contact structure, and thus improves process margin.

The invention discloses a preparation method of an SJ MOSFET device with high FOM performance. The preparation method comprises the steps that column grooves are etched in a wafer of an epitaxial layer and filled to form alternate first conductive type columns and second conductive type columns; etching the upper part of the first conductive type column to form a gate trench; filling an oxide in the gate trench and etching to form a gate bottom oxide layer; growing a gate oxide on the gate bottom oxide layer and etching to form a gate side oxide layer; growing gate polycrystalline silicon in the gate trench and performing back etching; performing ion implantation and well pushing diffusion on the upper parts of the first conductive type column and the second conductive type column to form a body region; continuously performing ion implantation and well pushing diffusion on the upper part of the body region to form a source region; growing and etching back on the upper surface of the source region to form a dielectric isolation layer; etching at least two connecting holes between the dielectric isolation layer and the gate trench; and filling the connecting hole and depositing a metal layer on the dielectric isolation layer and the connecting hole. And the prepared SJ MOSFET device is good in impact resistance, low in on resistance and high in reliability.

The application relates to the technical field of semiconductor and MEMS devices, in particular to a monolithic integration method of dielectric isolation bipolar IC and piezoresistive MEMS devices. A buried layer of a bipolar IC circuit is prepared on the upper surface of a second silicon base; then a single crystal silicon epitaxial layer is grown on the upper surface of the second silicon base; a circuit function area (including an NPN area and a PNP area) is prepared on the single crystal silicon epitaxial layer corresponding to the area of the bipolar IC circuit; an isolation groove penetrating through the single crystal silicon epitaxial layer and the second silicon base is formed by adopting an etching process, so that the NPN area and the PNP area in the bipolar IC circuit form isolated islands respectively; polycrystalline silicon is used to fill the isolation groove; a piezoresistor is prepared on the upper surface of the single crystal silicon epitaxial layer, and metal wires connecting the NPN area, the PNP area and the piezoresistor are prepared respectively. The application overcomes the problems of device thickness and stress mismatch, conflict of material resistivity requirements, and metal pollution control difficulty faced by IC-MEMS preparation.

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET). includes forming a bottom source / drain (S / D) recess through fin-shaped columns from a top S / D recess into a substrate, wherein each of the fin-shaped columns comprises a bottom high germanium (Ge) layer on the substrate and a stack of alternating channel layers and sacrificial layers over the bottom high Ge layer, forming an S / D epitaxial (epi) layer within the bottom S / D recess, selectively removing the bottom high Ge layer to the sacrificial layers, and forming a bottom cavity between the substrate and the stack of alternating channel layers and sacrificial layers, and forming a bottom dielectric layer in the bottom cavity.

A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source / drain (S / D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S / D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed above the third and fourth S / D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer interfaces at least a topmost one of the second channel layers.