1286 results about "Low input" patented technology

A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

The present invention proposes an ESD protection circuit with low input capacitance, suitable for an I/O pad. The ESD protection circuit includes a plurality of diodes and a power-rail ESD clamp circuit between power lines. The diodes are stacked and coupled between a first power line and the I/O pad. The ESD protection circuit between power lines is coupled between the first power line and a second power line. During normal operation, the diodes are reverse-biased and the ESD protection circuit between power lines is turned off. When an ESD event between the power line and the I/O pad occurs, the diodes are forward-biased, and the ESD protection circuit between power lines is turned on to conduct ESD current. The equivalent input capacitance of the ESD protection circuit of the present invention is very small, making it particularly suitable for the I/O port of high-frequency or high-speed IC.

A method and apparatus for estimating the presence of RF interference in a wireless data channel is described. The method and apparatus comprises a set of identical tracking/register (T/R) filter blocks, each T/R filter block associated and corresponding to an RF channel of interest. Each T/R filter block includes a pair of tracking/register (T/R) filters. Power/magnitude estimates from an RSSI calculation are input to the T/R filter blocks. One T/R filter is used to estimate the noise floor (in the absence of interference). The T/R filter latches and filters the lowest input values received from a power/magnitude circuit. The other T/R filter estimates the level of an interferer, if present, by latching and filtering the largest valued outputs of the power/magnitude circuit.

A power factor corrected (pfc) ac-dc converter has a modified boost input and a modified buck output. Unlike the prior art boost input, the boost switch returns to the output, not to ground. Unlike the prior art buck output stage, a third switch connects to the input. This allows much of the input current to pass through the converter to the output. There is no input current measurement, but nearly ideal power factor correction is achieved through “natural modulation.” A preferred pfc ac-dc converter uses a variable dc-dc transformer on its output, as a post regulator, to provide dielectric isolation and to provide voltage level shifting. The output of the pfc ac-dc converter has the control characteristics of a buck converter, so it is a natural mate for the variable dc-dc transformer. An ac-dc buck converter is most efficient at its maximum duty cycle. It cannot regulate for a lower input voltage, but it can reduce its duty-cycle to control for higher input voltages. A variable dc-dc transformer is most efficient at its maximum ratio. It cannot regulate for a higher input voltage, but it can reduce its effective turns ratio to control for a lower input voltage. With a small overlap in their control ranges, both parts of the power system can operate at maximum efficiency. The variable dc-dc transformer controls the output voltage for nominal and low input voltage. The ac-dc buck converter limits over-voltage transients.

The present invention relates to a preamplifier suitable for use with Electret Condenser Microphones such as used within telecommunication equipment. More particularly the invention relates to a preamplifier specially suited for the demands to such a preamplifier within telecommunication equipment: low input capacitance, gain and a combined terminal for output and supply voltage, thus making the preamplifier suitable for two terminal microphone assemblies. These features are obtained with a two stage amplifier with a first stage optimised for low input capacitance and the second stage being able to provide gain. The preamplifier may be implemented using an ASIC, thus making the preamplifier suitable for applications with very limited space available, such as for integration within microphone assemblies.

A bistable photonic crystal configuration comprises a waveguide sided coupled to a single-mode cavity. This configuration can generate extremely high contrast between the bistable states in its transmission with low input power. All-optical switching action is also achieved in a nonlinear photonic crystal cross-waveguide geometry, in which the transmission of a signal can be reversibly switched on and off by a control input, or irreversibly switched, depending on the input power level.

An RF transceiver integrated circuit has a novel segmented, low parasitic capacitance, internal loopback conductor usable for conducting IP2 self testing and/or calibration. In a first novel aspect, the transmit mixer of the transceiver is a current mode output mixer. The receive mixer is a passive mixer that has a low input impedance. In the loopback mode, the transmit mixer drives a two tone current signal to the passive mixer via the loopback conductor. In a second novel aspect, only one quadrature branch of the transmit mixer is used to generate both tones required for carrying out an IP2 test. In a third novel aspect, a first calibration test is performed using one quadrature branch of the transmit mixer at the same time that a second calibration test is performed using the other quadrature branch, thereby reducing loopback test time and power consumption.

An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

The invention discloses a switch converter with constant connection time control, and a control circuit and method thereof. A compensation control signal is generated according to the input voltage or a control signal, and a compensation signal is adjusted according to the compensation control signal so that the compensation signal can be adjusted to a proper value within a wide input range. Compared with the prior art, jittering and subharmonic oscillation under low input can be avoided, and dynamic response and load adjusting rate under high input are improved.

A low input-current-harmonic three-phase three-level boost rectifier includes an input stage for receiving a three-phase input voltage in relation to a neutral node and an output stage adapted to couple to at least one load. The rectifier further includes one or more switching converter stages, each having a plurality of serially-connected switches coupled to the neutral node, one of the serially-connected switches operating with a fixed duty cycle while the other of the serially-connected switches operating with a variable duty cycle, the fixed duty cycle being a substantially 50% duty cycle and the variable duty cycle being less than or equal to a substantially 50% duty cycle. The serially-connected switches are coupled to clamping diodes and clamping capacitors. The rectifier further includes one or more controllers adapted to vary the switching frequency and/or duty cycle of the plurality of switches based on at least one of a condition of the at least one load or the input voltage and includes one or more decoupling stages, each including one or more inductive elements adapted to inductively decouple the output stage from at least one of the one or more switching converter stages.

The invention relates to a multi-channel data collection unit, belonging to the technical field of data collection in testing and measurement. The collection unit consists of a plurality of collection channels, a testing channel and a collection unit control module, wherein each collection channel comprises a conditioning circuit which consists of a conventional filter circuit and a voltage protective circuit, an electric switch and a delta sigma analog to digital converter; the testing channel is formed by a delta sigma digital to analog converter; the collection unit control module is realized on the basis of a programmable logic controller; the plurality of collection channels are connected with the collection unit control module; the input end of the delta sigma digital to analog converter is connected with the output end of the collection unit control module; and the output end of the delta sigma digital to analog converter is connected with each electric switch and each delta sigma analog to digital converter of the collection channel respectively. By the multi-channel data collection unit, high dynamic range, low input nose, low harmonic distortion, low crosstalk and high common mode rejection ratio can be realized, and the requirement of low power consumption and low cost can be fulfilled.

The invention provides a circuit for outputting adjustable positive, negative or zero temperature coefficient current and voltage reference, including: a start-up circuit, a positive and negative temperature coefficient current generation circuit, a feedback stable and negative temperature coefficient current derivation circuit, and the temperature coefficient can be Adjusted current reference, voltage reference synthesis circuit. The invention is realized under the standard CMOS technology, has simple structure, low input voltage, and can generate current reference and voltage (VREF) reference with adjustable temperature coefficient, which can be positive, negative or zero temperature coefficient.

A method to increase the output power of narrow-linewidth rare earth-doped fiber amplifiers by suppressing simulated Brillouin scattering. The fiber amplifier is seeded with two or more lasers having frequencies and input powers that are sufficiently different. The seed signal with the highest emission cross section (e.g., signal 2) initially experiences the greatest gain. If signal 2 is also given sufficiently greater input power than signal 1, it will be amplified to its maximum value before the seed signals have reached the midpoint of the gain fiber. Beyond that point, the signal having the lower emission and absorption cross sections (signal 1) and significantly lower input power will continue to experience gain by power transfer from both signal 2 and the pump light, attaining a power output well beyond what the maximum output would have been had the amplifier been illuminated with a single frequency beam. This technique effectively reduces the Stokes light of signal 1, whereby higher power narrow-linewidth optical fiber amplifiers may be realized.

A semiconductor memory device having a hierarchical structure of data input/output lines and a precharge method thereof. A precharge method in a semiconductor memory device having a hierarchical structure includes precharging the global input/output line pairs with half of a memory cell array voltage, and precharging the local input/output line pairs with the half of the memory cell array voltage.

An effective method enhances energy saving at low load in a resonant converter with a hysteretic control scheme for implementing burst-mode at light load. The method causes a current controlled oscillator of the converter to stop oscillating when a feedback control current of the output voltage of the converter reaches a first threshold value, and introduces a nonlinearity in the functional relation between the frequency of oscillation and said feedback control current or in a derivative of the functional relation, while the control current is between a lower, second threshold value and the first threshold value, such that the frequency of oscillation remains equal or smaller than the frequency of oscillation when the control current is equal to the second threshold value. Several circuital implementations are illustrated, all of simple realization without requiring any costly microcontroller.

The invention relates to a technology method of flotation tailings classification recovery process, belongs to solid-liquid separation technology area, used to solve maximize recovery of flotation tailings issue. It uses classification Cyclone group to grade flotation tailings, the products moisture after dehydration is 14-18%, the particle size of recovery is 0.045-3mm, it occupy55-60% of floatation tailings quantity; the pressure filter recover fine fuel, the product after dehydration occupy 40-45% of floatation tailings quantity. The invention method filled the flotation tailings bank of use the technology at home and abroad, supplies a low input, high efficiency, simple process, a high degree automation of flotation tailings recovery method, has a simple system, low-moisture products, a bulk materials, can into the coal or other late Medium steam coal advantages. Six months can recover the investment, with good economic and social benefits.

A voltage regulator includes a first stage capable of receiving a reference voltage and capable of having a first current flowing through the first stage. A second stage is capable of having a second current flowing through the second stage. A third stage is capable of outputting an output voltage and capable of having a third current flowing through the second stage. The first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and maximum output current. The first stage drives the second stage as a low input impedance load.

A differential low noise amplifier (LNA) involves two main amplifying transistors biased in saturation, and two cancel transistors biased in sub-threshold. In one example, the gates of the cancel transistors are coupled to the drains of main transistors, in a symmetrical and cross-coupled fashion. The main transistors are source degenerated. Because the gates of cancel transistors are not coupled to the differential input leads of the LNA, the input capacitance of the LNA is reduced. Noise introduced into the LNA output due to the cancel transistors being biased in the sub-threshold region is reduced because there are two stages. The first stage involves the main transistors, and the second stage involves the cancel transistors. By increasing the gain of the first stage and decreasing the gain of the second stage, overall LNA gain is maintained while reducing the noise that the sub-threshold biased transistors contribute to the LNA output.

A fail-safe circuit for a pair of differential input lines detects when one or both lines are open. Each line has a pull-up of a switched p-channel transistor in series with a resistor or another p-channel transistor that has its effective resistance controlled by a gate bias. The gate of the switched p-channel transistor is driven to ground when power is applied to the gate of a grounding n-channel transistor. When power is off, a p-channel connecting transistor charges the gate node from the differential input line when a positive voltage is applied to the input line, such as during a leakage test. Charging the gate node prevents the switched p-channel transistor from turning on, blocking a leakage current path through the pull-up. An N-well bias circuit can be added, which connects the N-well under p-channel transistors to power or the gate node or the input line.