209 results about "Low input" patented technology

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

A method for synthesizing a video is provided. The method includes obtaining a shared motion latent code corresponding to a motion between frames of the video by inputting an input frame to a first encoder, obtaining a first latent representation by inputting the input frame to a second encoder to reduce a resolution of the input frame, and predicting, by using a trained neural network model, a next frame from the input frame based on the shared motion latent code and the first latent representation.

The invention discloses a low-output-ripple ultralow-offset-voltage operational amplifier and a working method thereof. The low-output-ripple ultralow-offset-voltage operational amplifier comprises a first chopper circuit, a first-stage operational amplifier additionally provided with an offset voltage adjusting circuit, a second chopper circuit, a notch filter, a second-stage operational amplifier and a third-stage operational amplifier which are sequentially connected. The offset voltage adjusting circuit trims the input offset voltage of the first-stage operational amplifier to hundreds of microvolts and then outputs the offset voltage to the second chopper circuit; the first chopper circuit and the second chopper circuit are used for modulating the offset voltage of the first-stage operational amplifier to a chopping frequency, and then the ripple voltage at the chopping frequency is filtered by the notch filter; the first-stage operational amplifier is designed to be a high-gain amplifier so as to restrain input offset voltage errors caused by the second-stage operational amplifier and the third-stage operational amplifier. According to the invention, low output ripple voltage and ultralow input offset voltage can be realized only by using the wave trap with a small area.

The invention discloses a novel chopping correlation double-sampling stable multi-path amplifying circuit and method, and relates to integrated circuit design. A Miller compensation capacitor in a chopping stable multi-path CSMP amplification circuit architecture is utilized to design a chopping correlation double-sampling circuit, and compared with a traditional correlation double-sampling circuit, a group of sampling capacitors and sampling switches are reduced. Large capacitance and large resistance required by a traditional high-pass filter circuit are eliminated, and the layout area and the current required for driving a high-pass filter capacitor are reduced; and thermal noise caused by large resistance in the passive high-pass filter is reduced, and the input equivalent noise density is improved. Through an offset calibration technology, the stability of the CSMP architecture is ensured, and the offset voltage is reduced at the same time; output ripples are suppressed by using the high-pass performance of the novel chopping correlation double-sampling circuit, 1 / f noise is reduced, and input equivalent noise density is reduced. The advantages of the chopping correlation double sampling technology and the stable multi-path amplification circuit are combined, and the advantages of low offset, low output ripple and low input equivalent noise density are achieved.

The invention discloses an AFE analog front-end circuit applied to a multi-channel high-speed optical receiver. The circuit comprises an SF-TIA, a single-ended to differential circuit and a CLTE. The SF-TIA, the single-ended to differential circuit and the CLTE are connected in sequence; the SF-TIA is used for converting an input current signal into a voltage signal and transmitting the voltage signal to the single-ended to differential circuit; wherein the current signal is obtained by converting an input optical signal; the single-ended to differential circuit is used for converting the voltage signal into a differential voltage signal and transmitting the differential voltage signal to the CLTE; and the CLTE is used for compensating the high-frequency gain of the differential voltage signal to obtain a compensated voltage signal and outputting the compensated voltage signal. The amplifier has the advantages of being high in gain, low in power consumption, low in input impedance, low in noise, low in requirement for power supply voltage and simple in structure.

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-voltage LDO (Low Dropout Regulator) circuit with an off-chip capacitor, which comprises an error amplifier EA, a buffer circuit BUFFER, a power tube made of a first P-type DEMOS, an output voltage dividing sampling resistance circuit consisting of a first resistor R1 and a second resistor R2, a floating rail circuit, an enabling circuit and a load capacitor, the floating rail circuit comprises a Zener diode and a third resistor, and a floating low power rail VFLOAT having a stable difference value with the input voltage is provided for the EA and the BUFFER through the reverse bias breakdown voltage of the Zener diode; according to the characteristics of low output impedance and low input parasitic capacitance of the BUFFER circuit, a low-frequency secondary pole composed of an EA high output resistor and a power tube large grid parasitic capacitor is split into two high-frequency poles, and the loop stability of the high-voltage LDO is guaranteed.

The invention relates to the technical field of power management, in particular to an LDO (low dropout regulator) circuit with a wide input voltage range, which comprises a pre-voltage-stabilizing module, a band-gap reference module, an error amplification module, a voltage-stabilizing control module and a power tube, the pre-voltage-stabilizing module is used for preprocessing a wide-range input voltage into a stable low power supply voltage; the band-gap reference module is used for converting the low power supply voltage into a reference voltage; the error amplification module is used for amplifying the difference value between the reference voltage and the feedback voltage of the output circuit into a high-gain and low-noise control signal; the control signal drives the power tube after being compensated and buffered by the voltage stabilization control module, and the power tube converts the wide input voltage into an LDO output signal. Only one LDO main body circuit is adopted, the wide input voltage range can be achieved, high input voltage can be adapted, low input voltage can also be adapted, the use number of components of an LDO chip is reduced, and the occupied area of the chip is greatly reduced.

The present disclosure relates to a method and system (1) for suppressing wind noise. The method comprises obtaining an input audio signal (100, 100′) comprising a plurality of consecutive audio signal segments (101, 102, 103, 101′, 102′, 103′) and suppressing wind noise in the input audio signal with a wind noise suppressor module (20) to generate a wind noise reduced audio signal. The method further comprises sing a neural network (10) trained to predict a set of gains for reducing noise in the input audio signal (100, 100′) given samples of the input audio signal (100, 100′), wherein a noise reduced audio signal is formed by applying said set of gains to the input audio signal (100, 100′) and mixing the wind noise reduced audio signal and the noise reduced audio signal with a mixer (30) to obtain an output audio signal with suppressed wind noise.

Systems, devices, and methods are provided for all-optical reconfigurable activation devices for realizing various activations functions using low input optical power. The device and systems disclosed herein include a directional coupler comprising a first phase-shift mechanism and an interferometer coupled to the directional coupler. The interferometer comprises at least one microring resonator and a second phase-shift mechanism coupled to thereto. The interferometer and the directional coupler comprise waveguides formed of a first material, while the microring resonator comprises a waveguide formed of a second material and a third phase-shift mechanism. The second material is provided as a low-loss material having a high Kerr effect and large bandgaps, to generate various nonlinear activation functions. The first, second, and third phase-shift mechanisms are configured to control biases within the disclosed systems and devices to achieve a desired activation function.

The invention discloses a low-noise low-power-consumption cascade input comparator which comprises a pre-amplification stage and a latch stage, the pre-amplification stage is used for amplifying a pair of differential signals input from the outside, the amplified differential signals are obtained and output to the latch stage, and the latch stage is used for latching the amplified differential signals. The latch stage is used for keeping a latch state and outputting a differential comparison result, the pre-amplification stage is used for inputting a pair of differential signals by arranging a three-stage cascade structure consisting of three pairs of input geminate transistors, and is used for preventing all connection nodes of the pre-amplification stage and the latch stage from being completely discharged to the ground by arranging a pair of cross coupling geminate transistors, so that charge storage is realized; the circuit has the advantages of low input reference noise, no consumption of a large amount of extra area and power consumption, small area and low power consumption.

The proposed operational amplifier comprises at least one first amplifier circuit in a main signal path between input terminals and one or two output terminals of the operational amplifier. A secondary signal path branches off from the main signal path between the input terminals and the first amplifier circuit, containing a second amplifier circuit. This secondary path is then rejoined to the main signal path in the first amplifier circuit. The first and second amplifier circuits are dimensioned such that the signal bandwidth of the main signal path is at least 10 times greater than the signal bandwidth of the secondary signal path, and the second amplifier circuit has a lower input offset than the first amplifier circuit.This makes it possible to implement an operational amplifier with a small input-related offset error voltage while simultaneously having a fast and broadband main signal path and low power consumption.

The invention provides a 24-bit intermediate accumulation processing method and device for NPU convolution operation and a server, and relates to the technical field of neural networks, and the method comprises the steps: determining data path information of original data according to a multiplication and addition calculation result between a preset weight and an activation value corresponding to the input original data when a neural network processor NPU carries out convolution operation, the preset accumulation frequency corresponds to the data path information; the data path information is compared with a preset data path threshold value, a target processing strategy of the original data is determined according to a comparison result, and the target processing strategy comprises a low input bit width processing strategy and a high input bit width processing strategy; and performing segmented accumulation processing on the original data according to a preset accumulation frequency, and executing 24-bit intermediate value read-back, addition and write-back processing corresponding to the target processing strategy to obtain a target convolution operation output result. According to the method, the operation cost can be reduced while the error is reduced.

A discrete signal output device using a commercial discrete signal IC according to the present invention is characterized by comprising: a discrete signal IC that outputs a predetermined discrete signal voltage through an output terminal according to a logic high or logic low input signal input to an input terminal, and outputs a fault signal through a fault terminal when an overcurrent is detected at the output terminal; and a modulation signal generation circuit that receives a control signal, outputs a logic high when the control signal is a logic high and provides it as an input signal to the discrete signal IC, and based on the fault signal, outputs a modulation signal in which logic high and logic low are repeated when an overcurrent is detected at the discrete signal IC when the control signal is a logic high and provides it as an input signal to the discrete signal IC.

The present disclosure relates to a two-step gradient independent input feedback type superconducting quantum interference device and a preparation method thereof, including: eight superconducting pads, the eight superconducting pads include four input superconducting pads and four negative feedback superconducting pads, one input superconducting pad and one negative feedback superconducting pad form a superconducting loop, and the four superconducting loops are connected in parallel and arranged in a centrosymmetric manner; an input coil, the input coil is coupled with the four superconducting input superconducting pads; a negative feedback coil, the negative feedback coil is coupled with the four negative feedback superconducting pads. The present disclosure can effectively reduce the crosstalk phenomenon between the input coil and the feedback coil, and improve the coupling coefficient and transmission efficiency of the input coil and the feedback coil.

The invention discloses an input and output request scheduling method and device, a storage medium and a program product, and relates to the technical field of computer application, and the method comprises the steps: employing a high-efficiency annular request queue to manage each input and output request, guaranteeing the rapid enqueue and dequeue operation of each input and output request, and improving the operation efficiency. And request scheduling is performed according to the system resource state, the resource demand information corresponding to each input / output request and the priority, so that the system resources can be dynamically allocated. Therefore, the system can process a plurality of input and output requests at the same time, the concurrent processing capability of the system is fully utilized, the plurality of input and output requests can be reasonably scheduled, competition and conflicts of system resources are avoided, the overall throughput of the system is improved, and the problems of high system calling overhead, frequent context switching, high efficiency and the like are solved. The technical problems of low input and output request scheduling efficiency in the prior art are solved, and the technical effects of reducing the system calling overhead, avoiding frequent context switching and improving the input and output request scheduling efficiency are achieved.

The invention provides a discontinuous pulse signal frequency acquisition system and method, and the system comprises an attenuation unit, a filtering unit, an impedance matching unit, a first comparator, a second comparator and a main control unit, and the attenuation unit is used for reducing the amplitude value of an input pulse signal; the filtering unit is used for filtering the signal after the amplitude value is reduced; the main control unit is connected with the first comparator and the second comparator. According to the invention, the discontinuous pulse signal is attenuated and subjected to filtering impedance matching and then is input into the first comparator and the second comparator at the same time, the main control module triggers the first comparator to count when detecting the rising edge output by the second comparator, and the first comparator calculates the period of two continuous square waves, so that the frequency of the discontinuous pulse signal is obtained; effective and rapid acquisition of discontinuous pulse signal frequency is realized.

1. The name of the design product: product holding reminder graphical user interface for electronic device. 2. The use of the design product: an electronic device. 3. The design points of the design product: the content of the graphical user interface. 4. The picture or photo that best indicates the design points: front view. 5. The electronic device is a conventional design, and other views are omitted. 6. The use of the graphical user interface: for product holding intelligent reminder. 7. The change state of the graphical user interface: the front view is the main interface, and the corresponding reminder items are set by inputting in the lower input box or clicking the example entries in the front view, which changes to interface change state figure 1; after reaching the preset reminder time point, it automatically jumps to interface change state figure 2. 8. Other circumstances that need to be explained: the semi-transparent cover in the figure covers the variable content picture.

The utility model discloses a UPS system capable of reducing input harmonic waves, which comprises N UPS modules and a transformation module, N is not less than two, the transformation module comprises a plurality of transformer units, a primary side winding of each transformer unit is of a triangular connection structure and is used for being connected with a power supply, and a secondary side winding of each transformer unit is of a triangular connection structure. The secondary side windings of each transformer unit are connected with the input ends of the UPS module in a one-to-one correspondence manner; the plurality of transformer units are respectively a first input transformer, a second input transformer, X third input transformers and Y fourth input transformers, a secondary side winding of the first input transformer is of a triangular connection structure, and a secondary side winding of the second input transformer is of a star connection structure; a secondary side winding of the third input transformer is of a positive zigzag connection structure, a secondary side winding of the fourth input transformer is of a negative zigzag connection structure, the difference value of X and Y is not larger than 1, and the sum of X and Y is N-2. According to the design, harmonic waves can be restrained by controlling the connection structure of the secondary side windings of the transformer units.

The present invention discloses a trench-gate superjunction device with reduced input capacitance, comprising a superjunction charge balance region and a body region located at the top of the superjunction charge balance region. The superjunction charge balance region includes alternating first and second conductivity type columns. A trench gate is disposed within the body region at the top of the first conductivity type column. A source region is disposed on one side of the trench gate proximate to the second conductivity type column, and the source region is located within the body region of the first conductivity type column. The source region is connected to a source metal via a source contact hole. The present invention provides a trench-gate superjunction device with reduced input capacitance. By changing the position of the source region and the connection between the source region and the trench gate, the input capacitance of the superjunction MOSFET device is reduced, thereby improving the turn-on speed of the MOSFET device.

The present invention discloses a bandgap reference circuit that generates low input offset. The circuit comprises a bandgap reference circuit, an auxiliary operational amplifier circuit, and a chopper circuit. The bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and a voltage bias circuit. The auxiliary operational amplifier circuit includes a polarity-variable transconductance amplifier for reducing voltage input offset. The chopper circuit includes a discrete-time low-pass filter and a polarity conversion switch. The discrete-time low-pass filter is used to filter out high-frequency signals output by the reference, and the polarity conversion switch is used to complete the positive-negative polarity conversion of the operational amplifier. The present invention ensures that the equivalent input offset voltage is reduced by orders of magnitude through the chopper circuit and the auxiliary operational amplifier circuit. The auxiliary operational amplifier circuit also uses output and input storage technology to ensure the low input offset of the auxiliary operational amplifier, thereby ensuring the accuracy of the output voltage of the bandgap reference circuit and providing a good bandgap reference for subsequent analog circuits.

The utility model discloses an improved topological structure based on BOOST and LLC power topology, which comprises a switching circuit, a full-bridge LLC bridge arm and a main switching tube which are connected in parallel with the input end of the switching circuit, and a first inductor connected with the full-bridge LLC bridge arm, and the output end of the switching circuit is connected with a transformer through a first filter capacitor and a second inductor. The secondary side of the transformer is connected in parallel with a switching tube assembly and a third filter capacitor; according to the utility model, the efficiency upper limit of the two-stage power topology architecture can be improved, the output power of the BOOST circuit is reduced by half, the use of power devices can be reduced, the cost is saved, the weight and the size of an inductor can be effectively reduced, the weight and the size of a DC / DC converter can be obviously reduced, the gain of a full-bridge LLC resonant cavity is ensured, and the output power of the two-stage power topology architecture is improved. And the stability of the output voltage of the DC / DC converter under the working condition of low input voltage is ensured.

The present disclosure relates to a second-order gradient independent input feedback superconducting quantum interference device and a preparation method thereof, comprising: eight superconducting pads, the eight superconducting pads comprising four input superconducting pads and four negative feedback superconducting pads, one input superconducting pad and one negative feedback superconducting pad forming one superconducting loop, the four superconducting loops being in parallel and arranged in a central symmetry; an input coil, the input coil being coupled with the four input superconducting pads; and a negative feedback coil, the negative feedback coil being coupled with the four negative feedback superconducting pads. The present disclosure can effectively reduce the crosstalk phenomenon between the input coil and the feedback coil, and improve the coupling coefficient and the transfer efficiency of the input coil and the feedback coil.

This invention discloses a GNSS navigation signal coexistence test system and a sensitivity threshold evaluation method, relating to the field of electromagnetic compatibility testing technology. The system includes a reverberation chamber, a GNSS navigation signal transponder, a GNSS navigation signal receiver, and a host computer. The reverberation chamber includes a mechanical stirrer, a radio frequency signal source, a radio frequency power amplifier, a spectrum analyzer, a transmitting antenna T, and a receiving antenna R. The GNSS navigation signal transponder includes a transponder terminal, a transponder receiving antenna TR, and a transponder transmitting antenna TT. The GNSS navigation signal receiver includes a receiving terminal and a receiving antenna RR. Utilizing the multipath scattering characteristics of the reverberation chamber, the system simulates the fading characteristics of wireless signals in a real environment. Furthermore, leveraging the high quality factor of the reverberation chamber, a high-level test environment is created over a wide frequency range with relatively low input power, enabling GNSS navigation signal coexistence testing and quantitative evaluation and analysis of sensitivity thresholds.

An interface circuit for reducing input impedance using mirrored current feedback is disclosed herein. The interface circuit includes a current mirror and an input circuit path. The parallel feedback via the return circuit path provides a mirrored current to the interface input, thereby reducing the input impedance of the interface circuit. With parallel feedback, an input impedance of the interface circuit is reduced relative to an impedance of the input circuit path. In this manner, the input impedance of the interface circuit may be reduced without changing the impedance of the input circuit path.

The invention relates to a high-power-supply-rejection-ratio low-dropout linear voltage regulator based on gate capacitance offset. The high-power-supply-rejection-ratio low-dropout linear voltage regulator comprises an error amplifier, a power tube MP, feedback networks R1 and R2, a load capacitor CL, a frequency compensation capacitor CM and a gate capacitance offset circuit. The output end of the error amplifier, the output end of the grid capacitance offset circuit and the grid of the power tube MP are connected with one end of the frequency compensation capacitor CM; the other end of the frequency compensation capacitor CM, the drain electrode of the power tube MP, one end of the resistor R1 and one end of the load capacitor CL are connected with a VOUT end; the source electrode of the power tube MP is connected with the VIN end; the other end of the load capacitor CL and one end of the resistor R2 are connected with a grounding end GND; the other end of the resistor R1 and the other end of the resistor R2 are connected with the in-phase input end VFB of the error amplifier. The gate capacitance offset circuit is introduced to the output of the error amplifier, so that the equivalent capacitance of the node is changed, the gain from input to output is reduced, and the power supply suppression capability is improved.

A combinatorial optimization problem processing device 100 comprises: a 1 × 2 Mach-Zehnder optical modulator 10 for receiving and modulating a polarization clock pulse train; an optical interference circuit 20 for receiving the polarization clock pulse train modulated by the 1 × 2 Mach-Zehnder optical modulator 10 and generating a predetermined interaction in an Ising model at a period of N pulses of the polarization clock pulse train; a modulating signal generation unit 40 for generating the modulating signal of the 1 × 2 Mach-Zehnder optical modulator 10 by waveform-shaping an electric signal obtained by photoelectrically converting an optical signal output from the optical interference circuit 20 and outputting a monitor signal representing the solution of an optimization problem to the outside; and an initialization control unit 30 for creating a neutral state for interaction between elements to initialize the optical interference circuit 20, by controlling the optical interference circuit 20 to reduce attenuation of the polarization clock pulse train input to the optical interference circuit 20. The combination optimization problem of the N elements is processed in association with the Ising model.

A method for reading and writing frame images with multiple buffer blocks and a system are provided. In the system, when an input-fast mode is switched to an input-low mode, a read end decides whether to read a next buffer block according to a writing progress. If a write end does not change the buffer block to be written, the read end keeps reading the buffer block, and otherwise the read end selects a next buffer block to be read. In an instance that the read end is required to read the same frame image repeatedly, when the input-slow mode is switched to the input-fast mode, the write end decides whether to write a next buffer block according to a reading progress. The write end selects a next buffer block to be written with a next frame image if the read end already reads last buffer block.

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder / subtractor, and a first multiplier. The low input word path includes a second adder / subtractor, and a second multiplier. The method includes selectively bypassing the second adder / subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

Various implementations include hearing assist devices and systems for processing audio signals. In particular implementations, a process includes receiving an input signal via a microphone; performing a sound pressure level (SPL) shift that decreases a gain of the input signal to generate a gain reduced audio signal; amplifying the gain reduced audio signal using dynamic range compression to generate an amplified audio signal; generating a noise reduced amplified signal using active noise reduction that simultaneously processes the input signal; and outputting the noise reduced amplified signal to an electrodynamic transducer.

A debouncing logic circuit for processing an asynchronous input signal (din) and provide a debounced signal (dout), including a clock edge (ck), a first stage of flip-flops (q0; q1) driven by the clock edge, a multiplexer (MUX1) and coupled to the first stage of flip-flops, a second stage of flip-flops (q2; q3), a counter logic module (cnt) driven by the clock edge, a comparator module, a second multiplexer (MUX2) operable to select between the processed output signal and the debounced signal based on the control signal from the comparator, the internal state being the selected signal and an output stage (q4) driven by the clock edge and configured to provide the debounced signal (dout).