93 results about "Low input" patented technology

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

A method for synthesizing a video is provided. The method includes obtaining a shared motion latent code corresponding to a motion between frames of the video by inputting an input frame to a first encoder, obtaining a first latent representation by inputting the input frame to a second encoder to reduce a resolution of the input frame, and predicting, by using a trained neural network model, a next frame from the input frame based on the shared motion latent code and the first latent representation.

The invention relates to the technical field of power management, in particular to an LDO (low dropout regulator) circuit with a wide input voltage range, which comprises a pre-voltage-stabilizing module, a band-gap reference module, an error amplification module, a voltage-stabilizing control module and a power tube, the pre-voltage-stabilizing module is used for preprocessing a wide-range input voltage into a stable low power supply voltage; the band-gap reference module is used for converting the low power supply voltage into a reference voltage; the error amplification module is used for amplifying the difference value between the reference voltage and the feedback voltage of the output circuit into a high-gain and low-noise control signal; the control signal drives the power tube after being compensated and buffered by the voltage stabilization control module, and the power tube converts the wide input voltage into an LDO output signal. Only one LDO main body circuit is adopted, the wide input voltage range can be achieved, high input voltage can be adapted, low input voltage can also be adapted, the use number of components of an LDO chip is reduced, and the occupied area of the chip is greatly reduced.

The proposed operational amplifier comprises at least one first amplifier circuit in a main signal path between input terminals and one or two output terminals of the operational amplifier. A secondary signal path branches off from the main signal path between the input terminals and the first amplifier circuit, containing a second amplifier circuit. This secondary path is then rejoined to the main signal path in the first amplifier circuit. The first and second amplifier circuits are dimensioned such that the signal bandwidth of the main signal path is at least 10 times greater than the signal bandwidth of the secondary signal path, and the second amplifier circuit has a lower input offset than the first amplifier circuit.This makes it possible to implement an operational amplifier with a small input-related offset error voltage while simultaneously having a fast and broadband main signal path and low power consumption.

The invention provides a 24-bit intermediate accumulation processing method and device for NPU convolution operation and a server, and relates to the technical field of neural networks, and the method comprises the steps: determining data path information of original data according to a multiplication and addition calculation result between a preset weight and an activation value corresponding to the input original data when a neural network processor NPU carries out convolution operation, the preset accumulation frequency corresponds to the data path information; the data path information is compared with a preset data path threshold value, a target processing strategy of the original data is determined according to a comparison result, and the target processing strategy comprises a low input bit width processing strategy and a high input bit width processing strategy; and performing segmented accumulation processing on the original data according to a preset accumulation frequency, and executing 24-bit intermediate value read-back, addition and write-back processing corresponding to the target processing strategy to obtain a target convolution operation output result. According to the method, the operation cost can be reduced while the error is reduced.

A discrete signal output device using a commercial discrete signal IC according to the present invention is characterized by comprising: a discrete signal IC that outputs a predetermined discrete signal voltage through an output terminal according to a logic high or logic low input signal input to an input terminal, and outputs a fault signal through a fault terminal when an overcurrent is detected at the output terminal; and a modulation signal generation circuit that receives a control signal, outputs a logic high when the control signal is a logic high and provides it as an input signal to the discrete signal IC, and based on the fault signal, outputs a modulation signal in which logic high and logic low are repeated when an overcurrent is detected at the discrete signal IC when the control signal is a logic high and provides it as an input signal to the discrete signal IC.

The invention provides a discontinuous pulse signal frequency acquisition system and method, and the system comprises an attenuation unit, a filtering unit, an impedance matching unit, a first comparator, a second comparator and a main control unit, and the attenuation unit is used for reducing the amplitude value of an input pulse signal; the filtering unit is used for filtering the signal after the amplitude value is reduced; the main control unit is connected with the first comparator and the second comparator. According to the invention, the discontinuous pulse signal is attenuated and subjected to filtering impedance matching and then is input into the first comparator and the second comparator at the same time, the main control module triggers the first comparator to count when detecting the rising edge output by the second comparator, and the first comparator calculates the period of two continuous square waves, so that the frequency of the discontinuous pulse signal is obtained; effective and rapid acquisition of discontinuous pulse signal frequency is realized.

1. The name of the design product: product holding reminder graphical user interface for electronic device. 2. The use of the design product: an electronic device. 3. The design points of the design product: the content of the graphical user interface. 4. The picture or photo that best indicates the design points: front view. 5. The electronic device is a conventional design, and other views are omitted. 6. The use of the graphical user interface: for product holding intelligent reminder. 7. The change state of the graphical user interface: the front view is the main interface, and the corresponding reminder items are set by inputting in the lower input box or clicking the example entries in the front view, which changes to interface change state figure 1; after reaching the preset reminder time point, it automatically jumps to interface change state figure 2. 8. Other circumstances that need to be explained: the semi-transparent cover in the figure covers the variable content picture.

The present disclosure relates to a second-order gradient independent input feedback superconducting quantum interference device and a preparation method thereof, comprising: eight superconducting pads, the eight superconducting pads comprising four input superconducting pads and four negative feedback superconducting pads, one input superconducting pad and one negative feedback superconducting pad forming one superconducting loop, the four superconducting loops being in parallel and arranged in a central symmetry; an input coil, the input coil being coupled with the four input superconducting pads; and a negative feedback coil, the negative feedback coil being coupled with the four negative feedback superconducting pads. The present disclosure can effectively reduce the crosstalk phenomenon between the input coil and the feedback coil, and improve the coupling coefficient and the transfer efficiency of the input coil and the feedback coil.

Various implementations include hearing assist devices and systems for processing audio signals. In particular implementations, a process includes receiving an input signal via a microphone; performing a sound pressure level (SPL) shift that decreases a gain of the input signal to generate a gain reduced audio signal; amplifying the gain reduced audio signal using dynamic range compression to generate an amplified audio signal; generating a noise reduced amplified signal using active noise reduction that simultaneously processes the input signal; and outputting the noise reduced amplified signal to an electrodynamic transducer.

A debouncing logic circuit for processing an asynchronous input signal (din) and provide a debounced signal (dout), including a clock edge (ck), a first stage of flip-flops (q0; q1) driven by the clock edge, a multiplexer (MUX1) and coupled to the first stage of flip-flops, a second stage of flip-flops (q2; q3), a counter logic module (cnt) driven by the clock edge, a comparator module, a second multiplexer (MUX2) operable to select between the processed output signal and the debounced signal based on the control signal from the comparator, the internal state being the selected signal and an output stage (q4) driven by the clock edge and configured to provide the debounced signal (dout).

This invention discloses a constant current control method for a primary-side feedback flyback converter, relating to the field of isolated converter technology. The method includes: when the primary-side feedback flyback converter operates in continuous current mode, determining the transformer demagnetization duration, cycle duration, and primary winding current valley value for the nth switching control cycle; obtaining the switching turn-off duration for the (n+1)th switching control cycle based on the transformer demagnetization duration, cycle duration, primary winding current valley value, a set reference primary current peak value, and the desired target current value; controlling the switching turn-on duration for the (n+1)th switching control cycle based on the reference primary current peak value, and controlling the switching turn-off duration for the (n+1)th switching control cycle to be the calculated turn-off duration. This method avoids low-frequency current ripple by eliminating the need for PID modulation calculations and can eliminate subharmonic oscillations at low input voltages.

The invention relates to the field of switching power supply control, in particular to a control method, a controller, a chip and a circuit of a parallel interleaved switching power supply. According to the invention, the two phases which are interleaved in parallel are operated at a phase difference of 180 degrees, so that the inductive current ripples are mutually offset, and the ripple current burden of an input capacitor is remarkably reduced. And under the action of uniformly distributed current, the current stress of a single-phase device is reduced, and inductors and switching devices with smaller sizes are used. Meanwhile, phase staggering can disperse switching loss and reduce thermal stress.

A method for reducing noise using a neural-network-based adaptive line enhancer includes receiving an input signal including a narrowband signal and noise. The narrow signal and the noise are de-correlated via an artificial neural network. The artificial neural network generates an estimate of the narrowband signal. The noise in the input signal is reduced based on the estimated narrowband signal.

The application relates to the technical field of semiconductor power devices, and discloses a SiC MOSFET structure with a low input capacitance and a STI structure and a manufacturing method thereof. The structure comprises a silicon carbide substrate, an N-type drift layer, a P well, and a heavily doped N region and a P region. A shallow groove is embedded in the surface of a JFET region between adjacent P wells, and a silicon dioxide layer is filled in the shallow groove to form a STI structure. The upper surface of the structure is flush with the upper surface of the unetched drift layer. The sidewall and the bottom of the shallow groove are covered with an N-type charge compensation layer with a higher doping concentration. A thin gate oxide layer covers the surface of the P well and the STI structure, and a gate electrode is arranged on the thin gate oxide layer. The application increases the insulating physical distance between the gate and the epitaxial layer by introducing the STI structure, reduces the parasitic capacitance and the high-frequency switching loss, compensates for the problem of the rise of the conduction resistance caused by the narrowing of the channel by using the N-type charge compensation layer, eliminates the physical step through surface planarization treatment, and improves the blocking withstand voltage level of the device.

The present application provides a vector modulation method and apparatus for a converter, a system, and a readable storage medium. The method comprises: when an operating sector to which a current vector corresponding to the current operating mode of a converter belongs is an odd-numbered sector and the application of two adjacent current vectors in the sector follows a high-to-low sequence, determining, on the basis of the flow direction of each phase current among three-phase input currents of the converter, a smooth switching condition that needs to be satisfied when the sector corresponding to the operating mode of the converter is switched from the odd-numbered sector to an even-numbered sector; on the basis of the smooth switching condition, calculating a target duty cycle compensation value of a target current vector in a target sector; and on the basis of the target duty cycle compensation value, performing duty cycle adjustment on a switching transistor corresponding to the target current vector. By means of the implementation of the solution of the present application, the problem of current distortion during sector switching can be effectively mitigated while ensuring the implementation of soft switching, and the THD of an input current can be significantly reduced.

This invention proposes a high-gain, high-linearity amplifier circuit, mainly comprising an input circuit and an output circuit. The input circuit has high gain, converting the received input voltage into current and amplifying it. The input circuit transmits the amplified current to the output circuit. The output circuit generates an output voltage and reduces the input impedance of the input circuit through its included feedback loop. The feedback loop in the output circuit also stabilizes the gain of the entire circuit system and optimizes the system linearity. This invention significantly improves the system gain through the amplifier circuit structure and the back-gate coupled circuit structure, and optimizes the system linearity by setting passive and active feedback loops. This invention achieves both high gain and high linearity.

A method for operating a power converter and a power converter are disclosed. A power converter includes: three input nodes and an output, each configured to receive a respective one of three alternating input voltages; three transformers, each comprising a first winding and a second winding inductively coupled to the first winding; an input circuit having three input stages, each input stage coupled to a respective one of the input nodes, a first winding of a respective one of the transformers, and a common circuit node; and an output circuit coupled to the second winding and the output of each of the transformers. The method includes detecting a lowest input voltage, which is one of the input voltages having a lowest amplitude; connecting one of the input nodes that receives the lowest input voltage to a common circuit node through an input stage connected to the one of the input nodes that receives the lowest input voltage; and operating the other input stages in a switched mode to generate an alternating voltage across a first winding connecting the other input stages.

The invention relates to the technical field of microwave radio frequency front ends, in particular to a sectional type matching microwave radio frequency front end module framework. Comprising a radio frequency input, a power amplifier, a multi-path adjustable switch matching array, a filter bank and an antenna device, and the radio frequency input is connected to the input end of the power amplifier; the output end of the power amplifier is connected with one end of the multi-path adjustable switch matching array; the other end of the multi-path adjustable switch matching array is connected with one end of the filter bank; the other end of the filter bank is connected with the antenna device; the power amplifier is configured to work in a low impedance window; the multi-path adjustable switch matching array is used for selecting a filter; the filter bank is configured to have a low input impedance characteristic and spectrally shaped. Through a sectional matching architecture, the matching network is separated from the filter and the switch module, so that the system can automatically select an optimal impedance path according to different working modes, and high-efficiency matching between low impedance and standard impedance is realized.

The invention belongs to the field of integrated circuits, and particularly relates to a JFET (Junction Field Effect Transistor) input operational amplifier suitable for high-speed weak current detection, which comprises a first biasing circuit, a second biasing circuit, a third biasing circuit, a fourth biasing circuit, a fifth biasing circuit and a sixth biasing circuit, the product of the gain of the differential input stage circuit and the gain of the intermediate amplification stage circuit is used as the gain of the amplifier, the complementary push-pull output stage circuit and the intermediate amplification stage circuit adopt a folded common-emitter common-base structure with emitter feedback, and the intermediate amplification stage circuit converts two differential signals output by the differential input stage circuit into single-ended signals. The complementary push-pull output stage circuit further converts the single-ended signal into an output signal of the amplifier. The problems of a trans-impedance amplifier with high gain bandwidth product, high slew rate, low noise and low input bias current required during high-speed weak current detection in the prior art are solved.

A high-electron mobility transistor includes a semiconductor body including a plurality of type III-nitride semiconductor layers stacked on top of one another, thereby forming a plurality of two-dimensional first charge type gas channels and at least one two-dimensional second charge type gas channel vertically in between two of the two-dimensional first charge type gas channel, source and drain electrodes that are laterally spaced apart from one another and in ohmic contact with the plurality of two-dimensional first charge type gas channel, a gate structure configured to control a conductive connection between the source and drain electrodes by controlling a conductive state of the plurality of two-dimensional first charge type gas channels, and a charge dissipation structure that is configured to remove second charge type carriers from the two-dimensional second charge type gas channel during an off-state of the high-electron mobility transistor.

The invention provides a boost converter based on coupling inductance interleaving, belongs to the technical field of power electronic direct-current converters, and provides an innovative architecture for solving the problems that a traditional high-gain boost circuit is generally large in component number, high in system cost, low in overall efficiency, remarkable in input current ripple and the like. By introducing a switching voltage clamping technology, the voltage stress and switching loss of a switching device are remarkably reduced; and an interleaving parallel structure is adopted, so that input current ripples in the switching-off process of the MOSFET are effectively inhibited, and the power density of the system is improved at the same time. The converter is widely applicable to various battery power supply systems, fuel cells, photovoltaic power generation and other green energy application occasions, is particularly applicable to technical scenes of low input voltage and high output voltage level, and has the advantages of high step-up ratio, low switching stress, excellent efficiency, simplicity and convenience in control, low cost and the like.

This invention proposes a circuit structure and method to improve the performance of DC-DC chips. By setting a comparator and a charge pump after the power transistor, the circuit structure can provide a negative voltage to the gate of the power transistor when the source-drain voltage of the power transistor in the DC-DC chip is detected to be greater than a given threshold voltage. This reduces the on-resistance of the power transistor, thereby solving the problems of slow startup speed caused by excessive power transistor impedance during DC-DC chip startup and low load capacity caused by excessive power transistor impedance at low input voltage.

This utility model discloses an ultrasonic energy driving circuit, belonging to the technical field of driving circuits for ultrasonic generators. It includes a waveform generating circuit and a matching circuit. The input terminal of the waveform generating circuit is connected to the output terminal of the frequency generating circuit. The waveform generating circuit includes two Class E amplifier circuits. The input terminal of each Class E amplifier circuit is connected to the DC output terminal of the power drive power supply. The output terminal of the waveform generating circuit is connected to the input terminal of the matching circuit, and the output terminal of the matching circuit is connected to the ultrasonic transducer. This utility model can reduce the input bus voltage under the same output power requirements, allowing a small switching power supply to meet the requirements. Furthermore, the size and weight of the heat sink for the field-effect transistor are reduced, and voltage stress can be shared, further reducing heat generation.

The invention provides a multi-channel operational amplifier circuit and system, and relates to the technical field of multi-channel operational amplification. The bias module is electrically connected with the differential input module, the differential input module is further electrically connected with the current summation module, the secondary amplification module and the frequency compensation module, and the secondary amplification module, the current summation module and the frequency compensation module are electrically connected with one another; the differential input module comprises a plurality of input differential pairs with equal transconductance, one of the input differential pairs is used for receiving the voltage of the feedback network, and the other input differential pairs are used for receiving output signals of different sensors; the current summing module is used for summing the currents of the rest input differential pairs; and the secondary amplification module is used for providing voltage gain required by the multi-path operational amplifier circuit after current summation. According to the invention, the signal-to-noise ratio of the whole system is improved, the addition of Hall signals in front of the amplifier is realized, and lower input noise and lower power consumption are realized.

The invention provides an input device. The input device comprises a base, a magnetic roller and an optical module, the magnetic roller is rotatably arranged on the base. The optical module is arranged on the base, located on one side of the magnetic roller and used for sensing rotation of the magnetic roller. By arranging the optical module, the power consumption of the input device can be reduced, and the cost of the input device can be reduced by sensing the rotation of the magnetic roller through the optical module.

The invention belongs to the field of high-speed signal transceiving, and particularly discloses a high-bandwidth low-loss double-pole double-throw repeater for switching data paths, which is composed of two DPDTs, the DPDTs are distributed amplification circuit architectures, and due to the fact that the distributed amplification circuit architectures have good broadband characteristics, due to the use of an input matching network and an output matching network, the bandwidth of the DPDTs is greatly improved. The distributed amplification circuit has the characteristics of low input echo reflection and output echo reflection in a wide frequency range, so that the DPDT provided by the invention has the advantages of high bandwidth and low reflection. Meanwhile, different from a traditional transmission gate type switching circuit, the amplification unit used for controlling on or off of a data path has a certain gain, lossless transmission of signals can be achieved, and the DPDT is made to be low in loss and even free of loss.

The application discloses a foldback type slope compensation system and a compensation method thereof, which adopts real-time sampling of the change of the conduction time of adjacent periods to correct the effect of slope compensation in real time, dynamically changes the size of the slope compensation voltage, enters a foldback type adjustment stage when the slope compensation is effective, and adopts a foldback method to find the optimal compensation amount, so that the problem of overlarge or too small slope compensation voltage can be effectively avoided, real-time disturbance caused by different input voltages and output voltages can be adjusted in real time, dynamic response is improved, and output voltage fluctuation caused by subharmonic oscillation can be effectively converged when the input voltage is low and the output is full.

The invention relates to a driver circuit for driving a voltage-controlled electro-optical modulator by providing an output voltage to the electro-optical modulator in dependence on an input voltage. The driver circuit comprises a supply input for receiving a direct supply voltage having a positive supply voltage level and an input for receiving the input voltage, wherein the input voltage varies between a low input level and a high input level. The driver circuit further comprises a level shifter circuit comprising two capacitors and being electrically connected to the input, and a voltage distribution circuit electrically connected between the level shifter circuit and an output of the driver circuit for providing the output voltage. The level shifter circuit is configured to generate, based on the input voltage and using a first of the two capacitors, a first voltage varying between the positive supply voltage level and a positive first level greater than the positive supply voltage level.

An electronic readout network topology for positron emission tomography is able to provide Time of Flight for photodetectors arranged in matrix arrays made up of a plurality of silicon photomultipliers. Each photodetector has anode and cathode terminals. The readout network topology ensures suitable polarisation of the set of photodetectors and provides a reduction diagram by creating a single connection to extract a unique time reference signal that is accurate and synched up in phase to a detection event at any position of the photodetector matrix instead of connecting to each individual photodetector. A fast amplifier with low input impedance is electrically coupled to this time reference signal, creating a path of low impedance for the rapid transition signals, reducing the total parasitic capacitance of the parallel arrangement of detectors, and improving the time response of the detector block. Moreover, the readout electronics creates a smaller number of positioning signals.