1105 results about "Muxponder" patented technology

Systems and methods for performing hardware approximation of functions are provided. In one example, a system comprises a controller, a plurality of multiplexors, configurable arithmetic circuits, and a mapping table that stores a set of function parameters. According to a mode of operations, the controller may configure the plurality of multiplexors to forward the set of function parameters or a subset of the function parameters to the arithmetic circuits to compute an approximation result. In a case where the subset of the function parameters is forwarded to the arithmetic circuits, the controller may configure the arithmetic circuits to perform post-processing, such as quantization, of the approximation result.

The invention discloses an anti-radiation hardening digital controlled oscillator, a clock data recovery circuit and equipment, and the digital controlled oscillator is characterized in that an anti-radiation hardening circuit unit is connected between a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), and comprises a voltage copying unit and a multiplexer; the voltage copying unit is used for copying a control voltage signal output by the digital-to-analog converter DAC, generating a copying voltage signal, sending the copying voltage signal to the multiplexer, and switching the output of the multiplexer from the control voltage signal to the copying voltage signal when the digital-to-analog converter DAC is subjected to single-particle bombardment. The DCO type clock data recovery circuit aims at solving the problem that a traditional DCO type clock data recovery circuit is prone to being affected by single particles when running in a radiation environment, single particle function interruption is generated, and consequently a space task fails, and the radiation hardening capacity of the DCO type clock data recovery circuit running in the radiation environment is improved.

A display device includes a timing controlling circuit configured to generate image data, a data control signal and a gate control signal; a data driving circuit configured to generate a data signal using the image data and the data control signal and generate a mux signal using an offset signal, a high level voltage signal and the data signal; a gate driving circuit configured to generate gate signals, emission signals using the gate control signal; and a display panel including pixels that are configured to display an image using the data signal, the mux signal, the gate signals, and the emission signals, wherein the mux signal is one of the high level voltage signal and voltage that is a sum of the data signal and the offset signal, and the mux signal is supplied to a power line that is connected to a pixel included in the display panel.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

To provide an acoustic wave device suppressing an area, where an acoustic wave element can be formed, from becoming smaller.SOLUTION: An acoustic wave device 100 includes: a support substrate 10; a piezoelectric layer 11 provided on the support substrate 10; an acoustic wave element 20 provided on the piezoelectric layer 11; a frame body 30 provided, on the support substrate 10, to surround the acoustic wave element 20 as viewed from the top of the piezoelectric layer 11; a lid 40 provided on the frame body 30 while sandwiching a gap 15 together with the support substrate 10, and sealing the acoustic wave element 20 in the gap 15; and a columnar body 50 which is provided between a lower surface 41 of the lid 40 and an upper surface 17 of the piezoelectric layer 11 within the gap 15 and in which a space 16 that is a gap between the lower surface 41 of the lid 40 and the columnar body is formed.SELECTED DRAWING: Figure 1

A multiplexer includes first and second filters, a resin layer, and an electrically conductive layer. A pass band of the first filter is different from a pass band of the second filter. The first filter is in contact with an electrically conductive layer, and the second filter is not in contact with the electrically conductive layer. The second filter has a greater thermal resistance value than the first filter, and lowers the pass band in response to a temperature rise. A region of the piezoelectric substrate closer to the first filter is a first region, and a region of the piezoelectric substrate farther from the first filter is a second region. Areas in the first and second regions where an acoustic wave resonator included in a parallel-arm circuit is provided are first and second areas. The second area is greater than the first area.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

A switched-element digital-to-analog converter (DAC) circuit for use, for example, in a successive-approximation register, SAR, analog-to-digital converter, ADC. The DAC circuit comprises a pool of unary circuit elements (410), each having a common nominal weighting value, and switching (420) and multiplexer (430) arrangements configured so that each unary circuit element (410) in the pool can be independently associated with any one of two or more bits of the switched-element DAC.

Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.

The embodiment of the invention discloses a vehicle controller awakening system, method and device and a vehicle, and the system comprises a multiplexer which comprises a first part pin, a second part pin, an output pin and a channel selection control pin; one input pin in the first part of pins and one input pin in the second part of pins are connected to a CAN bus and are used for receiving a CAN wake-up signal, and the other input pins are connected to other wake-up sources respectively; the output pin is connected with the input pin of the controller; the controller comprises a control signal output pin and an input pin, the control signal output pin is connected with the channel selection control pin, and the controller is used for controlling wake-up signal detection for the multiplexer through control signal polling based on polling cycles and polling the first part of pins and the second part of pins through two polling cycles respectively, and when the wake-up signal is received, starting is carried out. According to the embodiment of the invention, the rapid wake-up requirement of the CAN wake-up signal is met under the condition that the sleep power consumption of the whole vehicle is met.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

A system includes a plurality of application processors (APs), a plurality of flash memory devices associated with the plurality of APs, and a plurality of multiplexers, each to selectively couple a flash memory device of the plurality of flash memory devices to an AP of the plurality of APs. A controller is operatively coupled to the plurality of multiplexers and provides a trusted execution environment to execute a virtual root of trust (vROT) application for each respective AP of the plurality of APs. Each vROT application accesses a corresponding one or more of the plurality of flash memory devices via a corresponding one or more of the plurality of multiplexers.

Devices, systems, and methods for reconfigurable butterfly architectures are provided. A reconfigurable butterfly operator circuit includes a single multiplier configured to receive a first variable and a twiddle factor and produce a product, first and second modular subtractors coupled to the multiplier, the first modular subtractor coupled to receive input coefficients and provide a modular difference, and the second modular subtractor coupled to receive the product, a modular adder coupled to receive the input coefficients and provide a modular sum, and multiplexers coupled to (i) provide the input coefficients to the modular adder, (ii) provide the first variable and the twiddle factor to the multiplier, (iii) and receive the modular difference from the first modular subtractor, respectively, each of the multiplexers coupled to receive a control signal that selects whether the circuit is configured as a Gentleman-Sande butterfly operator circuit or a Cooley-Tukey butterfly operator circuit.

According to one embodiment, a transmitter device includes: a digital processing circuit generating n-phase first and second digital signals, the second digital signal shifted from the first digital signal by a first phase; a delay circuit generating an n-phase second clock signal shifted from an n-phase first clock signal by a second phase being 0 or more and being the first phase or less; a first multiplexer converting the first digital signal into a single-phase third digital signal based on the first clock signal; a second multiplexer converting the second digital signal into a single-phase fourth digital signal shifted from the third digital signal by a sum of the first phase and the second phase based on the second clock signal; and a first driver outputting a composite signal of first and second analog signals based on the third and fourth digital signals.

A display device is provided. The display device includes a substrate including a touch sensing area and a touch peripheral area disposed near the touch sensing area; a circuit layer disposed on the substrate; a touch sensor layer disposed on the circuit layer, including N number of touch sensing electrodes arranged in the touch sensing area in a first direction and a second direction, and N number of sensing transfer lines electrically connected to the N number of touch sensing electrodes, respectively; a multiplexer disposed in the touch peripheral area and electrically connected between the N number of sensing transfer lines and a touch driving circuit; and an electrostatic shielding layer overlapping with the multiplexer. The N number of sensing transfer lines extend from the N number of touch sensing electrodes to the multiplexer. Among the N number of sensing transfer lines, 2M number of sensing transfer lines selected by the multiplexer are electrically connected to the touch driving circuit. Each of N and M is a natural number and M is smaller than N.

An apparatus includes a first image processing path associated with a first image sensor and a second image processing path associated with a second image sensor. The apparatus further includes a multiplexer (MUX). The MUX is configured to provide data from the first image sensor to the second image processing path in accordance with a resource availability parameter associated with the second image processing path satisfying a resource availability condition.

An optical communication system can include a multiplexer / demultiplexer. The multiplexer / demultiplexer can transfer a first optical data signal between a first single-mode fiber and a first propagation mode of a few-mode fiber. The first propagation mode can have a first effective refractive index. The multiplexer / demultiplexer can transfer a second optical data signal between a second single-mode fiber and a combination of a second propagation mode of the few-mode fiber and a third propagation mode of the few-mode fiber. The second propagation mode and the third propagation mode can have a same effective refractive index that differs from the first effective refractive index. During propagation within the few-mode fiber, the second optical data signal can couple bidirectionally between the second propagation mode and the third propagation mode, while being substantially isolated from the first optical data signal in the first propagation mode.

Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.

A multi-master control circuit includes signal switch, D-type flip-flop, and multiplexer. The signal switch outputs switching signals based on a first control signal generated by a first processor or a second control signal generated by a second processor. The D-type flip-flop includes clock input, signal input, signal output, and inverted signal output. The clock input is coupled to the signal switch to receive the switching signals, and the inverted signal output is coupled to the signal input. Upon triggering by the switching signals, the signal output of the D-type flip-flop generates a selection signal. The multiplexer receives a first access signal generated by the first processor and a second access signal generated by the second processor. The multiplexer is coupled to the signal output of the D-type flip-flop to receive the selection signal and output either the first access signal or the second access signal based on the selection signal.

An interconnect fabric in an integrated circuit (IC) device can be hierarchically partitioned into a set of peripheral sub-fabrics and a glue sub-fabric coupled to each of the peripheral sub-fabrics based on the physical design information associated with the IC device. Each of the peripheral sub-fabrics and the glue sub-fabric can be implemented using 2:1 hierarchical multiplexers based on an agglomerative clustering scheme. Physically aware design of the hierarchical multiplexer tree along with the optimal placement of the 2:1 multiplexers can provide smaller overall wire length and reduced routing congestion in the interconnect.

The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.

According to an embodiment, a biopotential measurement system includes an analog front-end and digital circuits. The analog front-end circuit includes a sensing electrode, a forward amplifier, and a feedback amplifier with an integration capacitor. A feature is the attenuation circuit between the forward and feedback amplifiers, which provides an attenuation factor determining the integration capacitor's value for achieving the desired high-pass corner frequency. With configurable attenuation factors, the system can process different biopotential signals. Multiple analog front-end circuits can be used to process different signals simultaneously. The digital circuit includes a processor for signal processing, dynamic adjustment of attenuation factors, and anomaly detection. Additional components like switched capacitors, pseudo-resistors, and multiplexers can enhance the system's functionality. The design allows flexible, multi-parameter physiological monitoring with adjustable frequency responses and gain settings.

Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.

Configurable logic slices for programmable logic devices and methods of using and programming such logic slices and devices are presented herein. In one embodiment, a programmable logic device (PLD) is disclosed that includes a logic slice. The logic slice may include a first look-up table (LUT) configured to generate a first output; and an input switch stage configured to receive the first output and selectively generate a first signal. The logic slice may further include a second LUT configured to receive the first signal and to generate a second output; and a two-to-one multiplexer configured to receive the first output and the second output and selectively produce an output of the logic slice.

On a foveated electronic display, foveated image data may include a variety of groupings of pixels in different resolutions for different parts of the display. As such, different parts of the foveated image data are routed to different pixels of the electronic display. One way of routing data is to use multiplexers to select which image data is routed to which source latches of columns of pixels of the electronic display. Depending on the number of columns of the electronic display, however, the multiplexers may consume a significant portion of the die area while also consuming a significant amount of energy and reducing the field-of-view (FOV). Instead of using multiplexers to route foveated image data in the electronic display, groups of source latches of the electronic display may be hardwired to respective wires of a pixel data bus.

The SGPIO multi-path expansion circuit provided by the embodiment of the utility model comprises a mainboard management controller BMC and at least two complex programmable logic devices CPLDs connected with the BMC in series, each CPLD comprises an SGPIO slave node Slave and a first multiplexer MUX connected with the SGPIO slave node Slave, an output interface of the BMC is connected with the SGPIO slave node Slave in each CPLD, and an output interface of the BMC is connected with the first multiplexer MUX. Different SGPIO Slaves are configured to analyze signals of preset storage space digits in first signals transmitted by the output interface of the BMC. According to the technical scheme, the SGPIO Slave in the CPLD receives the signals transmitted by the output interface of the BMC, then the SGPIO Slave only analyzes the signals with the preset storage space bits in the first signals, and then the unanalyzed signal data is transmitted to the next CPLD to be analyzed, so that logic resources consumed by the CPLD are reduced, and the real-time performance of data transmission is improved.

A display device includes a display panel divided into a display area and a non-display area such that data lines and gate lines are arranged in the display area in an intersecting manner, thereby defining pixels in a matrix, a multiplexer disposed in the non-display area of the display panel at one side of the data lines, an auto-probe (AP) test circuit disposed in the non-display area of the display panel at the other side of the data lines, and a data driver for supplying a data voltage to the data lines of the display panel through the multiplexer. The multiplexer and the AP test circuit may detect a defect of a link line connected to each data line.

A multiplexer is disclosed. The multiplexer can include a multilayer piezoelectric substrate surface acoustic wave device that includes at least a portion of a transmission filter. The multiplexer can include a temperature compensated surface acoustic wave device that includes at least a portion of a reception filter. The reception filter is electrically connected to the transmission filter.