773 results about "Muxponder" patented technology

Systems and methods for performing hardware approximation of functions are provided. In one example, a system comprises a controller, a plurality of multiplexors, configurable arithmetic circuits, and a mapping table that stores a set of function parameters. According to a mode of operations, the controller may configure the plurality of multiplexors to forward the set of function parameters or a subset of the function parameters to the arithmetic circuits to compute an approximation result. In a case where the subset of the function parameters is forwarded to the arithmetic circuits, the controller may configure the arithmetic circuits to perform post-processing, such as quantization, of the approximation result.

A display device includes a timing controlling circuit configured to generate image data, a data control signal and a gate control signal; a data driving circuit configured to generate a data signal using the image data and the data control signal and generate a mux signal using an offset signal, a high level voltage signal and the data signal; a gate driving circuit configured to generate gate signals, emission signals using the gate control signal; and a display panel including pixels that are configured to display an image using the data signal, the mux signal, the gate signals, and the emission signals, wherein the mux signal is one of the high level voltage signal and voltage that is a sum of the data signal and the offset signal, and the mux signal is supplied to a power line that is connected to a pixel included in the display panel.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

The embodiment of the invention discloses a vehicle controller awakening system, method and device and a vehicle, and the system comprises a multiplexer which comprises a first part pin, a second part pin, an output pin and a channel selection control pin; one input pin in the first part of pins and one input pin in the second part of pins are connected to a CAN bus and are used for receiving a CAN wake-up signal, and the other input pins are connected to other wake-up sources respectively; the output pin is connected with the input pin of the controller; the controller comprises a control signal output pin and an input pin, the control signal output pin is connected with the channel selection control pin, and the controller is used for controlling wake-up signal detection for the multiplexer through control signal polling based on polling cycles and polling the first part of pins and the second part of pins through two polling cycles respectively, and when the wake-up signal is received, starting is carried out. According to the embodiment of the invention, the rapid wake-up requirement of the CAN wake-up signal is met under the condition that the sleep power consumption of the whole vehicle is met.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

Devices, systems, and methods for reconfigurable butterfly architectures are provided. A reconfigurable butterfly operator circuit includes a single multiplier configured to receive a first variable and a twiddle factor and produce a product, first and second modular subtractors coupled to the multiplier, the first modular subtractor coupled to receive input coefficients and provide a modular difference, and the second modular subtractor coupled to receive the product, a modular adder coupled to receive the input coefficients and provide a modular sum, and multiplexers coupled to (i) provide the input coefficients to the modular adder, (ii) provide the first variable and the twiddle factor to the multiplier, (iii) and receive the modular difference from the first modular subtractor, respectively, each of the multiplexers coupled to receive a control signal that selects whether the circuit is configured as a Gentleman-Sande butterfly operator circuit or a Cooley-Tukey butterfly operator circuit.

An apparatus includes a first image processing path associated with a first image sensor and a second image processing path associated with a second image sensor. The apparatus further includes a multiplexer (MUX). The MUX is configured to provide data from the first image sensor to the second image processing path in accordance with a resource availability parameter associated with the second image processing path satisfying a resource availability condition.

An optical communication system can include a multiplexer / demultiplexer. The multiplexer / demultiplexer can transfer a first optical data signal between a first single-mode fiber and a first propagation mode of a few-mode fiber. The first propagation mode can have a first effective refractive index. The multiplexer / demultiplexer can transfer a second optical data signal between a second single-mode fiber and a combination of a second propagation mode of the few-mode fiber and a third propagation mode of the few-mode fiber. The second propagation mode and the third propagation mode can have a same effective refractive index that differs from the first effective refractive index. During propagation within the few-mode fiber, the second optical data signal can couple bidirectionally between the second propagation mode and the third propagation mode, while being substantially isolated from the first optical data signal in the first propagation mode.

A multi-master control circuit includes signal switch, D-type flip-flop, and multiplexer. The signal switch outputs switching signals based on a first control signal generated by a first processor or a second control signal generated by a second processor. The D-type flip-flop includes clock input, signal input, signal output, and inverted signal output. The clock input is coupled to the signal switch to receive the switching signals, and the inverted signal output is coupled to the signal input. Upon triggering by the switching signals, the signal output of the D-type flip-flop generates a selection signal. The multiplexer receives a first access signal generated by the first processor and a second access signal generated by the second processor. The multiplexer is coupled to the signal output of the D-type flip-flop to receive the selection signal and output either the first access signal or the second access signal based on the selection signal.

According to an embodiment, a biopotential measurement system includes an analog front-end and digital circuits. The analog front-end circuit includes a sensing electrode, a forward amplifier, and a feedback amplifier with an integration capacitor. A feature is the attenuation circuit between the forward and feedback amplifiers, which provides an attenuation factor determining the integration capacitor's value for achieving the desired high-pass corner frequency. With configurable attenuation factors, the system can process different biopotential signals. Multiple analog front-end circuits can be used to process different signals simultaneously. The digital circuit includes a processor for signal processing, dynamic adjustment of attenuation factors, and anomaly detection. Additional components like switched capacitors, pseudo-resistors, and multiplexers can enhance the system's functionality. The design allows flexible, multi-parameter physiological monitoring with adjustable frequency responses and gain settings.

Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.

A multiplexer is disclosed. The multiplexer can include a multilayer piezoelectric substrate surface acoustic wave device that includes at least a portion of a transmission filter. The multiplexer can include a temperature compensated surface acoustic wave device that includes at least a portion of a reception filter. The reception filter is electrically connected to the transmission filter.

The invention provides an electric power secondary circuit multi-parameter intelligent detection system and method based on edge computing, the system comprises a composite sensing array, a self-adaptive probe system and an edge computing system, the composite sensing array comprises a plurality of sensors, the self-adaptive probe system comprises a multi-direction adjustable probe array, and the multi-direction adjustable probe array is connected with the edge computing system. The tail end of each probe in the multidirectional adjustable probe array is embedded into the permanent magnet, and the multidirectional adjustable probe array transmits the acquired electrical signals of the terminal strip to be tested to one or more of the plurality of sensors through the multiplexer; and the composite sensing array and the adaptive probe system are connected with the edge computing system, so that the detection efficiency is effectively improved.

The invention discloses an RRAM optical computing array reading circuit and method, and the circuit comprises an RRAM optical computing array, and a source line of each unit in the RRAM optical computing array is used for inputting a pulse signal to apply voltage bias; the pulse signal generation unit is used for generating a word line control signal and an RRAM optical calculation array unit bias voltage; the analog multiplexing control unit is used for selecting each subunit of the RRAM optical computing array; the pre-amplification and signal conversion unit is provided with a plurality of circuits and is used for detecting current changes of the photoelectric detection array subunits, converting the current changes into 0 / 1 signals and outputting the 0 / 1 signals to the FPGA control unit; the FPGA control unit is a system microcontroller and is used for controlling the pulse signal generation unit and the output analog multiplexer and processing signals of the pre-amplification and signal conversion unit. According to the invention, the circuit conversion problem caused by a large-span conductive state is solved, the circuit area is simplified, the system power consumption is reduced, and the applicability is high.

A controller wake-up circuit, method and related device, comprising: a controller, a wake-up source device and at least one multiplexer, the wake-up source device comprising a first type of wake-up source needing rapid wake-up; each input end of the multiplexer is correspondingly connected with one wake-up source; the interrupt signal output end of the first type of wake-up source is connected with the interrupt signal input end of the controller, the wake-up signal output end of the first type of wake-up source is connected with the input end of the multiplexer corresponding to the first type of wake-up source, and the first type of wake-up source outputs an interrupt signal to the controller through the interrupt signal output end. The controller receives the interrupt signal and outputs the polling wake-up signal to the multiplexer through the wake-up signal output end, the controller can be awakened by the interrupt signal, and then the signal source initiating wake-up is identified based on the polling result, so that the controller can be quickly awakened by the first type of signal source under the condition of low sleep power consumption.

The application relates to a non-volatile D flip-flop circuit. The non-volatile D flip-flop circuit formed by adopting the architecture mode of a latch circuit module, a self-enabled write circuit module, a non-volatile storage unit module, a read circuit module and a multiplexer module has only one working mode, so that the application has the characteristic of simple control timing. The self-enabled write circuit module and the non-volatile storage unit module arranged in the non-volatile D flip-flop circuit can realize real-time backup while reducing energy consumption.

To reduce power consumption and circuitry requirements, the following presents an “unmatched” data output architecture, in which the clock path does not mimic the data path. To provide proper data transfers in the data output path, the clock signal is tuned at points of the clock path, such as for data transfers from internal data buses to FIFOs and from the FIFO though the multiplexers to the input / output pads. An amount of timing offset is introduced in the generation of internal transfer clocks, which can be determined as part of a valid data window training process that can be performed by the controller, such as part of the power up process. To more quickly train the memory dies and determine the timing offset for an unmatched data output architecture, replica circuits for the data path and the clock path can be introduced on to the memory dies.

The invention discloses a firmware loading device, method and system, a programmable control device, a medium and a product, and relates to the technical field of computers, the device comprises the programmable control device and at least one multiplexer; the programmable control device is in communication connection with the at least one multiplexer, and the at least one multiplexer is further in communication connection with the target device and the multiple storage units. Target hardware configuration information corresponding to a target server is received, and a channel control signal is generated according to a preset mapping relation and the target hardware configuration information, so that a multiplexer opens a target communication channel under control, and target equipment reads and loads target firmware from a target storage unit. According to the firmware loading device based on the programmable control device and the multiplexer, the channel control signal is automatically generated by analyzing the hardware configuration information, automatic loading of the target equipment firmware is achieved, and the technical problems that firmware loading depends on manual operation and a server needs to be restarted are solved.

The present disclosure relates to ADC data processing circuitry for touch controllers. According to one embodiment, a signal processing circuit includes a coefficient accumulator and a dual multiplexer path for processing invalid ADC samples in a touch controller. When an ADC sample exceeds a saturation threshold, the circuit selects a zero value through one multiplexer while accumulating a coefficient through the other multiplexer path. Upon receiving a first valid sample, the circuit multiplies it with the accumulated coefficient and then resumes normal coefficient processing. This architecture enables continuous processing across multiple touch sensor channels without the need for buffering while maintaining mathematical equivalence through multiplication distribution rates.

The invention provides a receiving module, an operation method thereof and user equipment using the receiving module. The receive module includes a plurality of IF paths associated with the plurality of RF paths, at least one multiplexer (MUX), and at least one power detector (PD). Each IF path includes a transimpedance amplifier (TIA) and a low pass filter (LPF). The LPF is coupled to an output of the TIA. The at least one multiplexer is coupled to the plurality of IF paths. At least one power detector (PD) selectively couples at least two of the IF paths through at least one multiplexer to alternately detect signal strength of respective nodes between the TIA and the LPF in the respective IF paths. The at least two IF paths are associated with at least two RF paths of the plurality of RF paths having the same carrier frequency.

The invention relates to a display device and an electronic device. The display device includes: a display panel including a plurality of pixels; a gate driver that outputs a gate signal to the display panel; a data driver that generates a data voltage applied to the display panel; and a multiplexer block that outputs the data voltage to the display panel. The multiplexer block includes: an output control transistor including: a control electrode receiving an output control signal; a first electrode connected to the first data line; and a second electrode connected to the second data line.

Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.

A display pixel compensation circuit device using a dual-slope includes N channel multiplexers respectively coupled to sensing lines of corresponding channels; a sensing current conveyor configured to sense, on a target sensing line selected by control signals, a drain current of a target pixel's driving thin-film transistor; a noise current conveyor configured to sense, on an adjacent sensing line, panel noise, the adjacent sensing line being next to the target sensing line; and dual-slope error-detection circuitry configured to derive a pixel error from outputs of the two conveyors, convert the error into a sign value and an error value, and store these in a memory. In subsequent frames, the error value is arithmetically added to or subtracted from the digital pixel signal according to the sign value and supplied to respective channels, enabling real-time multi-bit correction with reduced silicon area and improved power efficiency.

The invention provides a communication transmission system and method for a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array), which relates to the field of communication transmission and comprises an I / O (Input / Output) control module, an internal DMA (Direct Memory Access) module and a data interleaving module, a GPIO multiplexing interface layer is arranged on the I / O control module; the GPIO multiplexing interface layer is in data and handshake signal interaction connection with an external FPGA (Field Programmable Gate Array); the output end of the transmission time and control module is in communication connection with the control multiplexer; the output end of the control multiplexer is respectively connected with the internal DMA module and the data interleaving module; the internal DMA module and the data interleaving module are connected through the I-FIFO module and the Q-FIFO module; and the data interleaving module is in data communication connection with the I / O control module. According to the invention, the CPU occupancy rate is obviously reduced, data preparation and transmission parallelization are realized, a hardware flow control and interruption mechanism is improved, the transmission reliability is guaranteed, the modular design is realized, and integration and expansion are easy.

The application provides a gating circuit and a multiplexer. The circuit comprises a first switch module, a second switch module, a voltage generating module, a first current generating module and a second current generating module, the second switch module is electrically connected with the first switch module, the voltage generating module, the first current generating module and the second current generating module, the voltage generating module is electrically connected with the first current generating module and the second current generating module, the first switch module and the second switch module are both used for being electrically connected with a positive electrode of a battery, the first switch module is used for being electrically connected with a battery output bus, and the second switch module is used for being electrically connected with a switch common bus. The gating circuit provided by the embodiment of the application effectively breaks through the speed bottleneck of the traditional scheme, greatly improves the overall switching frequency of the multiplexer and the real-time response of the system, and can meet the demand of the next generation battery management system for high-frequency and real-time voltage sampling.

The invention relates to a method and a device for preventing undesired triggering of short circuit or overcurrent protection. Methods, apparatus, systems, and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over-current protection. An example apparatus (500) includes an output terminal (108); a voltage detection device (506) coupled to the voltage detection input terminal and the output terminal (108) and comprising a voltage detection output (520) coupled to the first input terminal of the logic gate (508); a pulse expander (510) coupled between the logic gate (508) output (526) and the select node (528); a multiplexer (522) coupled to the select node (528) and configured to be coupled to the first protection circuit (512), the second protection circuit (514), and the driver (540); and a switch (530) coupled between the input terminal (524) and the output terminal (108) and including a switch gate terminal coupled to the driver (540).

A scan flip-flop configured to generate physically unclonable function (PUF) data according to the present disclosure includes a multiplexer configured to provide an internal signal through an input switch, a first latch circuit configured to latch the internal signal, wherein the first latch circuit comprises a first inverter, a second inverter, a first switch connected in parallel with the first inverter, and a second switch connected in series with the second inverter. Additionally, a second latch circuit configured to latch an output of the first latch circuit and output a latched value, wherein the second latch circuit comprises a third inverter, a fourth inverter, an output inverter connected in series with the third inverter, and a fourth switch connected in series with the fourth inverter. A third switch is configured to switch between the first latch circuit and the second latch circuit.