1395 results about "Muxponder" patented technology

Systems and methods for performing hardware approximation of functions are provided. In one example, a system comprises a controller, a plurality of multiplexors, configurable arithmetic circuits, and a mapping table that stores a set of function parameters. According to a mode of operations, the controller may configure the plurality of multiplexors to forward the set of function parameters or a subset of the function parameters to the arithmetic circuits to compute an approximation result. In a case where the subset of the function parameters is forwarded to the arithmetic circuits, the controller may configure the arithmetic circuits to perform post-processing, such as quantization, of the approximation result.

The invention provides a laser gas telemetering system capable of eliminating the influence of distance change, and aims to solve the problem of inaccurate concentration detection caused by different intensity and receiving quantity of optical signals received by a detector when the telemetering system is in different telemetering distances. Optical signals of different telemetering distances are converted into electric signals meeting detection requirements by automatically regulating and controlling the photoelectric conversion gain multiple, and the core is a pre-amplification circuit capable of regulating and controlling the gain multiple and an automatic gain control algorithm. A photoelectric conversion chip OPA380 and a multiplexer MAX4638 are selected to form the pre-amplification circuit capable of regulating and controlling the gain multiple, and the pre-amplification circuit is provided with eight different gain regulation and control gears. According to the automatic gain control algorithm, detection signals are identified and judged according to the voltage amplitude after photoelectric conversion, and the gain multiple of the pre-amplification circuit is regulated and controlled in real time. According to the invention, the detection accuracy can be improved, and guidance is provided for field application of the mobile telemetering system.

The embodiment of the invention provides a hardware control system, method and device, a storage medium and electronic equipment, and the system comprises a processor which is used for generating a hardware control signal of hardware equipment; the information distribution module is used for generating interface address information; the first end of the multiplexer is connected with the information distribution module, the second end of the multiplexer is connected with the processor, the third end of the multiplexer is connected with the receiving end of the interface switching module, and the multiplexer is used for conducting the first end and the third end under the condition that the first control signal is received so as to transmit interface address information; the first terminal is used for conducting a second terminal and a third terminal under the condition of receiving a second control signal so as to transmit a hardware control signal; and the output end of the interface switching module is connected with the plurality of interfaces. According to the method and the device, the problem of relatively low expandability of hardware equipment in related technologies is solved, so that the effect of improving the flexibility and expandability of the system is achieved.

An apparatus, including: a first multiplexer including inputs configured to receive an input data signal and a scan signal, and a select input configured to receive shift control signal; a first latch including an input coupled to an output of the first multiplexer, and a complementary (e.g., inverting) clock input configured to receive a clock signal; a second latch including an input coupled to the output of the first multiplexer, and a non-complementary clock input configured to receive the clock signal; and a second multiplexer including inputs coupled to outputs of the first and second latches, respectively, a select input configured to receive the clock signal, and an output configured to generate an output data or scan signal.

The invention discloses an anti-radiation hardening digital controlled oscillator, a clock data recovery circuit and equipment, and the digital controlled oscillator is characterized in that an anti-radiation hardening circuit unit is connected between a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), and comprises a voltage copying unit and a multiplexer; the voltage copying unit is used for copying a control voltage signal output by the digital-to-analog converter DAC, generating a copying voltage signal, sending the copying voltage signal to the multiplexer, and switching the output of the multiplexer from the control voltage signal to the copying voltage signal when the digital-to-analog converter DAC is subjected to single-particle bombardment. The DCO type clock data recovery circuit aims at solving the problem that a traditional DCO type clock data recovery circuit is prone to being affected by single particles when running in a radiation environment, single particle function interruption is generated, and consequently a space task fails, and the radiation hardening capacity of the DCO type clock data recovery circuit running in the radiation environment is improved.

A method and system is presented for utilizing an automation server and / or a traffic control manager in the content origination workflow to control a multiplexer, data carousel, and / or packager of an interactive television (iTV) system to synchronize the content (audio, video) with the interactive application data. Further, other aspects provide methods and systems for network ad insertion to generate iTV enhanced advertisements by placing a local ad splicer in the network to allow for splicing of both iTV enhanced advertisements and splicing of iTV applications into an MPEG-2 transport stream.

Devices, systems, and methods for sharing an image sensor data stream with an active alignment subsystem are provided. An example device includes an image sensor coupled to a first processor. The first processor is coupled to a multiplexer and the image sensor. The first processor is configured to receive an image stream from the image sensor, transmit the image stream to a second processor via the multiplexer operating in a first state, and transmit the image stream to at least one test port of the data capture device via the multiplexer operating in a second state. The multiplexer is configured to connect the second processor to the first processor when operating in the first state, and connect the at least one test port to the first processor when operating in the second state. Responsive to receiving an enable signal, the multiplexer operates in the second state, else the first state.

A display device includes a timing controlling circuit configured to generate image data, a data control signal and a gate control signal; a data driving circuit configured to generate a data signal using the image data and the data control signal and generate a mux signal using an offset signal, a high level voltage signal and the data signal; a gate driving circuit configured to generate gate signals, emission signals using the gate control signal; and a display panel including pixels that are configured to display an image using the data signal, the mux signal, the gate signals, and the emission signals, wherein the mux signal is one of the high level voltage signal and voltage that is a sum of the data signal and the offset signal, and the mux signal is supplied to a power line that is connected to a pixel included in the display panel.

Systems and devices for power multiplexing are described. A device can include a first power input circuit including a first power driver having a first gate that is configured to receive power from a first power input channel and output power to a power output channel. The device includes a second power input circuit including a second power driver having a second gate that is configured to receive power from a second power input channel and output power to the power output channel. The device includes a charge pump connected to the power output channel that generates an output having a voltage greater than a voltage on the power output channel. The device includes a switching circuit connected to the output of the charge pump that is configured to selectively control the first and second power input circuits to output power to the power output channel.

Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.

Aspects of this disclosure relate to bulk acoustic wave devices that include a first electrode, a second electrode, and a piezoelectric layer having a recess outside of the active region of the bulk acoustic wave device. The first electrode and the second electrode overlap and are on opposing sides of the piezoelectric layer throughout the active region. Related acoustic wave filters, multiplexers, radio frequency modules, radio frequency systems, wireless communication devices, methods of manufacture, and methods of filtering are disclosed.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

To provide an acoustic wave device suppressing an area, where an acoustic wave element can be formed, from becoming smaller.SOLUTION: An acoustic wave device 100 includes: a support substrate 10; a piezoelectric layer 11 provided on the support substrate 10; an acoustic wave element 20 provided on the piezoelectric layer 11; a frame body 30 provided, on the support substrate 10, to surround the acoustic wave element 20 as viewed from the top of the piezoelectric layer 11; a lid 40 provided on the frame body 30 while sandwiching a gap 15 together with the support substrate 10, and sealing the acoustic wave element 20 in the gap 15; and a columnar body 50 which is provided between a lower surface 41 of the lid 40 and an upper surface 17 of the piezoelectric layer 11 within the gap 15 and in which a space 16 that is a gap between the lower surface 41 of the lid 40 and the columnar body is formed.SELECTED DRAWING: Figure 1

A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.

A multiplexer includes first and second filters, a resin layer, and an electrically conductive layer. A pass band of the first filter is different from a pass band of the second filter. The first filter is in contact with an electrically conductive layer, and the second filter is not in contact with the electrically conductive layer. The second filter has a greater thermal resistance value than the first filter, and lowers the pass band in response to a temperature rise. A region of the piezoelectric substrate closer to the first filter is a first region, and a region of the piezoelectric substrate farther from the first filter is a second region. Areas in the first and second regions where an acoustic wave resonator included in a parallel-arm circuit is provided are first and second areas. The second area is greater than the first area.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

A switched-element digital-to-analog converter (DAC) circuit for use, for example, in a successive-approximation register, SAR, analog-to-digital converter, ADC. The DAC circuit comprises a pool of unary circuit elements (410), each having a common nominal weighting value, and switching (420) and multiplexer (430) arrangements configured so that each unary circuit element (410) in the pool can be independently associated with any one of two or more bits of the switched-element DAC.

An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.

An integrated circuit device includes a multiplexor and multiple receivers for high-speed data communication interfaces. The multiplexor includes multiple signal inputs, a selector input, and a signal output. Each receiver includes a differential data signal input including a positive signal input and a negative signal input, a first termination resistor to terminate the positive signal input to a reference voltage node, a second termination resistor to terminate the negative signal input to the reference voltage node, and a noise measurement node to detect common mode noise at the reference voltage node, the noise measurement node coupled to an associated one of the signal inputs.

Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.

Certain aspects of the present disclosure are directed towards a configurable Fourier transform circuit. The circuit includes a first input Fourier transform component having a first set of multiplexers, wherein the first input Fourier transform component is configurable to perform Fourier transforms of different sizes and different number of channels by controlling the first set of multiplexers; a first set of multiplier circuits having inputs coupled to outputs of the first input Fourier transform component; and a first output Fourier transform component having inputs coupled to outputs of the first set of multiplier circuits and having a second set of multiplexers, wherein the first output Fourier transform component is configurable to perform Fourier transforms of different sizes and different number of channels by controlling the second set of multiplexers.

The embodiment of the invention discloses a vehicle controller awakening system, method and device and a vehicle, and the system comprises a multiplexer which comprises a first part pin, a second part pin, an output pin and a channel selection control pin; one input pin in the first part of pins and one input pin in the second part of pins are connected to a CAN bus and are used for receiving a CAN wake-up signal, and the other input pins are connected to other wake-up sources respectively; the output pin is connected with the input pin of the controller; the controller comprises a control signal output pin and an input pin, the control signal output pin is connected with the channel selection control pin, and the controller is used for controlling wake-up signal detection for the multiplexer through control signal polling based on polling cycles and polling the first part of pins and the second part of pins through two polling cycles respectively, and when the wake-up signal is received, starting is carried out. According to the embodiment of the invention, the rapid wake-up requirement of the CAN wake-up signal is met under the condition that the sleep power consumption of the whole vehicle is met.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

The invention provides an FIFO (First In First Out) data reading method, device, system, equipment and medium, the method comprises the following steps: when a data reading request is triggered, calculating a read address according to a data reading address carried in the data reading request; the read address is used for representing a value when the read address register is about to be updated in the previous clock period; selecting target data from the next beat of data of the register file or the beat-to-write data through the multiplexer according to the beat-to-read address; the next beat of data of the register file refers to data stored in the register file in the next clock period; the current data are data which are currently written into a first-in first-out (FIFO) queue; and performing a beating operation on the target data through a register, and performing a reading operation through a data reading interface of the FIFO queue. According to the scheme, the overall delay of data reading is reduced, the running speed and performance of the whole system are improved, and then the running speed of a chip is increased.

A system includes a plurality of application processors (APs), a plurality of flash memory devices associated with the plurality of APs, and a plurality of multiplexers, each to selectively couple a flash memory device of the plurality of flash memory devices to an AP of the plurality of APs. A controller is operatively coupled to the plurality of multiplexers and provides a trusted execution environment to execute a virtual root of trust (vROT) application for each respective AP of the plurality of APs. Each vROT application accesses a corresponding one or more of the plurality of flash memory devices via a corresponding one or more of the plurality of multiplexers.

Devices, systems, and methods for reconfigurable butterfly architectures are provided. A reconfigurable butterfly operator circuit includes a single multiplier configured to receive a first variable and a twiddle factor and produce a product, first and second modular subtractors coupled to the multiplier, the first modular subtractor coupled to receive input coefficients and provide a modular difference, and the second modular subtractor coupled to receive the product, a modular adder coupled to receive the input coefficients and provide a modular sum, and multiplexers coupled to (i) provide the input coefficients to the modular adder, (ii) provide the first variable and the twiddle factor to the multiplier, (iii) and receive the modular difference from the first modular subtractor, respectively, each of the multiplexers coupled to receive a control signal that selects whether the circuit is configured as a Gentleman-Sande butterfly operator circuit or a Cooley-Tukey butterfly operator circuit.

According to one embodiment, a transmitter device includes: a digital processing circuit generating n-phase first and second digital signals, the second digital signal shifted from the first digital signal by a first phase; a delay circuit generating an n-phase second clock signal shifted from an n-phase first clock signal by a second phase being 0 or more and being the first phase or less; a first multiplexer converting the first digital signal into a single-phase third digital signal based on the first clock signal; a second multiplexer converting the second digital signal into a single-phase fourth digital signal shifted from the third digital signal by a sum of the first phase and the second phase based on the second clock signal; and a first driver outputting a composite signal of first and second analog signals based on the third and fourth digital signals.

A display device is provided. The display device includes a substrate including a touch sensing area and a touch peripheral area disposed near the touch sensing area; a circuit layer disposed on the substrate; a touch sensor layer disposed on the circuit layer, including N number of touch sensing electrodes arranged in the touch sensing area in a first direction and a second direction, and N number of sensing transfer lines electrically connected to the N number of touch sensing electrodes, respectively; a multiplexer disposed in the touch peripheral area and electrically connected between the N number of sensing transfer lines and a touch driving circuit; and an electrostatic shielding layer overlapping with the multiplexer. The N number of sensing transfer lines extend from the N number of touch sensing electrodes to the multiplexer. Among the N number of sensing transfer lines, 2M number of sensing transfer lines selected by the multiplexer are electrically connected to the touch driving circuit. Each of N and M is a natural number and M is smaller than N.

An apparatus includes a first image processing path associated with a first image sensor and a second image processing path associated with a second image sensor. The apparatus further includes a multiplexer (MUX). The MUX is configured to provide data from the first image sensor to the second image processing path in accordance with a resource availability parameter associated with the second image processing path satisfying a resource availability condition.