1763 results about "Muxponder" patented technology

A communication network includes first switches interconnected with second switches. Each first switch includes a first integrated circuit (IC) switch chip, downlink ports, and uplink ports. Each second switch includes ports coupled to at least one uplink port of each of the first switches, and a second IC switch chip in an IC package. To permit each second IC switch chip to forward packets amongst a large number of first switches and to reduce a number of external interconnects of the IC package, each second IC switch chip includes sets of multiplexer / demultiplexer circuitry, each multiplexer / demultiplexer circuitry being coupled between an external interconnect, and a set of multiple internal network interfaces of the second IC switch chip. The multiplexer / demultiplexer circuitry demultiplexes a data stream from the external interconnect to multiple internal network interfaces, and multiplexes multiple data streams from the multiple internal network interfaces to the external interconnect.

A vehicular vision system includes a plurality of cameras disposed at a vehicle, a multiplexor operable to aggregate the image data from the cameras into aggregated image data, and an interior rearview mirror assembly disposed at the vehicle remote from the multiplexor. The interior rearview mirror assembly includes a mirror head adjustably disposed at a mounting base configured to attach at an interior portion of the vehicle. The mirror head includes a mirror casing and a mirror reflective element. The interior rearview mirror assembly includes an image processor for processing image data. The interior rearview mirror assembly includes a display for displaying images captured by the cameras. The image processor, responsive to receiving the aggregated image data transferred from the multiplexor, displays at the video display video images derived at least in part from the aggregated image data.

An application specific integrated circuit (ASIC) for computing a convolutional neural network (CNN) has a first input bus that receives a stream of ordered values from an array, each location in the array having one or more channels, and a plurality of kernel processing blocks that receive inputs through a configurable multiplexer. The arrangement and connection of the kernel processing blocks and the bus enable the ASIC to operate as a pipeline system and transmit the output stream in a manner synchronized with the input stream.

A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

Techniques for fully homomorphic encryption are described. In some examples, a register file to store polynomials is coupled to a butterfly compute path. The butterfly compute path includes a multiplier coupled to a first input and a second input to multiply the first and second input to, when enabled, generate a multiplication output, a first multiplexer coupled to an output of the multiplier and to the first input to output a selection between the output of the multiplier and the first input, an adder to add, when enabled, a third input to the selected output of the first multiplexer, a subtractor to subtract, when enabled, an output of the multiplier from the third input, and a second multiplexer coupled to an output of the multiplier and to the first input to, when enabled, output a selection between the output of the multiplier and the subtractor.

A systolic array can implement an architecture tailored to perform matrix multiplications on sparse matrices. Each processing element in the systolic array may include a register configured to store a value, and a multiplexor configured to select an input element from multiple input data buses based on metadata associated with the value. Each processing element may also include a multiplier configured to multiply the selected input element with the value to generate a multiplication result, and an adder configured to add the multiplication result to a partial sum input to generate a partial sum output.

The utility model relates to the technical field of servers, in particular to a server power supply heat dissipation device, which comprises a CPLD (complex programmable logic device) arranged on a power supply backboard and connected with a BMC (baseboard management controller) through an I2C (inter-integrated circuit) link; the CPLD is connected with a first port of the multiplexer, and the BMC is connected with a second port of the multiplexer; a third port of the multiplexer is connected with the power management bus; the CPLD is connected with a control pin of the multiplexer so as to control the multiplexer to communicate the first port to the third port or communicate the second port to the third port; the power management bus is connected with a voltage sensor and a current sensor which are arranged at the downstream of the power converter; and the CPLD is connected with the power supply fan driving chip.

A PCIe clock detection circuit includes a clock detector, a clock receiver, a counter coupled to the clock receiver, a multiplexer coupled to the counter, and an AND gate coupled to the clock detector and the multiplexer. The clock detector is used to detect amplitude of a clock signal and generate a clock detection signal accordingly. The clock receiver is used to generate a reference clock signal according to the clock signal. The counter is used to generate a counter signal according to the reference clock signal. The multiplexer is used to generate a MUX output signal according to the counter signal and a reference signal. The AND gate is used to generate a clock detection output signal according to the clock detection signal and the MUX output signal.

A filter device includes a filter circuit including first and second terminals and series arm resonators along a series arm connecting the first terminal and the second terminal, and an additional circuit connected in parallel at least some of the series arm resonators. The additional circuit includes first, second, and third interdigital transducer electrodes. The first interdigital transducer electrode is connected to a first node at one end portion of a series arm resonator having a lowest anti-resonant frequency of the series arm resonators, the second interdigital transducer electrode is connected to a second node having a potential different from a potential of the first node, the third interdigital transducer electrode is connected to a third node having a potential different from the potentials of the first and second nodes, and the first and second nodes are closer to the first terminal than the third node.

The invention provides a core particle and a test method thereof, and the core particle comprises a home terminal generator which is used for generating and sending a test code to a sending channel for transmission; wherein one test code is transmitted through one sending channel, and the number of the test codes is the same as that of the sending channels; the home terminal multiplexer is used for receiving the detection code through the receiving channel; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels; and the home terminal checker is used for generating a corresponding check code according to the received detection code and checking the corresponding detection code through the check code, if the check is successful, the transmission channel corresponding to the detection code is unobstructed, otherwise, the transmission channel corresponding to the detection code is transmission fault. According to the core particle and the test method thereof provided by the invention, the requirements of a serial transmission test of a single channel and a parallel transmission test of a plurality of transmission channels can be met.

Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and / or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and / or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.

Systems and methods for performing hardware approximation of functions are provided. In one example, a system comprises a controller, a plurality of multiplexors, configurable arithmetic circuits, and a mapping table that stores a set of function parameters. According to a mode of operations, the controller may configure the plurality of multiplexors to forward the set of function parameters or a subset of the function parameters to the arithmetic circuits to compute an approximation result. In a case where the subset of the function parameters is forwarded to the arithmetic circuits, the controller may configure the arithmetic circuits to perform post-processing, such as quantization, of the approximation result.

The invention provides a laser gas telemetering system capable of eliminating the influence of distance change, and aims to solve the problem of inaccurate concentration detection caused by different intensity and receiving quantity of optical signals received by a detector when the telemetering system is in different telemetering distances. Optical signals of different telemetering distances are converted into electric signals meeting detection requirements by automatically regulating and controlling the photoelectric conversion gain multiple, and the core is a pre-amplification circuit capable of regulating and controlling the gain multiple and an automatic gain control algorithm. A photoelectric conversion chip OPA380 and a multiplexer MAX4638 are selected to form the pre-amplification circuit capable of regulating and controlling the gain multiple, and the pre-amplification circuit is provided with eight different gain regulation and control gears. According to the automatic gain control algorithm, detection signals are identified and judged according to the voltage amplitude after photoelectric conversion, and the gain multiple of the pre-amplification circuit is regulated and controlled in real time. According to the invention, the detection accuracy can be improved, and guidance is provided for field application of the mobile telemetering system.

The embodiment of the invention provides a hardware control system, method and device, a storage medium and electronic equipment, and the system comprises a processor which is used for generating a hardware control signal of hardware equipment; the information distribution module is used for generating interface address information; the first end of the multiplexer is connected with the information distribution module, the second end of the multiplexer is connected with the processor, the third end of the multiplexer is connected with the receiving end of the interface switching module, and the multiplexer is used for conducting the first end and the third end under the condition that the first control signal is received so as to transmit interface address information; the first terminal is used for conducting a second terminal and a third terminal under the condition of receiving a second control signal so as to transmit a hardware control signal; and the output end of the interface switching module is connected with the plurality of interfaces. According to the method and the device, the problem of relatively low expandability of hardware equipment in related technologies is solved, so that the effect of improving the flexibility and expandability of the system is achieved.

The invention discloses an automatic traversal test circuit, an automatic traversal test device, an interrupt request test method and an interrupt request test system, and the automatic traversal test circuit comprises a multiplexer which comprises N test pins, and the total number N of the test pins is the same as the number of to-be-tested interfaces of a to-be-tested chip; the chip to be tested and the multiplexer form multi-channel connection; the multiplexer further comprises at least one first control interface and a selection input end; the truth value state of the first control interface is changed under the action of the first control instruction, so that the selection input end is controlled to select a path corresponding to the target test pin to be conducted. According to the invention, the multichannel multiplexer analog switch is added in the test circuit to replace the function of manually plugging and switching pins. The multi-interface interrupt request automatic test of the chip to be tested can be realized.

An apparatus, including: a first multiplexer including inputs configured to receive an input data signal and a scan signal, and a select input configured to receive shift control signal; a first latch including an input coupled to an output of the first multiplexer, and a complementary (e.g., inverting) clock input configured to receive a clock signal; a second latch including an input coupled to the output of the first multiplexer, and a non-complementary clock input configured to receive the clock signal; and a second multiplexer including inputs coupled to outputs of the first and second latches, respectively, a select input configured to receive the clock signal, and an output configured to generate an output data or scan signal.

The invention discloses an anti-radiation hardening digital controlled oscillator, a clock data recovery circuit and equipment, and the digital controlled oscillator is characterized in that an anti-radiation hardening circuit unit is connected between a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), and comprises a voltage copying unit and a multiplexer; the voltage copying unit is used for copying a control voltage signal output by the digital-to-analog converter DAC, generating a copying voltage signal, sending the copying voltage signal to the multiplexer, and switching the output of the multiplexer from the control voltage signal to the copying voltage signal when the digital-to-analog converter DAC is subjected to single-particle bombardment. The DCO type clock data recovery circuit aims at solving the problem that a traditional DCO type clock data recovery circuit is prone to being affected by single particles when running in a radiation environment, single particle function interruption is generated, and consequently a space task fails, and the radiation hardening capacity of the DCO type clock data recovery circuit running in the radiation environment is improved.

The embodiment of the invention provides a calculation core and a data processing method, relates to the technical field of chips, and solves the problems that an existing storage and calculation integrated device is low in calculation resource utilization rate and high in hardware cost. According to the specific scheme, a calculation core comprises a plurality of convolution circuits and a plurality of multiplexers, each multiplexer comprises an output end and at least two input ends, the output ends of the multiplexers correspond to the input ends of the convolution circuits in a one-to-one mode, the output end of each convolution circuit in the convolution circuits is coupled with the input ends of the L multiplexers, l is an integer greater than or equal to 2, at least one of the L multiplexers further comprises an external data output end, and at least one of the L convolution circuits corresponding to the L multiplexers further comprises an external data input end. Wherein the multiplexer is used for conducting the output end of at least one convolution circuit coupled with the multiplexer to the output end of the multiplexer.

A method and system is presented for utilizing an automation server and / or a traffic control manager in the content origination workflow to control a multiplexer, data carousel, and / or packager of an interactive television (iTV) system to synchronize the content (audio, video) with the interactive application data. Further, other aspects provide methods and systems for network ad insertion to generate iTV enhanced advertisements by placing a local ad splicer in the network to allow for splicing of both iTV enhanced advertisements and splicing of iTV applications into an MPEG-2 transport stream.

Devices, systems, and methods for sharing an image sensor data stream with an active alignment subsystem are provided. An example device includes an image sensor coupled to a first processor. The first processor is coupled to a multiplexer and the image sensor. The first processor is configured to receive an image stream from the image sensor, transmit the image stream to a second processor via the multiplexer operating in a first state, and transmit the image stream to at least one test port of the data capture device via the multiplexer operating in a second state. The multiplexer is configured to connect the second processor to the first processor when operating in the first state, and connect the at least one test port to the first processor when operating in the second state. Responsive to receiving an enable signal, the multiplexer operates in the second state, else the first state.

A display device includes a timing controlling circuit configured to generate image data, a data control signal and a gate control signal; a data driving circuit configured to generate a data signal using the image data and the data control signal and generate a mux signal using an offset signal, a high level voltage signal and the data signal; a gate driving circuit configured to generate gate signals, emission signals using the gate control signal; and a display panel including pixels that are configured to display an image using the data signal, the mux signal, the gate signals, and the emission signals, wherein the mux signal is one of the high level voltage signal and voltage that is a sum of the data signal and the offset signal, and the mux signal is supplied to a power line that is connected to a pixel included in the display panel.

Systems and devices for power multiplexing are described. A device can include a first power input circuit including a first power driver having a first gate that is configured to receive power from a first power input channel and output power to a power output channel. The device includes a second power input circuit including a second power driver having a second gate that is configured to receive power from a second power input channel and output power to the power output channel. The device includes a charge pump connected to the power output channel that generates an output having a voltage greater than a voltage on the power output channel. The device includes a switching circuit connected to the output of the charge pump that is configured to selectively control the first and second power input circuits to output power to the power output channel.

A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal.

A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.

Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.

Aspects of this disclosure relate to bulk acoustic wave devices that include a first electrode, a second electrode, and a piezoelectric layer having a recess outside of the active region of the bulk acoustic wave device. The first electrode and the second electrode overlap and are on opposing sides of the piezoelectric layer throughout the active region. Related acoustic wave filters, multiplexers, radio frequency modules, radio frequency systems, wireless communication devices, methods of manufacture, and methods of filtering are disclosed.

An acoustic wave filter includes a divided resonator group and series arm resonators in a path connecting an input-output terminal and an input-output terminal to each other and parallel arm resonators each between a node in the path described above and the ground. The divided resonator group, the series arm resonators, and the parallel arm resonators each include an acoustic wave resonator including an interdigital transducer electrode on a piezoelectric substrate. The divided resonator group includes divided resonators coupled in series with each other. The IDT electrode included in the divided resonator includes a first withdrawal electrode. The IDT electrode included in the divided resonator includes a second withdrawal electrode different from the first withdrawal electrode with respect to the electrode finger structure.

A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined asNM,where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.

A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.