53 results about "Field-programmable object array" patented technology

A field programmable object array integrated circuit has video data compression capability. The integrated circuit comprises an array of programmable objects and a video compression co-processor communicatively coupled to the array of objects. The video compression co-processor comprises a set of search engines and a subpixel engine. The subpixel engine can interpolate subpixels from integer pixels and shift the integer pixels by a predetermined number of subpixels. The search engines can perform a plurality of sum of absolute differences (SAD) computations between search window pixels and macroblock pixels to locate the best SAD value using either integer pixels and/or the interpolated subpixels.

The embodiment of the invention provides a method, a device and a system for testing the field programmable gate array, the method of which comprises that: the control chip receives the FPGA (field programmable gate array) and test the data of interface format recognized by the control chip output after the transformer of the related information; the control chip sends the data of interface format which can be recognized to the test computer; the control chip receives the control information sent by the test computer; the control chip sends the control information to FPGA. The embodiment of the invention solves the problems that the online test and remote test can not be achieved due to the limit of JTAG interface and the JTAG cable in length in prior art by the control chip on the veneer and the external communication interface.

A field-programmable object array integrated circuit employs a course gain architecture comprising a core array of highly optimized silicon objects that are individually programmed and synchronously connected via high performance parallel communications structures permitting the user to configure the device to implement a variety of very high performance algorithms. The high level functions available in the objects combined with the unique interconnect structures enables performance superior to existing field programmable solutions while maintaining and enhancing the flexibility. A consistent peripheral “donut” structure around the core of each object makes them interchangeable to build up complex circuits without redesign of standard objects.

The invention belongs to the technical field of an integrated circuit, in particular to a traversal test method of a configurable logic block (CLB) of a field programmable gate array (FPGA) based on a look-up table (LUT) structure. The method comprises: carrying out traversal tests on the single-point fault of an LUT, testing the multiple-point fault of the LUT, carrying out traversal tests on a distributive RAM, assigning the initial value of the trigger to be 0 or 1, carrying out level fixing on a setting terminal and a resetting terminal, leading the enabling to be invalid, and carrying out traversal tests on setting, resetting and enabling and the like. The invention can complete all the tests on the confronting manufacturing of all the CLBs in FPGA chips, and can cover all the basic logic devices, programmable code points and internal interconnection resources inside the CLBs. The configuration times, configuration difficulty and test time required by the test can all be greatly optimized.

The invention discloses a development board of a network multi-core processor on a test board based on four field programmable gate arrays (FPGA). Four FPGA chips are interconnected to form an entire interconnected structure; each FPGA chip is provided with a GTX transmission channel and a GPIO transmission channel which are respectively connected with the other three FPGA chips; and each FPGA chip is provided with a power management module, a board level clock drive module and a memory system. Date input and output ports of the development board are respectively arranged on the second and the fourth FPGA chips; and the data input and output ports are full-duplex differential 2.5Gbps fiber interfaces. The emulated memory bandwidth of the development board reaches 759.2Gbps which is far from being achieved by the current circuit designs of the other development boards with multiple FPGAs; with the interconnection of the chips, the throughput is above 30Gbps; and the development board provides enough hardware resource for FPGA hardware designers so as to test and realize the design of a prototype chip of a VL (very large) multi-core processor based on NoC.

A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a controller. The array of objects is designed to operate at an operational clock speed during non-testing operation, wherein the design of the objects is not constrained to require within an object extra circuitry not essential to non-testing operation to facilitate built-in self-testing. The interfaces are connected to the objects to enable communication with the objects and to thereby facilitate built-in self-testing of the objects. The controller causes a selected subset of the objects to be activated and configured for testing, to stimulate the selected subset for some time with an input test pattern delivered via the interfaces while the selected subset of objects operates at the operational clock speed, and to observe a response of the selected subset of objects.

The invention relates to a universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays). The universal dynamic aging system for the Virtex-5 FPGAs includes an upper computer, a program-controlled power source, a programmer, an aging signal board, a high temperature test box, an aging test board and an aging FPGA; the upper computer generates a power-on instruction, sends an aging FPGA configuration bit stream, receives and displays aging response data; the program-controlled power source supplies power; the programmer completes the bit stream configuration of the aging FPGA; the aging signal board generates aging excitation signals; the high temperature test box adjusts the temperature of the aging signal board and the aging FPGA; and the aging FPGA includes a clock management module, a system monitoring module, a clock gating module and an aging function module. According to the universal dynamic aging system for the Virtex-5 FPGAs (field programmable gate arrays), the status of the aging function module is automatically adjusted according to the temperature of a chip, and aging response data are generated.

The invention discloses a field programmable gate array (FPGA) online configuration method. The method comprises the following steps of: connecting a central processing unit (CPU) and a storage in which FPGA configuration data is stored, and FPGA respectively, and connecting a general purpose input/output (GPIO) of the CPU and a pin of load data of the FPGA; retrieving configuration data from the storage by the CPU; and finishing loading the configuration data by controlling the time sequence relationship of the GPIO in a passive serial (PS) mode. By the method, cost can be reduced in the design, expensive non-erasable and erasable configuration chips can be replaced, the confidentiality and upgradeability requirements of the design can be met, and the updating of product software can be finished at any time by easily copying a file.

The invention provides a system and a method for collaborative power management of an FPGA (field programmable gata array) chip and a BMC (baseboard management controller) chip used on an ATCA (advanced telecom computing architecture) blade. The system comprises the FPGA chip, the BMC chip, N power modules and a cabinet manager. Enable pins and Power Good pins of the N power modules are respectively connected with IO (in-out)pins of the FPGA chip, output ends of the N power modules are all connected on an AD (analog-digital) sampling interface of the BMC chip, and the FPGA chip and the BMC chip are communicated through a I2C (inter-integrated circuit) bus. The cabinet manager and the BMC chip are connected bidirectionally. By the aid of the system and the method, whether or not power-on of the FPGA chip is normal is indicated according to state of an LED (light-emitting diode) indicator light, searching power failure by using hardware tools can be further avoided as far as possible, so that troubleshooting becomes simple and high-efficient.

The invention relates to a device for field programmable gate array (FPGA) single event effect dynamic fault testing. The device comprises a control circuit module (11), an upper computer control module (12), a controllable pulse laser module (15) and a three-dimensional mobile module (16), wherein the three-dimensional mobile module (16) is used for installing a tested FPGA device (13) to be tested during the testing; the upper computer control module (12) is connected with the control circuit module (11), and the control circuit module (11) is connected to the controllable pulse laser module (15). During the testing, the control circuit module (11) is further connected with the tested FPGA device (13) and a contrast tested FPGA device (14) corresponding to the tested FPGA device (13).

The invention discloses a system for debugging FPGA (field programmable gate array) in real time, comprising an SPI (serial peripheral interface) transceiving module, an SFR (special function register) decoding module, a data storing unit and a logic detection unit, wherein the SPI transceiving module is used for receiving external data to form a detection command and detection data and sending an internal detection result and internal storage data; the SFR decoding module is used for decoding a register command with special functions; the data storing unit is used for storing specified sampled data; and the logic detection unit is used for being connected with at least one group of logic units to be detected and carrying out real-time verification to obtain a verification result; and the modules and the units are sequentially connected for carrying out data communication. A real-time debugging method of the system comprises the following steps that: the SPI transceiving module receives data of a monitoring system, the data received by the SPI transceiving module is converted into a detection instruction or detection data by virtue of the SFR module, is stored by the data storing unit and then is sent to the logic detection unit, the logic detection unit judges the logic units to be detected, and judgement data and result are stored and then are transmitted by the SPI transceiving module. The system disclosed by the invention takes an SPI bus protocol as a protocol used for realizing data interaction between a basic debugging device and equipment, and high-speed product debugging and verifying design and dynamic check debugging are realized.

Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal processing accelerators (SPAs) and an array of network nodes. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input signals from the FPGA. The array of network nodes controllably route the input signals to the array of SPAs.

A user register state capture circuit adopting a single-event hardened FPGA (field programmable gate array) comprises a user register, a transistor M3, a transistor M4, an SRAM (static random-access memory) storage unit and a capture signal generation circuit, wherein the transistor M3 and the transistor M4 are arranged between the user register and the SRAM storage unit; the capture signal generation circuit generates an output signal CAPTURE, controls conduction of the transistor M3 and the transistor M4 and realizes data capture readback. Compared with the prior art, the state capture circuit has the advantages that through capture readback operation, dynamic partial reconfiguration can be performed if the condition that configuration bit stream stored in the CSRAM (custom SRAM) has single-event upset is discovered, corresponding logic can be reset if the state of the SRAM storage unit for storing the captured user register state in the CSRAM has an error, so that the single-event upset accumulation effect of an FPGA chip is reduced remarkably.

The invention discloses an FPGA (field programmable gate array) and CPU (central processing unit) SDIO (secure digital input output) communication interface implementation method and device. An FPGA serves as a slave device without an IP (interface protocol) core, customizes an SDIO communication interface and adopts an SDIO communication protocol. A CPU serves as a master device, acquires a hybrid device drive process matched with an SDIO device and finishes drive registration and loading. The CPU can register one hybrid device in a drive, so that an application program can access the hybriddevice. The communication interface is applicable to the CPU and the FPGA in most design, and can meet the communication requirements of non-high-speed interfaces.

The invention provides a field programmable gate array (FPGA)-based common object request broker architecture (CORBA) communication device, which comprises a master resolution module, a master packaging module, an interconnect module, a plurality of resolution sub-modules and a plurality of packaging sub-modules, wherein each resolution sub-module and each packaging sub-module correspond to each application module on an FPGA; the master resolution module performs data information exchange with other processors by external data interfaces, and transmits data information to the application modules by the interconnect module and the resolution sub-modules; and each application module transmits the data information to the master packaging module by corresponding packaging sub-modules and the interconnect module. The FPGA-based CORBA communication device is designed, implemented and run on the FPGA, is free from the limitations of the specific type of the FPGA, and can realize direct CORBAcommunication between the application modules on the FPGA and the application modules on the other processors without running any adaptor module and agent module on a general purpose processor.

The invention discloses a chip testing system and method based on a field programmable gata array (fpga), and relates to the technical field of chip testing. The chip testing system based on the fpgacomprises a PC terminal and the fpga, wherein the PC terminal is used for applying a test incentive instruction and sending the test incentive instruction to the fpga; and the fpga is used for receiving the test incentive instruction, parsing the test incentive instruction and sending the test incentive instruction to a chip, the fpga can judge whether a test type is an IO test or a register test,the IO test comprises configuration of a chip test mode and vertical pull operation of chip IO, and the register test comprises read-write operation of a chip register. The chip testing system and method support two test types of IO and register read-write operation, users can debug test codes online, compilation time is short, and the chip testing system and method can flexibly meet various chiptesting requirements.

A method using an FPGA (field programmable gate array) for controlling DSP (digital signal processor) program load running, which includes the steps: 1 selecting a chip with a power output enable end EN to supply power to a DSP; 2 connecting a certain IO (input/output) pin of the FPGA to the enable end EN, and temporarily naming the IO pin as IO pin CONTRL_EN; and 3 editing FPGA codes, and enabling the IO pin CONTRL_EN to continuously output low level after FPGA loading is completed. The method has the advantages of simplicity, capability of leading design and debugging of a circuit to be simpler and easier and high flexibility and reliability. Particularly when a plurality of DSPs are connected with the FPGA, the method is convenient for arbitrarily defining the electrifying load sequence and delay time of the DSPs, which cannot be realized by any special chips.

The invention belongs to the technical field of design and development of circuits, and discloses a guidable FPGA (field programmable gate array) configuration circuit. The guidable FPGA configuration circuit comprises a serial FLASH memory, wherein FCLK, FnCS, FMOSI and FMIS interfaces of the serial FLASH memory are connected with an external processor; the configuration information is written into the serial FLASH memory via the interfaces; CLK and SNA interfaces are connected with the external processor; the guiding information is set via the interfaces; nConfig, DI, DCLK, nCS and DO are connected with the FPGA. The guidable FPGA configuration circuit has the advantages that if the capacity of the FLASH memory is enough, multiple copies of FPGA configuration information can be stored in one FLASH chip, so that the number of chips can be reduced; the external processor can force the FPGA to reconfigure via CLK and SDA, so as to realize the heat exchange of the FPGA functions.

The disclosure relates to a security RAM block with multiple partitions. Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message authentication codes (MACs) for further controlling access to data in each partition.

The invention relates to a BLOCK RAM (Random Access Memory) cascade structure of a field programmable gate array FPGA. The BLOCK RAM cascade structure comprises a column of SRAM18K (Static Random Access Memory) units, wherein two adjacent SRAM18K units in one column of the SRAM18K units are in address cascade or data parallel connection through a first stage ASIC (Application Specific Integrated Circuit) cascade logic routing architecture, and one BLOCK RAM unit is formed, and the like, taking wiring of a CLK REGION in the FPGA as the limit, two adjacent BLOCK RAM units are cascaded and one BRAM GROUP unit is formed; and two adjacent BRAM GROUP units are cascaded to form one BRAM COLUMN unit, and a BLOCK RAM cascade structure with the required address depth and data width can be formed. The BLOCK RAM cascade structure of the field programmable gate array FPGA provided by the invention can realize a memory cell RAM with the required address depth and data width, simplify a software algorithm and save peripheral wiring resources.

The embodiment of the invention provides a data communication method between processors and FPGA (field programmable gate array) equipment. Data output from a first processor is read by FPGA; an interruption signal is written into a second processor; and the second processor reads data which is output from the first processor and is read from the FPGA. Compared with the prior art that the communication mode between the processors is realized by a double-port RAM (random-access memory) chip, the communication method provided by the invention has the characteristics that data can be exchanged in time, logic realization is more flexible, and the cost performance is higher.