Universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays)

A sophisticated and dynamic technology, applied in digital circuit testing, electronic circuit testing, etc., can solve the problems of large fluctuation range, FPGA over-temperature operation, low measurement accuracy, etc., to achieve high temperature control accuracy, standardized interface, universal strong effect

CN106569124AInactive Publication Date: 2017-04-19CHINA ACADEMY OF SPACE TECHNOLOGY
11 Cites 16 Cited by

Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2017-04-19
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
Patent Text Reader

Abstract

The invention relates to a universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays). The universal dynamic aging system for the Virtex-5 FPGAs includes an upper computer, a program-controlled power source, a programmer, an aging signal board, a high temperature test box, an aging test board and an aging FPGA; the upper computer generates a power-on instruction, sends an aging FPGA configuration bit stream, receives and displays aging response data; the program-controlled power source supplies power; the programmer completes the bit stream configuration of the aging FPGA; the aging signal board generates aging excitation signals; the high temperature test box adjusts the temperature of the aging signal board and the aging FPGA; and the aging FPGA includes a clock management module, a system monitoring module, a clock gating module and an aging function module. According to the universal dynamic aging system for the Virtex-5 FPGAs (field programmable gate arrays), the status of the aging function module is automatically adjusted according to the temperature of a chip, and aging response data are generated.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The present invention relates to a general dynamic burn-in system for Virtex-5 FPGAs, in particular to a dynamic burn-in test applicable to all types of FPGAs of the Virtex-5 series and capable of real-time monitoring of the junction temperature of burn-in FPGA chips. A system of monitoring and dynamic regulation. Background technique

[0002] Virtex-5 is the fifth-generation FPGA product of Xilinx's Virtex series. There are generally two ways to choose FPGA for aerospace models: one is to purchase aerospace-grade (V-grade) products and use them after passing the test; the other is to purchase low-grade FPGAs. (M-level or I-level) products are used after upgrading and screening. From the analysis of availability and selection cost, the latter method is more advantageous. Dynamic burn-in is an important test item in low-level FPGA upgrade screening. Generally, it is required to make as many internal resources as possible in the FPGA chip operate at the...

Examples

Embodiment Construction

[0031] Aiming at the deficiencies in the prior art, the present invention provides a Virtex-5 FPGA general-purpose dynamic burn-in system, which overcomes the defects that the existing FPGA dynamic burn-in technology does not have versatility and lacks accurate FPGA junction temperature measurement means. While having a certain generality, it can also accurately measure and control the junction temperature of the FPGA chip. The system of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0032] Such as figure 1 Shown is a kind of Virtex-5 FPGA general dynamic aging system structural schematic diagram of the present invention, a kind of Virtex-5 FPGA general dynamic aging system, comprises aging system hardware, upper computer software, lower computer software, wherein, aging System hardware includes upper computer, program-controlled power supply, programmer, burn-in signal board, high-temperature test chamber, burn-in test...