Universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays)

Abstract

The invention relates to a universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays). The universal dynamic aging system for the Virtex-5 FPGAs includes an upper computer, a program-controlled power source, a programmer, an aging signal board, a high temperature test box, an aging test board and an aging FPGA; the upper computer generates a power-on instruction, sends an aging FPGA configuration bit stream, receives and displays aging response data; the program-controlled power source supplies power; the programmer completes the bit stream configuration of the aging FPGA; the aging signal board generates aging excitation signals; the high temperature test box adjusts the temperature of the aging signal board and the aging FPGA; and the aging FPGA includes a clock management module, a system monitoring module, a clock gating module and an aging function module. According to the universal dynamic aging system for the Virtex-5 FPGAs (field programmable gate arrays), the status of the aging function module is automatically adjusted according to the temperature of a chip, and aging response data are generated.

Description

technical field [0001] The present invention relates to a general dynamic burn-in system for Virtex-5 FPGAs, in particular to a dynamic burn-in test applicable to all types of FPGAs of the Virtex-5 series and capable of real-time monitoring of the junction temperature of burn-in FPGA chips. A system of monitoring and dynamic regulation. Background technique [0002] Virtex-5 is the fifth-generation FPGA product of Xilinx's Virtex series. There are generally two ways to choose FPGA for aerospace models: one is to purchase aerospace-grade (V-grade) products and use them after passing the test; the other is to purchase low-grade FPGAs. (M-level or I-level) products are used after upgrading and screening. From the analysis of availability and selection cost, the latter method is more advantageous. Dynamic burn-in is an important test item in low-level FPGA upgrade screening. Generally, it is required to make as many internal resources as possible in the FPGA chip operate at the...

AI Technical Summary

Problems solved by technology

When multiple device types or packages are involved, it is necessary to develop (or process) multiple dynamic aging systems, which is too costly for users with "many types and small batches"

[0005] (2) Lack of accurate FPGA junction temperature measurement means

Considering that the power consumption of the FPGA itself and the temperature rise of the chip caused by the actual operation are relatively large, if the ambient temperature of the burn-in test is directly set to the maximum junction temperature allowed in the manual, the FPGA will overheat.

There are two main methods for measuring the junction temperature of the FPGA: one is to use the power consumed by the FPGA and the thermal resistance of the package to calculate the temperature rise of the chip (temperature rise = power consumption × thermal resistance), but due to the actual thermal resistance value It is closely related to the air flow rate of the burn-in test, and there is a large fluctuation range, so this method cannot accurately calculate the actual temperature of the FPGA chip

The other is to use the temperature-measuring diode integrated in Xilinx FPGA to calculate the chip temperature by measuring the voltage drop change of the diode. This method requires the use of a dedicated industrial-grade plastic-encapsulated analog-to-digital converter (ADC), because the ADC cannot withstand FPGA Dynamic aging test temperature, so it can only be designed for remote measurement outside the high-temperature test chamber, resulting in low measurement accuracy, so the chip junction temperature cannot be accurately calculated

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