532 results about "Fpga chip" patented technology

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

The embodiment of the invention discloses a 4K splicing processor and a 4K splicing display system. The 4K splicing processor comprises a driving circuit used for processing a 4K resolution signal, the driving circuit comprises an FPGA chip U5, TVS array chips U10, U11, U12 and U13 and DP signal line connectors CN9 and CN10; the model of the U5 is Spartan-6, the models of the U10, the U11, the U12 and the U13 are all RClamp0524P, the CN9 is connected with the U5 through the U10 and the U11, and the CN10 is connected with the U5 through the U12 and the U13; the U5 receives the input 4K resolution signal through the CN9 to process the 4K resolution signal and outputs the processed 4K resolution signal through the CN10 to achieve 4K resolution signal looping. According to the 4K splicing processor and the 4K splicing display system, the problem that 4K splicing display system equipment is complex is solved.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

The invention relates to a configuration implementation method and system for a large-scale FPGA (Field Programmable Gate Array) interconnection system-on-chip. The system comprises 32 data interconnection FPGA core particles and a control FPGA core particle, the control FPGA is connected with the data FPGA through 32 groups of independent Slave Serial interfaces to realize parallel configuration, and state monitoring is carried out through 32 groups of UART (Universal Asynchronous Receiver / Transmitter) interfaces; configuration data are received externally by adopting an RGMII interface, and an upper computer is connected through a system UART. The method comprises the following steps that: after the FPGA is controlled to be self-started from the Flash, an upper computer issues a configuration data packet through the RGMII; the FPGA is controlled to synchronously drive 32 groups of Slave Serial time sequences to complete parallel configuration; the state is fed back in real time through a dual-mode monitoring mechanism, and timeout fault-tolerant logic is implanted. According to the configuration implementation method and system, the configuration efficiency is improved, interface signals are optimized and reduced, single-node fault isolation is supported, and the system availability is improved.

The application discloses a method and device for realizing high-speed operation of an algorithm based on a multi-level field cache, which comprises the following steps: a configuration management CPU sends algorithm parameters to an FPGA chip and saves the algorithm parameters in a RAM; a service processing CPU creates a handle and sends the handle to the configuration management CPU; the configuration management CPU generates a key number according to the handle; the configuration management CPU sends a key library to the FPGA chip; the service processing CPU sends a to-be-operated message to the FPGA chip; an algorithm scheduling module performs fragmentation judgment, and performs subsequent processing according to a sequence judgment result; a password operation module takes the received key, an initialization vector or an intermediate chain variable and the to-be-operated message as input, performs password operation, and outputs a calculation result and an operated intermediate chain variable; whether the to-be-operated message is the last data fragment is judged according to a tail fragment identifier, and subsequent processing is performed according to a tail fragment judgment result. The application can reduce the communication interface and CPU access times, realize high-speed operation of a password algorithm, and improve the overall performance of a password service system.

The invention discloses an EtherCAT master station distributed clock synchronization method based on an ARM and an FPGA, and relates to the technical field of industrial control, the method comprises the following steps: S1, using an FPGA chip integrated with the ARM and programmable logic resources to construct an EtherCAT master station distributed clock module, the ARM and the programmable logic resources interacting through an internal AXI interconnection bus; s2, the programmable logic resource obtains an enable signal sent by the ARM end, and if the enable signal is 1, the master station performs topology scanning, delay calculation, clock compensation and dynamic drift compensation operations on the slave station to obtain a delay compensation value and a local clock compensation value of the slave station; s3, after compensation is completed, the state machine of the master station automatically jumps to a synchronous signal generation module, SYNC parameters are obtained from the ARM end, and SYNC signal starting time of the slave station is calculated according to the SYNC parameters; s4, respectively converting the delay compensation value, the local clock compensation value and the starting time of the slave station into message information, sending the message information to the slave station, adding 1 to the address of the slave station, and returning to the step S1 until the distributed clock configuration of all the slave stations is completed; the EtherCAT master station distributed clock synchronization method solves the problem that a synchronization (SYNC) signal generated after a distributed clock algorithm is started is unstable, and shows potential and value in the field of higher-frequency slave station synchronization.

The invention discloses a control method of an interleaved parallel bidirectional DCDC converter. A circuit of the converter comprises three pairs of MOSFET switch tubes, three inductors and an output capacitor. The phase difference of PWM waves of the three pairs of MOSFET switch tubes is 120 degrees, and the phase difference is used for effectively reducing current ripples through staggered complementation of currents of all phases. Double closed-loop control is adopted, the DSP chip is responsible for current inner loop control, and the FPGA chip is responsible for voltage outer loop and power outer loop control. The current sharing precision is high, through flexible configuration of multiple proportionality coefficients and zero points, input fluctuation and load abrupt change interference can be accurately restrained, oscillation is avoided, stable output is ensured, and when load abrupt change or mode switching is carried out, output can be rapidly adjusted, transition time can be shortened, and overshoot can be reduced. And high dynamic response and strong robustness of the system are realized, so that complex and changeable application requirements are met.

The invention discloses an FPGA-based DDR3 cache circuit, which comprises an interconnection structure of an FPGA chip and a plurality of DDR3 storage chips, point-to-point direct connection is adopted for DQ / DQS / DM signals of the DDR3 chips, control / address / clock signals are shared with the DDR3 chips through a Fly-by topological structure, and the sequential relationship between CK + / CK-and DQS + / DQS-is adjusted through a write-in equalization technology. Through the point-to-point direct connection design of DQ / DQS / DM signals, the problems of reflection and crosstalk in a traditional topological structure are eliminated, and the error code risk is reduced; the time sequence relation between CK + / CK-and DQS + / DQS-is dynamically adjusted through the write-in equalization technology, and time sequence deviation caused by PCB wiring length and impedance mismatching or temperature change is compensated; the Fly-by topological structure is connected with control / address / clock signals, so that signal branches and reflection are reduced, and signal attenuation and crosstalk are reduced.

The invention relates to the technical field of quantum computer control, and belongs to a quantum equipment instruction distribution system and method based on multi-thread parallel routing, the system comprises an upper computer, an instruction board, an instruction routing board and an equipment end, and the instruction distribution method comprises the following steps: S1, inputting a program instruction and a control instruction through the upper computer, the data is issued to the instruction board through the local bus interface; s2, multi-thread parallel execution of the program instruction is achieved in an instruction board FPGA chip, a control instruction is generated and output to a routing board through a high-speed radio frequency interface, and the control instruction comprises a target address code; s3, dynamically selecting an output port by the instruction routing board according to the target address code generated in S2, and distributing the instruction to specified equipment; and S4, each device in the device end receives the instruction through the SSMA sequence interface and executes the instruction. According to the invention, efficient synchronous control of quantum equipment is realized through multi-thread parallel execution and a dynamic routing mechanism.

The invention discloses a method for improving data transmission bandwidth through an FPGA. The method comprises the steps that a data packaging module of a detector main control board sends data to be transmitted to a multi-channel GTP sending end in parallel; the data acquisition card receives the data of the corresponding channels through the multi-channel GTP receiving end and recovers Data and KCOD of each channel; an FIFO read-write control module of the data acquisition card writes data recovered by multiple channels into asynchronous FIFOs corresponding to the channels through write logic, and data buffering is carried out; the FIFO read-write control module simultaneously reads cache data of a plurality of asynchronous FIFOs through read control logic to realize cross-clock domain synchronization of multi-channel data; performing CRC (cyclic redundancy check) and processing on the read multi-channel data to obtain synchronous effective transmission data; and a single-channel GTP is upgraded to a dual-channel GTP or a multi-channel GTP, so that the data transmission bandwidth is improved, and normal operation of the FPGA chip is ensured.

The invention discloses a primary frequency modulation cooperative control system for a thermal power generating unit, and the system comprises a high-frequency data collection module which synchronously collects the frequency of a power grid, the valve position of a steam turbine and the main steam pressure through an FPGA chip, calculates the frequency change gradient, and activates a rapid frequency modulation mode when the frequency change gradient exceeds a preset range or not; the multi-modal compensation decision module is used for calling a multi-modal dynamic compensation model to predict a power gap in a future time period and distributing a compensation amount; the safety constraint execution module is used for monitoring the main steam pressure deviation and triggering the reinforcement learning agent to update the parameter library when the main steam pressure deviation exceeds the preset load change rate; and the parameter optimization module is used for carrying out reinforcement learning dynamic adjustment on state space and action space parameters, and integrating security constraint indexes in a reward function. Through collaborative design of multi-mode dynamic compensation, intelligent parameter optimization and security constraint protection, the problems of response delay, parameter mismatch and security risk of a traditional frequency modulation technology are solved, and the method has remarkable technical innovation and engineering application value.

The invention discloses an imaging dynamic range expansion method based on variable integral time, and relates to the field of infrared imaging. The method comprises the following steps of: firstly, sending an infrared original image acquired by a medium-wave infrared movement to an FPGA (Field Programmable Gate Array) chip, decoding integral time of the infrared original image, and converting a signal format; then the integral time information and the converted infrared image signal are synchronously sent to a non-uniformity correction module, and non-uniformity noise is corrected; performing dynamic range expansion of the fused image signal on the corrected image signal through a variable integral time imaging algorithm; and finally, digitally displaying the obtained fused image signal. The core innovation of the method is that a hierarchical integral time segmentation calibration model is established, and a non-uniformity correction parameter dynamically matched with integral time is obtained. The method breaks through the physical limitation of single-frame integration time, the low-temperature background signal-to-noise ratio is remarkably improved while high-temperature target details are reserved, and the method is particularly suitable for the refined imaging requirement of a high-dynamic complex infrared scene.

The invention discloses an integrated fire detection intelligent lamp for a railway tunnel. The integrated fire detection intelligent lamp comprises a multi-mode sensing module, an integrated thermal imaging array sensor, a multispectral flame sensor, a laser scattering type smoke sensor and an electrochemical CO sensor. An FPGA chip and a lightweight convolutional neural network model are arranged in the signal processing module, space-time fusion analysis is carried out on multi-modal sensing data in real time, and a fire judgment threshold is dynamically optimized through transfer learning; the dynamic ad hoc network communication module supports dual protocols of LoRaWAN and TSN; the adaptive power supply adopts an AC / DC power conversion module, integrates a piezoelectric vibration energy collection module and a thermoelectric power generation module, and combines a super capacitor and a lithium battery to realize quintuple redundant power supply; and the three-dimensional lighting array consists of a plurality of groups of independently controlled LED matrixes and is used for dynamically adjusting a lighting area and brightness distribution. The fire hazard detection sensitivity is improved through multi-dimensional data fusion, the illumination function is achieved, and the use requirement of the railway tunnel in the severe environment is met.

The invention discloses an SOC prototype verification logic division method and system based on resource constraints. The method comprises the steps that a to-be-verified SOC prototype is split into modules meeting the resource constraints of an FPGA; the split modules are tried to be combined in pairs to form modules meeting the resource constraint of the FPGA; 1 is added to the loop variable i of the finally obtained module according to the sequence of the number of the external connecting lines from large to small, and the FPGAs are distributed in the multi-FPGA verification platform; integrating the modules distributed with the FPGAs to generate a netlist file; and converting the netlist file into a bit stream file and downloading the bit stream file into the distributed FPGA. According to the method, the process of mapping SOC design to multiple FPGAs is achieved, logic division is rapidly achieved for the design, rapid time sequence convergence is achieved through reasonable arrangement of resources, the FPGA chip resource utilization rate is increased, and time sequence optimization iteration of a net list after integration is reduced.

The invention discloses a time synchronization method, a time synchronization system and a storage medium, and the method comprises the steps: receiving and fusing multi-source time signals at the same time, and obtaining a local time reference signal; calculating the frequency compensation amount of a local clock source in real time based on an LSTM model trained by using a local time reference signal; detecting whether the time signal is available, and determining to switch an atomic clock taming mode or a timekeeping mode based on a detection result; inserting a timestamp with femtosecond precision for the initial data message through the PIC to obtain a target data message; and sending the time synchronization information and the target data message to a 6G network node through a precision time protocol of the FPGA chip. According to the invention, on the basis that the satellite signal is taken as a time reference, two conditions that the satellite signal is available and unavailable are considered, and a local clock source and photon time service are adjusted in combination with a multi-source satellite signal fusion result, so that the time synchronization precision is improved, and the 6G network requirement is met.

The invention discloses a simultaneous multi-beam low-slow small target detection radar real-time processing method and system, and belongs to the technical field of radars. The system comprises a DSP chip connected with an upper computer. The DSP chip is connected with the FPGA chip through an EMIF interface and an SRIO interface. The DSP chip is used for analyzing a control command of an upper computer and sending the control command to the FPGA chip through the EMIF interface; and the FPGA chip is used for processing the acquired radar signal and transmitting a processed result to a DDR3 (Double Data Rate 3) of the DSP through an SRIO (Serial Radio Input / Output) interface. By optimizing the processing flow and the algorithm, hardware resources are fully mined, and the radar detection capability of the low-speed small target in the strong clutter environment is greatly improved. A complex number modulo operation module is designed to solve the problem that complex number modulo operation consumes long time. The multi-core parallel performance of the DSP is fully exerted, and the operation efficiency higher than that of a traditional method is achieved. Aiming at the DDR3 bus bottleneck, multiple cores access DDR3 densely in a peak shifting manner through the scheduling of the main control core, so that the time consumption of multi-core processing is reduced.

The invention discloses master-slave integrated MVB (Multifunction Vehicle Bus) simulation test equipment based on an FPGA (Field Programmable Gate Array) and an MCU (Microprogrammed Control Unit). An FPGA chip, an MCU chip and an MVB communication physical layer circuit are arranged in an equipment body; an MVB master logic unit and an MVB slave logic unit are integrated in the FPGA chip; the MCU chip is in communication connection with the main logic unit and the MVB slave logic unit; and the MVB communication physical layer circuit is used for realizing conversion between a logic level signal output by the FPGA chip and an EMD signal of an MVB bus. The MVB main logic control unit sends an MVB main frame according to the port traversal table stored in the port table unit; and after the MVB slave logic data and state control unit obtains the sending control right of the MVB sending control unit, the MVB slave logic unit sends or receives data with the MVB bus. The device number and cable connection are reduced, the deployment time of the test system is shortened, and the single test duration is shortened.

The invention discloses a satellite integrated electronic system. According to the system, a heterogeneous FPGA architecture is adopted, a satellite service management module is deployed on a first FPGA chip, and a measurement and control module and an encryption and decryption module are integrated on a second FPGA chip. The system realizes fault isolation through the design of an independent power domain and a reset domain of the measurement and control and encryption and decryption module, ensures that a measurement and control link is not interrupted through a hardware bypass channel in the second FPGA chip, and improves the reliability of the system. The encryption and decryption module adopts an encryption mode mapping graph and management system, supports a dynamic key management mechanism triggered based on three events of periodic switching, mapping graph updating and periodic parameter updating, can flexibly configure an encryption strategy according to an on-orbit task demand, and improves the security and adaptability of the system. The problems that in the prior art, chip performance and cost are difficult to balance, the integration level is low, and a whole machine fails due to a single-point fault are effectively solved, and the method is particularly suitable for a microsatellite platform with strict requirements for cost, size and reliability.

The invention relates to a non-contact high-precision pipe network damage detection system, which relates to the technical field of underground pipe network detection, and comprises a bimodal sensing unit, a data processing unit, a self-adaptive optical unit, a protective shell and a power management module. Through cooperation of the infrared thermal imaging module and the laser scanning module, millimeter-level precision can be realized, a visible light camera or a near-infrared camera can be automatically switched according to environmental turbidity through arrangement of a light filtering switching mechanism, clear imaging in a turbid water body can be ensured, and through a built-in FPGA chip of the data processing unit, the data processing unit can be used for realizing high-definition imaging of the visible light camera or the near-infrared camera. Through cooperation of the bimodal sensing unit, the data processing unit and the adaptive optical unit, temperature field and point cloud data can be synchronously acquired, after fusion, + / -3mm damage positioning precision can be realized, and when the turbidity is greater than 200NTU, high reliability can still be maintained, the detection efficiency can be improved, and the detection precision can be improved. And the risk of manual underwater operation is thoroughly avoided.

The application relates to a high-speed encryption and decryption engine and an encryption and decryption implementation method, wherein a plurality of physical channels are provided to provide a plurality of service processing modules with cryptographic services, the problem that a cryptographic card can only provide a single service channel is solved, secondary keys are imported into an FPGA chip for buffering, a session key is managed in a life cycle by the FPGA chip, the time cost of key updating required by cryptographic operation can be reduced, and the processing delay of the cryptographic service can be obviously reduced; the FPGA chip is used as a cryptographic operation processing core unit, multi-stage parallel pipeline processing is realized, and the processing performance is effectively improved.

The invention provides a remote sensing information on-satellite intelligent processing system and method based on a GPU. The system comprises a bottom plate, and a master control integrated plate and a processing plate which are fixed on the bottom plate in an extensible manner; the main control integrated board at least comprises a main control FPGA chip, each processing board in the processing boards at least comprises a plurality of GPU modules, the processing FPGA chip is arranged on the main control integrated board or each processing board, and the processing FPGA chip and the plurality of GPU modules form a heterogeneous parallel processing structure; the master control FPGA chip is used for remote control and telemetering communication, power-on and power-off of the processing board and program uploading control; the processing FPGA chip is used for data transmission and data distribution; and the plurality of GPU modules are used for processing the original echo data in parallel by using the target program. The method not only meets the requirements of processing real-time performance and data volume, but also adapts to the imaging and target detection recognition algorithm structure of the spaceborne SAR, can efficiently map the algorithm, and realizes full-real-time, high-efficiency and low-power-consumption information processing and distribution.

The invention discloses a large-computing-power SAR real-time imaging and target recognition system based on an FPGA + GPU architecture, and relates to the technical field of SAR imaging and target recognition, and the system is characterized in that an SAR echo data collection module collects multiband data through a 16-bit AD / DA daughter card and an FMC interface; the preprocessing module carries out noise reduction and filtering processing based on an FPGA and fuses multi-dimensional features. The high-speed interaction module adopts a GTH interface and an ETH interface to realize FPGA-GPU data transmission; the knowledge graph module dynamically updates features and relationships; the imaging matching module generates a high-resolution image by relying on the GPU and outputs a candidate category; the reasoning optimization module outputs an accurate result and feeds back the accurate result to the knowledge graph; preprocessing and feature extraction of SAR echo data are achieved through the FPGA chip, noise reduction, filtering and range compression are carried out on original data through the parallel processing capacity of the FPGA chip, and the data processing efficiency is improved.

The invention is suitable for the technical field of traveling wave distance measurement, and relates to a medium-high voltage power grid traveling wave distance measurement device and method, and the device comprises a signal conditioning circuit, an ADC chip, an FPGA chip, an embedded processor MPU, an embedded NPU module, a remote communication module, a Beidou module, and a power module. The signal conditioning circuit, the ADC chip, the FPGA chip and the embedded processor MPU are in communication connection in sequence, the embedded processor MPU is further in communication connection with the remote communication module and the Beidou module, and the power module is electrically connected with the signal conditioning circuit, the ADC chip, the FPGA chip, the Beidou module, the embedded processor MPU and the remote communication module. The device is simple in structure and convenient to operate, reduces the cost and power consumption of traveling wave fault location equipment, and improves the fault location accuracy of traveling wave fault location.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

The invention relates to the technical field of chip design simulation verification, in particular to a memory type dynamic determination method for prototype verification and hardware simulation, and the method comprises the steps: carrying out sub-design division according to the module level of each module in a user netlist in combination with a first resource threshold sequence corresponding to an FPGA (Field Programmable Gate Array), and fitting the design logic clustering characteristics; according to the method, the hardware segmentation requirements of cross-sub-design interconnection and adaptation to multi-FPGA prototype verification are reduced, the layout and wiring difficulty is reduced, the performance and frequency of the FPGA are effectively improved, storage type allocation is realized according to the first target conversion rate and the second target conversion rate of the object and the target memory type, and the storage efficiency is improved. Relative balance and independence of various kinds of memory resources are achieved in the sub-design as much as possible, the number of FPGA chips needed for achieving the sub-design is reduced, and equivalently, the performance of the FPGA is improved.

The application relates to the technical field of chip verification, and discloses an FPGA chip DSP module bit stream verification method and device. In the method, a bit stream file generation method is used to convert configurable parameters of a DSP module from abstract test intentions into specific physical configuration files, the low efficiency of configuring bit stream files for the functions of each DSP module is avoided, then a two-stage routing analysis method is used for function verification of the DSP module, a complete signal path mapping between an SWH port and core logic of the DSP module is accurately constructed, the correctness of the functions of the DSP module itself is ensured, and the interconnection correctness of the DSP module and adjacent modules is ensured, then an initial verification platform is reconstructed based on a port mapping table, and a high-abstraction-level behavior model is combined for result comparison, the verification efficiency and reliability of the DSP module are greatly improved, and the efficiency and accuracy of bit stream verification of the FPGA chip DSP module are ensured.

The application discloses a kind of master station controller control method, device, equipment and storage medium, the method includes: FPGA chip generates bus cycle interruption and pulse output completion interruption, and bus cycle interruption and pulse output completion interruption are sent to CPU unit;CPU unit obtains the time difference between master station system clock and slave station system clock in bus cycle interruption;Obtain cycle planning data in pulse output completion interruption, and write time difference and cycle planning data into FPGA chip;FPGA chip is simultaneously controlled according to time difference and cycle planning data to bus and pulse output control.The time difference between master station system clock and slave station system clock obtained by CPU unit and cycle planning data are written into FPGA chip in the application, and FPGA chip is simultaneously controlled according to time difference and cycle planning data to bus and pulse output control, and the simultaneous control of pulse motor and bus motor is realized.

The present disclosure relates to a TCP mirror data processing method, device, chip and medium, wherein the method comprises: constructing a second buffer in the FPGA chip when it is determined according to a first current TCP mirror packet that a preset TCP reconnection condition is met; when the first buffer contains a target TCP mirror packet to be output, opening the read interface of the first buffer and the write interface of the second buffer, and closing the read interface of the second buffer and the write interface of the first buffer; when the first buffer does not contain a target TCP mirror packet to be output, closing the read interface of the first buffer and opening the read interface of the second buffer, and sending the corresponding TCP mirror packet to the server through the read interface of the second buffer. In this technical solution, the out-of-order rearrangement processing based on the heterogeneous structure is realized, and it is ensured that the normal out-of-order rearrangement operation is not affected during the reconnection, the smooth transition is realized, and the continuity and integrity of the out-of-order rearrangement processing are ensured, thereby improving the reliability and stability of the heterogeneous structure.

The utility model discloses a programmable logic device test experiment device, which relates to the field of logic device test experiments and comprises a replaceable FPGA test circuit, a phase-locked loop test circuit, a pulse width modulation test circuit, a chip power supply circuit, a serial port test circuit, a Bank area power supply test circuit, a power supply generation circuit and a liquid crystal display control circuit. According to the experimental device for testing the programmable logic device, through a mode of combining the liquid crystal display screen and the FPGA function test board, a large-scale test machine in traditional test equipment is omitted, so that a test system is more portable, comprehensive coverage test of FPGA chip functions can be realized through compiling a plurality of self-test programs, and the test efficiency is improved. Therefore, not only can the basic logic function of the FPGA be tested, but also the advanced characteristics and boundary conditions of the FPGA can be deeply verified, so that the function correctness of the FPGA chip can be more comprehensively ensured.