950 results about "Fpga chip" patented technology

The invention relates to the technical field of radar control, in particular to an anti-interference control method applied to a radar, and aims to solve the problem that an existing radar anti-interference technology is insufficient in anti-interference capability in a complex electromagnetic environment. According to the method, multi-dimensional input data of a radar system are synchronously collected, interference feature extraction is performed on multi-dimensional data streams by using a dual-channel deep network, and interference fingerprint vectors are output to a dynamic feature library in real time. And based on the interference feature priority list, performing cooperative processing, including spatial filtering, frequency domain notch, polarization projection and residual extraction and sparse reconstruction of a target signal. And dynamically adjusting the processing parameters according to the real-time evaluation result. And data distribution processing is carried out on the suppressing interference and the deception interference, and final target trajectory information is output through result fusion. Parallel processing is also realized on the FPGA chip, and the processing speed is improved. On the whole, the anti-interference capability, the stability and the real-time performance of the radar system in a complex electromagnetic environment are improved.

The invention discloses an SM4 encryption method based on an FPGA, and relates to the technical field of data encryption, and the method comprises the steps: obtaining to-be-encrypted plaintext data; a plurality of SM4 encryption cores are configured on the FPGA chip to perform parallel encryption operation on plaintext data to be encrypted; wherein each SM4 encryption core adopts a pipeline architecture, and the pipeline architecture comprises an access device, a round function arithmetic unit and a key adder; an extraction circuit based on physical noise and integrated on the FPGA chip is utilized to generate N-bit random numbers as encryption keys of each SM4 encryption core; handshake signals are collected to calculate the operation efficiency of each SM4 encryption core; adjusting FPGA resource allocation among the SM4 encryption cores by adopting a priority scheduling algorithm according to the operation efficiency; in the encryption operation process, power consumption equalization is carried out by adopting polynomial and logical operation hybrid calculation, and time sequence randomization is carried out by adopting a random waiting period. Aiming at the problem of weak anti-difference sensitivity in the prior art, the side channel attack resistance is improved.

The invention discloses a loess tunnel surrounding rock deformation monitoring method, and relates to the technical field of civil engineering and geological engineering, and the method comprises the steps: integrating a spiral winding type optical fiber sensor, a double-cavity humidity compensation vibrating wire sensor and a microseismic array, and capturing surrounding rock strain, vibration and geological activities; the vibrating wire sensor suppresses humidity interference through a silicone oil damping medium and self-adaptive excitation frequency, and the optical fiber sensor is fixed through a pre-embedded silica gel sleeve to adapt to surrounding rock deformation; edge computing nodes are deployed on the inner wall of the tunnel, an FPGA chip and a lightweight GRU model are integrated, optical fiber strain, a micro-seismic energy spectrum and laser point cloud displacement field data are fused in real time, the strain gradient is analyzed, and a crack propagation probability cloud picture is generated; redundant optical fiber link switching is combined with a six-degree-of-freedom mechanical arm to realize breakpoint self-repairing, and a self-cleaning air curtain is integrated to inhibit dust adhesion; and constructing a geological parameter library based on a BIM-GIS fusion platform, driving a finite element-discrete element coupling model to dynamically update boundary conditions, and predicting surrounding rock deformation and collapse risks.

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

The invention discloses a beam information on-line measurement method based on a steady-state forward voltage vector relation principle. The beam information on-line measurement method comprises the following steps: measuring a cavity incident signal Pf of a radio frequency cavity on line to obtain an original forward voltage Vf * of the radio frequency cavity; performing calibration and normalization processing on the original forward voltage Vf * to obtain a forward voltage Vf; scaling the forward voltage Vf to obtain a standardized forward voltage Uf; based on the standardized forward voltage Uf0 and Uf1 under two conditions of no beam current and beam current, respectively calculating steady-state mean values UF0 and UF1; obtaining a steady-state beam equivalent voltage VB based on the steady-state mean values UF0 and UF1; and based on the steady-state beam current equivalent voltage VB, the beam current intensity IB and the beam current synchronous phase # imgabs0 # in the steady state are obtained. Therefore, the device can be completely deployed in an FPGA chip, and beam information on-line real-time measurement can be realized at the sub-microsecond magnitude.

The invention provides a task queue-based heterogeneous resource pool real-time scheduling method, which comprises the following steps of: splitting tasks transmitted at random moments into sub-task sets with topological relations, adding the tasks into a queue to open up a track, and sequencing and numbering according to priorities; the bottom layer chip is interconnected, a resource pool monitor is added to monitor the state of resources, a heterogeneous resource pool is constructed, and data is provided for a scheduling system; the scheduling system obtains the real-time states of the queue and the resource pool, monitors the occurrence of events, makes a dynamic decision, sets an optimization target, and schedules the required computing resources for the subtasks according to the priority in the queue. According to the method, the parallel computing advantage of the FPGA chip is fully exerted, high-speed communication in the heterogeneous resource pool is ensured, the resource utilization efficiency of the resource pool is greatly improved, the total task set execution time delay can be effectively reduced, and meanwhile, the heterogeneous resource pool can achieve the load balancing effect.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

In order to solve the problem that quick response and distortionless recording of ultrahigh-frequency partial discharge signals are difficult to realize when accidental pulses are generated in the prior art, the invention relates to a dual-channel parallel processing architecture for ultrahigh-frequency partial discharge signals, which comprises a signal cloning circuit and a signal processing circuit, the ultrahigh-frequency partial discharge module is used for receiving ultrahigh-frequency partial discharge signals and synchronously outputting the ultrahigh-frequency partial discharge signals as first target signals and second target signals after lossless copying; the low-gain channel circuit is used for performing buffer transmission for maintaining an original bandwidth and a dynamic range on the first target signal to generate a first gain signal; the high-gain channel circuit is used for performing gain amplification on the second target signal to generate a second gain signal; the digital signal processing unit is used for performing synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; and the FPGA chip is integrated in the digital signal processing unit and is used for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm and generating a fusion signal.

The invention relates to an FPGA (Field Programmable Gate Array)-based satellite-borne equipment single event upset resisting system and an implementation method. The system comprises an anti-fuse FPGA chip, an SRAM (Static Random Access Memory) FPGA chip and an FPGA chip, the SRAM type FPGA chip is used for completing signal processing; the three FLASH chips are used for solidifying three identical SRAM (Static Random Access Memory) FPGA programs; the anti-fuse FPGA chip reads backup programs from the three FLASH chips respectively at the same time after the equipment is normally powered on, compares the three backup programs, starts to vote when at least two kinds of data are consistent through comparison, brushes the same data into the SRAM type FPGA chip to complete configuration of the FPGA chip, and refreshes the FPGA chip at regular time at the same time. By adopting the method, the single event upset resistance of the FPGA in the space environment can be enhanced, and the method has the advantages of high stability, low cost and the like.

The embodiment of the invention discloses a 4K splicing processor and a 4K splicing display system. The 4K splicing processor comprises a driving circuit used for processing a 4K resolution signal, the driving circuit comprises an FPGA chip U5, TVS array chips U10, U11, U12 and U13 and DP signal line connectors CN9 and CN10; the model of the U5 is Spartan-6, the models of the U10, the U11, the U12 and the U13 are all RClamp0524P, the CN9 is connected with the U5 through the U10 and the U11, and the CN10 is connected with the U5 through the U12 and the U13; the U5 receives the input 4K resolution signal through the CN9 to process the 4K resolution signal and outputs the processed 4K resolution signal through the CN10 to achieve 4K resolution signal looping. According to the 4K splicing processor and the 4K splicing display system, the problem that 4K splicing display system equipment is complex is solved.

The invention discloses test equipment, a test system, a test method and a test device.The test equipment provided by the invention is internally provided with an FPGA chip capable of controlling a target power supply for supplying power to a to-be-tested MCU, and in practical application, different test logic programs can be configured in the FPGA chip according to practical requirements, so that the test efficiency is improved; according to the technical scheme, the FPGA chip in the test equipment can generate the high-frequency clock signal, so that the time accuracy during voltage burr fault injection of the to-be-tested MCU can be ensured, and the test effect of the to-be-tested MCU can be further ensured.

The invention relates to a video acquisition and transmission method and device for converting a 10-gigabit network into a PCIe (Peripheral Component Interconnect Express) interface. The method comprises the following steps: receiving a video stream through a double 10-gigabit network optical module, carrying out protocol analysis and preprocessing through an FPGA (Field Programmable Gate Array), realizing multi-path alternate reading and writing by utilizing DDR3 ping-pong cache, dynamically distributing the video stream to multiple devices through a three-path PCIe 3.0 * 4 interface and an XDMA (Extensible Direct Memory Access), and optimizing the transmission priority in combination with a load state. The device comprises two paths of SFP + optical modules, a Xilinx Virtex7 series FPGA chip (integrated with a 10-gigabit network MAC, a PCIe XDMA IP core and a DDR3 controller), three paths of PCIe 3.0 * 4 interfaces and an external DDR3 memory. The system has the advantages that the double 10-gigabit network input and multi-PCIe channel collaborative architecture breaks through the single-channel bandwidth bottleneck; the intelligent ping-pong cache and the AXI arbitration strategy reduce the data conflict risk; and dynamic bandwidth allocation optimizes real-time performance.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

The invention provides an adaptive ultra-wideband space-time digital beam forming method and system based on a multi-term filter. The system comprises an FPGA chip module and an AD / DA conversion module, the FPGA chip module is connected with the AD / DA conversion module and is used for forming a wave beam and sending wave beam data to the AD / DA conversion module, generating an intermediate frequency broadband signal and transmitting the intermediate frequency broadband signal to a subsequent circuit; the AD / DA conversion module is used for inputting the intermediate frequency signal subjected to AD sampling into the FPGA chip module and receiving beam data; a multi-term filter structure is adopted, the signal bandwidth is effectively reduced through the time delay function preposition and multi-phase filter combined technology, the time domain ultra-wideband beam forming function is efficiently achieved, and the time domain ultra-wideband beam forming device can be widely applied to radar wideband digital beam forming, microphone arrays, sonar arrays and other systems.

The invention provides a space carrier intelligent bus GLINK interface bridging design method based on a domestic FPGA, belongs to the field of FPGA application, can provide two paths of GLINK data transmission channels and two paths of GLINK data relay / forwarding channel high-speed interfaces at the same time by utilizing FPGA chip resources and combining with a GLINK chip, and can meet the requirements of switching networking and annular networking at the same time. An external memory access interface (EMIF) of a GLINK chip is configured for an international standardized PCIe protocol, and meanwhile, an FIFO synchronous read-write interface in a DMA mode is adopted, so that the communication safety is guaranteed, malicious attacks and accidental interruption are prevented, the communication reliability is improved, and the communication transmission rate is increased.

The invention provides an FPGA (Field Programmable Gate Array) accelerator card with a hard synchronization function, which comprises an FPGA chip used for processing a computing task issued by a universal processor system, the FPGA chip is provided with a storage module and a power supply module, and external interfaces comprise a PCIE (Peripheral Component Interface Express) interface, a QSFP (Quad Small Form-factor Pluggable) optical interface, an SMA (Shape Memory Alloy) interface and an RS422 interface. And the PCIE interface and the QSFP optical interface are respectively interconnected with the high-speed port of the FPGA module at a high speed. And the storage module, the SMA interface and the RS422 interface are all connected to a general I / O pin of the FPGA. According to the invention, the synchronization signal from the external device can be received, and the PCIE message interrupt is sent to the universal processor system end through the PCIE interface, so that the synchronization time base establishment between the universal processor system and the acceleration card external device is realized. And the message interruption of the PCIE is used as a strong real-time synchronization mode, so that the accurate control on the external equipment can be realized. Meanwhile, the PCIE module and the QSFP optical interface can achieve high-speed data transmission, and the acceleration card supporting strong real-time processing is formed by combining high-density parallel computing of the FPGA.

The invention relates to a configuration implementation method and system for a large-scale FPGA (Field Programmable Gate Array) interconnection system-on-chip. The system comprises 32 data interconnection FPGA core particles and a control FPGA core particle, the control FPGA is connected with the data FPGA through 32 groups of independent Slave Serial interfaces to realize parallel configuration, and state monitoring is carried out through 32 groups of UART (Universal Asynchronous Receiver / Transmitter) interfaces; configuration data are received externally by adopting an RGMII interface, and an upper computer is connected through a system UART. The method comprises the following steps that: after the FPGA is controlled to be self-started from the Flash, an upper computer issues a configuration data packet through the RGMII; the FPGA is controlled to synchronously drive 32 groups of Slave Serial time sequences to complete parallel configuration; the state is fed back in real time through a dual-mode monitoring mechanism, and timeout fault-tolerant logic is implanted. According to the configuration implementation method and system, the configuration efficiency is improved, interface signals are optimized and reduced, single-node fault isolation is supported, and the system availability is improved.

The application discloses a method and device for realizing high-speed operation of an algorithm based on a multi-level field cache, which comprises the following steps: a configuration management CPU sends algorithm parameters to an FPGA chip and saves the algorithm parameters in a RAM; a service processing CPU creates a handle and sends the handle to the configuration management CPU; the configuration management CPU generates a key number according to the handle; the configuration management CPU sends a key library to the FPGA chip; the service processing CPU sends a to-be-operated message to the FPGA chip; an algorithm scheduling module performs fragmentation judgment, and performs subsequent processing according to a sequence judgment result; a password operation module takes the received key, an initialization vector or an intermediate chain variable and the to-be-operated message as input, performs password operation, and outputs a calculation result and an operated intermediate chain variable; whether the to-be-operated message is the last data fragment is judged according to a tail fragment identifier, and subsequent processing is performed according to a tail fragment judgment result. The application can reduce the communication interface and CPU access times, realize high-speed operation of a password algorithm, and improve the overall performance of a password service system.

The invention discloses an EtherCAT master station distributed clock synchronization method based on an ARM and an FPGA, and relates to the technical field of industrial control, the method comprises the following steps: S1, using an FPGA chip integrated with the ARM and programmable logic resources to construct an EtherCAT master station distributed clock module, the ARM and the programmable logic resources interacting through an internal AXI interconnection bus; s2, the programmable logic resource obtains an enable signal sent by the ARM end, and if the enable signal is 1, the master station performs topology scanning, delay calculation, clock compensation and dynamic drift compensation operations on the slave station to obtain a delay compensation value and a local clock compensation value of the slave station; s3, after compensation is completed, the state machine of the master station automatically jumps to a synchronous signal generation module, SYNC parameters are obtained from the ARM end, and SYNC signal starting time of the slave station is calculated according to the SYNC parameters; s4, respectively converting the delay compensation value, the local clock compensation value and the starting time of the slave station into message information, sending the message information to the slave station, adding 1 to the address of the slave station, and returning to the step S1 until the distributed clock configuration of all the slave stations is completed; the EtherCAT master station distributed clock synchronization method solves the problem that a synchronization (SYNC) signal generated after a distributed clock algorithm is started is unstable, and shows potential and value in the field of higher-frequency slave station synchronization.

The invention discloses a high-speed backboard system and method for achieving LVDS communication based on an FPGA, the high-speed backboard system comprises a controller and a communication assembly, the communication assembly comprises a plurality of communication modules, the communication assembly specifically comprises a master station module and at least one slave station module, the controller is connected with the master station module, and the slave station module is connected with the controller. An FPGA chip is arranged in each of the master station module and the slave station module, and the FPGA chip in the master station module is electrically connected with an MCU; each of the master station module and the slave station module at least comprises a sending interface and a receiving interface, and data frame interaction is carried out between the master station module and the slave station module through an interface assembly composed of the sending interface and the receiving interface. The master station module and the slave station module achieve data exchange through the interface assembly, the purpose that the master station module controls the slave station module and obtains information of the slave station module is achieved, the structure is simple, connection between the modules is stable and reliable, the use efficiency of the system on site is improved, and cost is reduced.

The invention discloses a knowledge-driven and data-driven magnaporthe oryzae AVR (Automatic Voltage Regulation) gene RNA (Ribonucleic Acid) secondary structure generator, which is characterized in that an on-chip memory of an ARM (Advanced RISC Machines) chip and an external DRAM (Dynamic Random Access Memory) chip are adopted for respectively storing RNA original data and intermediate results; an FPGA chip is adopted to realize mapping from an RNA sequence to a knowledge graph, and features such as base pairing are fused through LUT; a multi-core AI chip is adopted, an encoder-decoder network is executed in parallel, and knowledge and data are fused to generate a secondary structure; and the VAE-GAN network is executed in a streamlined manner through an AI chip, the quality of the generated structure is evaluated and iteratively optimized, and an accurate RNA secondary structure is generated. The invention further discloses a knowledge-driven and data-driven fused magnaporthe oryzae AVR gene RNA secondary structure prediction method, RNA physicochemical characteristics are utilized, deep learning, transfer learning and knowledge distillation technologies are combined, and the prediction accuracy and operation efficiency are improved.

The invention discloses a circuit and a chip for enabling a CXL protocol to support a low-rate serial link. The circuit provided by the invention comprises a link management state machine containing a sending SDS state, a 4-byte clock skew compensation character SKP4B generation circuit and an analysis circuit, an encoder and a decoder supporting a data stream start character SDS, a 128b / 130b encoder and a decoder, a data stream start detection circuit, a 40: 1 parallel-serial conversion circuit, a 32: 1 parallel-serial conversion circuit, a multiplexer, a 1: 40 serial-parallel conversion circuit and a 1: 1 parallel-serial conversion circuit, the output end of the multiplexer is connected with the input end of the demultiplexer through a serial link, and the output end of the demultiplexer is connected with the input end of the demultiplexer through a serial link. The invention aims to enable the CXL protocol to extend and support PCIe Gen1 and Gen2 rates, so that the FPGA chip can use the CXL protocol, and the ASIC chip can use the CXL protocol at a low rate.

The invention discloses a control method of an interleaved parallel bidirectional DCDC converter. A circuit of the converter comprises three pairs of MOSFET switch tubes, three inductors and an output capacitor. The phase difference of PWM waves of the three pairs of MOSFET switch tubes is 120 degrees, and the phase difference is used for effectively reducing current ripples through staggered complementation of currents of all phases. Double closed-loop control is adopted, the DSP chip is responsible for current inner loop control, and the FPGA chip is responsible for voltage outer loop and power outer loop control. The current sharing precision is high, through flexible configuration of multiple proportionality coefficients and zero points, input fluctuation and load abrupt change interference can be accurately restrained, oscillation is avoided, stable output is ensured, and when load abrupt change or mode switching is carried out, output can be rapidly adjusted, transition time can be shortened, and overshoot can be reduced. And high dynamic response and strong robustness of the system are realized, so that complex and changeable application requirements are met.

The invention provides an FPGA online configuration method and device, a medium and a program product. The method comprises the steps that a main control chip downloads an encrypted FPGA programming file from an upper computer and stores the encrypted FPGA programming file to a specified directory; in response to equipment upgrading or power-off restarting operation, the main control chip searches a target version in a specified directory, and reads configured FPGA version information from the FPGA chip; in response to the fact that the configured FPGA version information is not matched with the target version, the main control chip erases a configuration memory corresponding to the FPGA chip and writes an FPGA programming file of the target version into the configuration memory; and in response to equipment power-on operation, the FPGA chip reads the FPGA programming file from the configuration memory for configuration in the AS mode. The invention provides a set of universal remote online configuration operation method, the operation is simple and feasible, the FPGA programming file does not need to be analyzed, and the influence of FPGA platform difference is greatly reduced.

The invention discloses an FPGA-based DDR3 cache circuit, which comprises an interconnection structure of an FPGA chip and a plurality of DDR3 storage chips, point-to-point direct connection is adopted for DQ / DQS / DM signals of the DDR3 chips, control / address / clock signals are shared with the DDR3 chips through a Fly-by topological structure, and the sequential relationship between CK + / CK-and DQS + / DQS-is adjusted through a write-in equalization technology. Through the point-to-point direct connection design of DQ / DQS / DM signals, the problems of reflection and crosstalk in a traditional topological structure are eliminated, and the error code risk is reduced; the time sequence relation between CK + / CK-and DQS + / DQS-is dynamically adjusted through the write-in equalization technology, and time sequence deviation caused by PCB wiring length and impedance mismatching or temperature change is compensated; the Fly-by topological structure is connected with control / address / clock signals, so that signal branches and reflection are reduced, and signal attenuation and crosstalk are reduced.

The invention discloses a radiation-resistant all-digital high-frequency low-level control system which is characterized in that the system can be arranged on an accelerator site with strong radiation and is used for solving the problem that signals are interfered due to the fact that the signal transmission distance is too long. According to the system, the functions of all peripheral chips which cannot work normally due to strong radiation on the accelerator site are included in the radiation-resistant FPGA chip, and the functions of all the external chips and the original functions of the radiation-resistant FPGA chip are achieved through the radiation-resistant FPGA chip. The system is realized by using a single radiation-resistant FPGA chip, a high-frequency digital control algorithm is realized through firmware program design of the radiation-resistant FPGA chip, the control function of a high-frequency low-level control system is met, and the radiation-resistant problem of the whole system is directly solved. The system can be placed on the site of an accelerator, breaks through the limitation that a transmission cable needs to penetrate through a wall, is closer to a controlled object, and does not need a radio frequency cable to penetrate through a pipeline in the wall.

The invention discloses a multi-channel high-speed sampling data storage system and a control method. The system comprises a disk array, an upper computer, a DDR3 memory particle cache module, a PXIe transport protocol module, an Aurora transport protocol module, a DDR3 memory bank cache module, a data acquisition and signal processing module and an A / D conversion module. The control method comprises the steps that an upper computer issues a control instruction in a PIO mode through a PXIe transmission protocol module and issues reconfiguration data in a DMA reading mode, a first FPGA chip stores the reconfiguration data into a DDR3 memory particle cache module, and reconfiguration of a second FPGA chip is initiated; after configuration is completed, the first FPGA chip transmits a control command and parameters to the second FPGA chip through an Aurora protocol, receives a digital intermediate frequency signal converted by the A / D conversion module according to the command, and carries out corresponding signal processing and logic control in three modes of single point, real time and triggering according to an instruction of an upper computer.

The invention discloses a digital twinning-based heat-assisted flow drilling and riveting control method and a digital twinning-based heat-assisted flow drilling and riveting control system. The method comprises the following steps: acquiring temperature, pressure, displacement and surface topography data; a temperature-pressure-morphology comprehensive index is constructed through weighted fusion; real-time processing is carried out through the FPGA chip and the lightweight AI model; a Pareto frontier solution set is generated in combination with a Monte Carlo-NSGA-II hybrid algorithm; constructing a heat-force-phase change coupling unified constitutive model to carry out multi-physics field reverse optimization; dynamic updating of process parameters is realized through a digital twinborn case library; and dynamically modulating PID parameters by adopting deep reinforcement learning. The system comprises a multi-source data acquisition terminal, an intelligent decision module and a dynamic control module. According to the method, the problems of parameter lag and poor adaptability of a traditional method are solved, and the processing task can be efficiently and accurately completed.

The invention discloses a spray head plate of a printer and a printing system, relates to the technical field of ink-jet printing, and aims to solve the problem of high printing cost caused by the fact that one spray head plate is only connected with one spray head in the prior art. The nozzle plate comprises an FPGA chip, a controller, a driver and a nozzle switching assembly. The spray head switching assembly is connected with a plurality of or a plurality of spray heads; the FPGA chip receives the initial control instruction, converts the initial control instruction into a recognizable control instruction and sends the recognizable control instruction to the controller; the controller determines a target nozzle based on the control instruction, and sends a first digital driving signal in the control instruction to the FPGA chip after the target nozzle is determined; the target nozzle comprises at least one or one nozzle; the FPGA chip converts the first digital driving signal into a second digital driving signal and sends the second digital driving signal to the driver; the driver is further connected with the spray head switching assembly and converts the second digital driving signal into a target analog signal so as to drive a target spray head.

The invention relates to the technical field of integrated circuits, and discloses a soft error injection system which comprises an upper computer and an FPGA chip, the FPGA chip comprises error injection logic, a configuration circuit and an SRAM, and the configuration circuit is provided with an internal configuration interface and an ECC interface; the upper computer generates configurable bit information and expected injection dislocation information of the FPGA chip; the error injection logic is configured as follows: judging whether the ECC in the FPGA chip is running or not through the ECC interface; if it is determined that the ECC does not run, the configuration frame of the SRAM is read back and stored through an internal configuration interface; according to the expected injection misplacement information, carrying out negation on corresponding position bits in the configuration frame to obtain an injection misplacement configuration frame; calculating the CRC of the error injection configuration frame, and generating a new configuration frame according to the write instruction, the error injection configuration frame and the CRC; and a new configuration frame is written into the SRAM through the internal configuration interface via the configuration circuit, and an error injection completion instruction is sent to an upper computer. The invention further provides the FPGA chip, and soft error injection is carried out through the error injection logic.