727 results about "Fpga chip" patented technology

The invention discloses a loess tunnel surrounding rock deformation monitoring method, and relates to the technical field of civil engineering and geological engineering, and the method comprises the steps: integrating a spiral winding type optical fiber sensor, a double-cavity humidity compensation vibrating wire sensor and a microseismic array, and capturing surrounding rock strain, vibration and geological activities; the vibrating wire sensor suppresses humidity interference through a silicone oil damping medium and self-adaptive excitation frequency, and the optical fiber sensor is fixed through a pre-embedded silica gel sleeve to adapt to surrounding rock deformation; edge computing nodes are deployed on the inner wall of the tunnel, an FPGA chip and a lightweight GRU model are integrated, optical fiber strain, a micro-seismic energy spectrum and laser point cloud displacement field data are fused in real time, the strain gradient is analyzed, and a crack propagation probability cloud picture is generated; redundant optical fiber link switching is combined with a six-degree-of-freedom mechanical arm to realize breakpoint self-repairing, and a self-cleaning air curtain is integrated to inhibit dust adhesion; and constructing a geological parameter library based on a BIM-GIS fusion platform, driving a finite element-discrete element coupling model to dynamically update boundary conditions, and predicting surrounding rock deformation and collapse risks.

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

In order to solve the problem that quick response and distortionless recording of ultrahigh-frequency partial discharge signals are difficult to realize when accidental pulses are generated in the prior art, the invention relates to a dual-channel parallel processing architecture for ultrahigh-frequency partial discharge signals, which comprises a signal cloning circuit and a signal processing circuit, the ultrahigh-frequency partial discharge module is used for receiving ultrahigh-frequency partial discharge signals and synchronously outputting the ultrahigh-frequency partial discharge signals as first target signals and second target signals after lossless copying; the low-gain channel circuit is used for performing buffer transmission for maintaining an original bandwidth and a dynamic range on the first target signal to generate a first gain signal; the high-gain channel circuit is used for performing gain amplification on the second target signal to generate a second gain signal; the digital signal processing unit is used for performing synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; and the FPGA chip is integrated in the digital signal processing unit and is used for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm and generating a fusion signal.

The invention relates to an FPGA (Field Programmable Gate Array)-based satellite-borne equipment single event upset resisting system and an implementation method. The system comprises an anti-fuse FPGA chip, an SRAM (Static Random Access Memory) FPGA chip and an FPGA chip, the SRAM type FPGA chip is used for completing signal processing; the three FLASH chips are used for solidifying three identical SRAM (Static Random Access Memory) FPGA programs; the anti-fuse FPGA chip reads backup programs from the three FLASH chips respectively at the same time after the equipment is normally powered on, compares the three backup programs, starts to vote when at least two kinds of data are consistent through comparison, brushes the same data into the SRAM type FPGA chip to complete configuration of the FPGA chip, and refreshes the FPGA chip at regular time at the same time. By adopting the method, the single event upset resistance of the FPGA in the space environment can be enhanced, and the method has the advantages of high stability, low cost and the like.

The embodiment of the invention discloses a 4K splicing processor and a 4K splicing display system. The 4K splicing processor comprises a driving circuit used for processing a 4K resolution signal, the driving circuit comprises an FPGA chip U5, TVS array chips U10, U11, U12 and U13 and DP signal line connectors CN9 and CN10; the model of the U5 is Spartan-6, the models of the U10, the U11, the U12 and the U13 are all RClamp0524P, the CN9 is connected with the U5 through the U10 and the U11, and the CN10 is connected with the U5 through the U12 and the U13; the U5 receives the input 4K resolution signal through the CN9 to process the 4K resolution signal and outputs the processed 4K resolution signal through the CN10 to achieve 4K resolution signal looping. According to the 4K splicing processor and the 4K splicing display system, the problem that 4K splicing display system equipment is complex is solved.

The invention relates to a video acquisition and transmission method and device for converting a 10-gigabit network into a PCIe (Peripheral Component Interconnect Express) interface. The method comprises the following steps: receiving a video stream through a double 10-gigabit network optical module, carrying out protocol analysis and preprocessing through an FPGA (Field Programmable Gate Array), realizing multi-path alternate reading and writing by utilizing DDR3 ping-pong cache, dynamically distributing the video stream to multiple devices through a three-path PCIe 3.0 * 4 interface and an XDMA (Extensible Direct Memory Access), and optimizing the transmission priority in combination with a load state. The device comprises two paths of SFP + optical modules, a Xilinx Virtex7 series FPGA chip (integrated with a 10-gigabit network MAC, a PCIe XDMA IP core and a DDR3 controller), three paths of PCIe 3.0 * 4 interfaces and an external DDR3 memory. The system has the advantages that the double 10-gigabit network input and multi-PCIe channel collaborative architecture breaks through the single-channel bandwidth bottleneck; the intelligent ping-pong cache and the AXI arbitration strategy reduce the data conflict risk; and dynamic bandwidth allocation optimizes real-time performance.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

The invention provides an adaptive ultra-wideband space-time digital beam forming method and system based on a multi-term filter. The system comprises an FPGA chip module and an AD / DA conversion module, the FPGA chip module is connected with the AD / DA conversion module and is used for forming a wave beam and sending wave beam data to the AD / DA conversion module, generating an intermediate frequency broadband signal and transmitting the intermediate frequency broadband signal to a subsequent circuit; the AD / DA conversion module is used for inputting the intermediate frequency signal subjected to AD sampling into the FPGA chip module and receiving beam data; a multi-term filter structure is adopted, the signal bandwidth is effectively reduced through the time delay function preposition and multi-phase filter combined technology, the time domain ultra-wideband beam forming function is efficiently achieved, and the time domain ultra-wideband beam forming device can be widely applied to radar wideband digital beam forming, microphone arrays, sonar arrays and other systems.

The invention provides a space carrier intelligent bus GLINK interface bridging design method based on a domestic FPGA, belongs to the field of FPGA application, can provide two paths of GLINK data transmission channels and two paths of GLINK data relay / forwarding channel high-speed interfaces at the same time by utilizing FPGA chip resources and combining with a GLINK chip, and can meet the requirements of switching networking and annular networking at the same time. An external memory access interface (EMIF) of a GLINK chip is configured for an international standardized PCIe protocol, and meanwhile, an FIFO synchronous read-write interface in a DMA mode is adopted, so that the communication safety is guaranteed, malicious attacks and accidental interruption are prevented, the communication reliability is improved, and the communication transmission rate is increased.

The invention relates to a configuration implementation method and system for a large-scale FPGA (Field Programmable Gate Array) interconnection system-on-chip. The system comprises 32 data interconnection FPGA core particles and a control FPGA core particle, the control FPGA is connected with the data FPGA through 32 groups of independent Slave Serial interfaces to realize parallel configuration, and state monitoring is carried out through 32 groups of UART (Universal Asynchronous Receiver / Transmitter) interfaces; configuration data are received externally by adopting an RGMII interface, and an upper computer is connected through a system UART. The method comprises the following steps that: after the FPGA is controlled to be self-started from the Flash, an upper computer issues a configuration data packet through the RGMII; the FPGA is controlled to synchronously drive 32 groups of Slave Serial time sequences to complete parallel configuration; the state is fed back in real time through a dual-mode monitoring mechanism, and timeout fault-tolerant logic is implanted. According to the configuration implementation method and system, the configuration efficiency is improved, interface signals are optimized and reduced, single-node fault isolation is supported, and the system availability is improved.

The application discloses a method and device for realizing high-speed operation of an algorithm based on a multi-level field cache, which comprises the following steps: a configuration management CPU sends algorithm parameters to an FPGA chip and saves the algorithm parameters in a RAM; a service processing CPU creates a handle and sends the handle to the configuration management CPU; the configuration management CPU generates a key number according to the handle; the configuration management CPU sends a key library to the FPGA chip; the service processing CPU sends a to-be-operated message to the FPGA chip; an algorithm scheduling module performs fragmentation judgment, and performs subsequent processing according to a sequence judgment result; a password operation module takes the received key, an initialization vector or an intermediate chain variable and the to-be-operated message as input, performs password operation, and outputs a calculation result and an operated intermediate chain variable; whether the to-be-operated message is the last data fragment is judged according to a tail fragment identifier, and subsequent processing is performed according to a tail fragment judgment result. The application can reduce the communication interface and CPU access times, realize high-speed operation of a password algorithm, and improve the overall performance of a password service system.

The invention discloses an EtherCAT master station distributed clock synchronization method based on an ARM and an FPGA, and relates to the technical field of industrial control, the method comprises the following steps: S1, using an FPGA chip integrated with the ARM and programmable logic resources to construct an EtherCAT master station distributed clock module, the ARM and the programmable logic resources interacting through an internal AXI interconnection bus; s2, the programmable logic resource obtains an enable signal sent by the ARM end, and if the enable signal is 1, the master station performs topology scanning, delay calculation, clock compensation and dynamic drift compensation operations on the slave station to obtain a delay compensation value and a local clock compensation value of the slave station; s3, after compensation is completed, the state machine of the master station automatically jumps to a synchronous signal generation module, SYNC parameters are obtained from the ARM end, and SYNC signal starting time of the slave station is calculated according to the SYNC parameters; s4, respectively converting the delay compensation value, the local clock compensation value and the starting time of the slave station into message information, sending the message information to the slave station, adding 1 to the address of the slave station, and returning to the step S1 until the distributed clock configuration of all the slave stations is completed; the EtherCAT master station distributed clock synchronization method solves the problem that a synchronization (SYNC) signal generated after a distributed clock algorithm is started is unstable, and shows potential and value in the field of higher-frequency slave station synchronization.

The invention discloses a circuit and a chip for enabling a CXL protocol to support a low-rate serial link. The circuit provided by the invention comprises a link management state machine containing a sending SDS state, a 4-byte clock skew compensation character SKP4B generation circuit and an analysis circuit, an encoder and a decoder supporting a data stream start character SDS, a 128b / 130b encoder and a decoder, a data stream start detection circuit, a 40: 1 parallel-serial conversion circuit, a 32: 1 parallel-serial conversion circuit, a multiplexer, a 1: 40 serial-parallel conversion circuit and a 1: 1 parallel-serial conversion circuit, the output end of the multiplexer is connected with the input end of the demultiplexer through a serial link, and the output end of the demultiplexer is connected with the input end of the demultiplexer through a serial link. The invention aims to enable the CXL protocol to extend and support PCIe Gen1 and Gen2 rates, so that the FPGA chip can use the CXL protocol, and the ASIC chip can use the CXL protocol at a low rate.

The invention discloses a control method of an interleaved parallel bidirectional DCDC converter. A circuit of the converter comprises three pairs of MOSFET switch tubes, three inductors and an output capacitor. The phase difference of PWM waves of the three pairs of MOSFET switch tubes is 120 degrees, and the phase difference is used for effectively reducing current ripples through staggered complementation of currents of all phases. Double closed-loop control is adopted, the DSP chip is responsible for current inner loop control, and the FPGA chip is responsible for voltage outer loop and power outer loop control. The current sharing precision is high, through flexible configuration of multiple proportionality coefficients and zero points, input fluctuation and load abrupt change interference can be accurately restrained, oscillation is avoided, stable output is ensured, and when load abrupt change or mode switching is carried out, output can be rapidly adjusted, transition time can be shortened, and overshoot can be reduced. And high dynamic response and strong robustness of the system are realized, so that complex and changeable application requirements are met.

The invention discloses an FPGA-based DDR3 cache circuit, which comprises an interconnection structure of an FPGA chip and a plurality of DDR3 storage chips, point-to-point direct connection is adopted for DQ / DQS / DM signals of the DDR3 chips, control / address / clock signals are shared with the DDR3 chips through a Fly-by topological structure, and the sequential relationship between CK + / CK-and DQS + / DQS-is adjusted through a write-in equalization technology. Through the point-to-point direct connection design of DQ / DQS / DM signals, the problems of reflection and crosstalk in a traditional topological structure are eliminated, and the error code risk is reduced; the time sequence relation between CK + / CK-and DQS + / DQS-is dynamically adjusted through the write-in equalization technology, and time sequence deviation caused by PCB wiring length and impedance mismatching or temperature change is compensated; the Fly-by topological structure is connected with control / address / clock signals, so that signal branches and reflection are reduced, and signal attenuation and crosstalk are reduced.

The invention discloses a digital twinning-based heat-assisted flow drilling and riveting control method and a digital twinning-based heat-assisted flow drilling and riveting control system. The method comprises the following steps: acquiring temperature, pressure, displacement and surface topography data; a temperature-pressure-morphology comprehensive index is constructed through weighted fusion; real-time processing is carried out through the FPGA chip and the lightweight AI model; a Pareto frontier solution set is generated in combination with a Monte Carlo-NSGA-II hybrid algorithm; constructing a heat-force-phase change coupling unified constitutive model to carry out multi-physics field reverse optimization; dynamic updating of process parameters is realized through a digital twinborn case library; and dynamically modulating PID parameters by adopting deep reinforcement learning. The system comprises a multi-source data acquisition terminal, an intelligent decision module and a dynamic control module. According to the method, the problems of parameter lag and poor adaptability of a traditional method are solved, and the processing task can be efficiently and accurately completed.

The invention provides a comprehensive display device based on an FPGA (Field Programmable Gate Array) and double-ARM processor architecture, and relates to the field of avionics, which is characterized in that flight attitude data of a target aircraft are firstly collected and transmitted to a first ARM processor through an MIPI (Mobile Industry Processor Interface), the data are preprocessed by the first ARM processor and then stored in an input buffer area of a double-port shared memory, and the input buffer area is used for storing the data into a second ARM processor; then the FPGA chip reads the preprocessed data from the input buffer area to generate a flight attitude indication image, the flight attitude indication image is written into the output buffer area, the second ARM processor reads the attitude indication image from the output buffer area, the attitude indication image and the navigation image are subjected to image synthesis based on semantic feature interaction to obtain a synthesized flight display image, the synthesized flight display image is stored in a display frame buffer area, and finally, the flight display image is displayed. And reading the synthesized image from the display frame buffer region, and transmitting the synthesized image to a multifunctional display screen of a cockpit for display through an LVDS interface. Therefore, more efficient, accurate and reliable flight information display can be realized.

The invention relates to the technical field of quantum computer control, and belongs to a quantum equipment instruction distribution system and method based on multi-thread parallel routing, the system comprises an upper computer, an instruction board, an instruction routing board and an equipment end, and the instruction distribution method comprises the following steps: S1, inputting a program instruction and a control instruction through the upper computer, the data is issued to the instruction board through the local bus interface; s2, multi-thread parallel execution of the program instruction is achieved in an instruction board FPGA chip, a control instruction is generated and output to a routing board through a high-speed radio frequency interface, and the control instruction comprises a target address code; s3, dynamically selecting an output port by the instruction routing board according to the target address code generated in S2, and distributing the instruction to specified equipment; and S4, each device in the device end receives the instruction through the SSMA sequence interface and executes the instruction. According to the invention, efficient synchronous control of quantum equipment is realized through multi-thread parallel execution and a dynamic routing mechanism.

The invention discloses a method for improving data transmission bandwidth through an FPGA. The method comprises the steps that a data packaging module of a detector main control board sends data to be transmitted to a multi-channel GTP sending end in parallel; the data acquisition card receives the data of the corresponding channels through the multi-channel GTP receiving end and recovers Data and KCOD of each channel; an FIFO read-write control module of the data acquisition card writes data recovered by multiple channels into asynchronous FIFOs corresponding to the channels through write logic, and data buffering is carried out; the FIFO read-write control module simultaneously reads cache data of a plurality of asynchronous FIFOs through read control logic to realize cross-clock domain synchronization of multi-channel data; performing CRC (cyclic redundancy check) and processing on the read multi-channel data to obtain synchronous effective transmission data; and a single-channel GTP is upgraded to a dual-channel GTP or a multi-channel GTP, so that the data transmission bandwidth is improved, and normal operation of the FPGA chip is ensured.

The invention relates to the field of infrared imaging image processing, in particular to a temperature sensing and image processing method and device based on an infrared camera, and the method comprises the following steps: S1, starting the infrared camera, capturing the infrared radiation of a detected object through a detector, generating original image temperature data, and transmitting the original image temperature data to an FPGA chip; s2, the FPGA chip receives and preprocesses the generated image temperature data; s3, converting the temperature data into an infrared grey-scale map in the FPGA chip, and then transmitting the infrared grey-scale map to the SOC chip; s4, the SOC chip uses a built-in super-resolution module to improve the resolution of the preprocessed image data; s5, analyzing the processed image data through a posture recognition module, recognizing and marking key parts of the measured object, and representing the key parts by using two-dimensional coordinates; s6, determining an accurate temperature distribution point of the measured object; and S7, storing the positioned temperature points as coordinates in a dictionary form, superposing the coordinates to the source image, and outputting the image to the cloud and the client.

The invention discloses a primary frequency modulation cooperative control system for a thermal power generating unit, and the system comprises a high-frequency data collection module which synchronously collects the frequency of a power grid, the valve position of a steam turbine and the main steam pressure through an FPGA chip, calculates the frequency change gradient, and activates a rapid frequency modulation mode when the frequency change gradient exceeds a preset range or not; the multi-modal compensation decision module is used for calling a multi-modal dynamic compensation model to predict a power gap in a future time period and distributing a compensation amount; the safety constraint execution module is used for monitoring the main steam pressure deviation and triggering the reinforcement learning agent to update the parameter library when the main steam pressure deviation exceeds the preset load change rate; and the parameter optimization module is used for carrying out reinforcement learning dynamic adjustment on state space and action space parameters, and integrating security constraint indexes in a reward function. Through collaborative design of multi-mode dynamic compensation, intelligent parameter optimization and security constraint protection, the problems of response delay, parameter mismatch and security risk of a traditional frequency modulation technology are solved, and the method has remarkable technical innovation and engineering application value.

The invention discloses an imaging dynamic range expansion method based on variable integral time, and relates to the field of infrared imaging. The method comprises the following steps of: firstly, sending an infrared original image acquired by a medium-wave infrared movement to an FPGA (Field Programmable Gate Array) chip, decoding integral time of the infrared original image, and converting a signal format; then the integral time information and the converted infrared image signal are synchronously sent to a non-uniformity correction module, and non-uniformity noise is corrected; performing dynamic range expansion of the fused image signal on the corrected image signal through a variable integral time imaging algorithm; and finally, digitally displaying the obtained fused image signal. The core innovation of the method is that a hierarchical integral time segmentation calibration model is established, and a non-uniformity correction parameter dynamically matched with integral time is obtained. The method breaks through the physical limitation of single-frame integration time, the low-temperature background signal-to-noise ratio is remarkably improved while high-temperature target details are reserved, and the method is particularly suitable for the refined imaging requirement of a high-dynamic complex infrared scene.

The invention discloses a universal detection system and method for providing different types of connection interfaces, and the method comprises the steps: simulating a boundary scanning element through an FPGA chip of a universal test card, and cooperating with an RC circuit and a differential signal mode conversion element; therefore, different types of to-be-tested interfaces can be provided, the same general test card can be used for pin detection of an input and output pin, a grounding pin, a differential signal pin, a power supply pin and a differential clock signal pin, and the technical effect of universal detection of different types of connection interfaces can be achieved.

The invention provides a digital model of an FPGA configuration circuit, an FPGA data configuration method, equipment and a medium. The digital model comprises a parameter configuration module, a read-write processing module and a configuration state determination module. According to the digital model provided by the invention, the configuration of the digital model is realized through the parameter configuration module, so that the digital model can adapt to FPGA chips of different models, an FPGA configuration circuit does not need to be greatly modified, and the universality is high; the configuration of the FPGA chip and the configuration state detection are realized through the read-write processing module and the configuration state determination module, so that the configuration of the FPGA chip can be effectively completed; and the digital model adopts a partitioning design, so that a user can efficiently maintain and upgrade each module, and can expand on the basis of functional modules to support more types of FPGA chips and meet more configuration scene requirements.

The invention provides a trusted startup system and a startup method of the trusted startup system, and belongs to the technical field of communication, the system comprises an on-chip ROM (Read Only Memory) located in a CPU (Central Processing Unit), a one-time programmable memory located in the CPU, a password acceleration engine located in the CPU and an FPGA (Field Programmable Gate Array) chip connected with the CPU, the system comprises an FPGA (Field Programmable Gate Array) chip, a startup firmware chip, a system file chip and a system file backup chip which are connected with the FPGA chip, an on-chip boot program stored in an on-chip ROM (Read Only Memory), a trusted password module stored on a password acceleration engine, and Feiteng basic firmware, Feiteng universal firmware and a trusted system which are stored in startup firmware, and the self-developed Linux system is stored in the system file and the system file backup. According to the method, the system and the system starting process are completely credible, including security, credibility and tamper-proofing of all files in the system starting operation process, and security starting and tamper-proofing of the system are ensured in a mode of combining software design and hardware design.

The invention discloses an integrated fire detection intelligent lamp for a railway tunnel. The integrated fire detection intelligent lamp comprises a multi-mode sensing module, an integrated thermal imaging array sensor, a multispectral flame sensor, a laser scattering type smoke sensor and an electrochemical CO sensor. An FPGA chip and a lightweight convolutional neural network model are arranged in the signal processing module, space-time fusion analysis is carried out on multi-modal sensing data in real time, and a fire judgment threshold is dynamically optimized through transfer learning; the dynamic ad hoc network communication module supports dual protocols of LoRaWAN and TSN; the adaptive power supply adopts an AC / DC power conversion module, integrates a piezoelectric vibration energy collection module and a thermoelectric power generation module, and combines a super capacitor and a lithium battery to realize quintuple redundant power supply; and the three-dimensional lighting array consists of a plurality of groups of independently controlled LED matrixes and is used for dynamically adjusting a lighting area and brightness distribution. The fire hazard detection sensitivity is improved through multi-dimensional data fusion, the illumination function is achieved, and the use requirement of the railway tunnel in the severe environment is met.

The invention provides a universal reset system applied to an FPGA chip configuration circuit, and relates to the technical field of universal reset, reset signals generated in the FPGA configuration process are classified through a reset request circuit, and preset signal processing is executed according to preset function scenes and priorities; selecting a plurality of reset requests through a reset selection circuit, and responding to the reset requests according to a preset priority sequence; a reset signal from a reset request circuit is synchronously processed through a reset synchronous processing circuit, and the control signal is transmitted between clock domains; after the reset operation is completed through the reset release circuit, the FPGA is converted from the reset state to the normal working state, the FPGA configuration reset circuit can meet the FPGA configuration reset requirements in various scenes, and the metastable state problem in the reset signal transmission process can be effectively solved.

The invention discloses a cuff-free calibration-free flexible patch type blood pressure detection system based on an ultrasonic echo method, and relates to the technical field of blood pressure detection of biomedical engineering. Comprising a transmitting and receiving integrated probe, a transmitting circuit, an amplitude limiting circuit, an amplifying circuit, a filter circuit, an A / D conversion circuit, an FPGA chip, a Bluetooth module and a mobile terminal. Wherein the FPGA chip outputs a high-frequency signal, a low-voltage signal is converted into a negative high-voltage signal through the transmitting circuit to drive the ultrasonic transducer, the ultrasonic transducer generates ultrasonic waves under excitation and receives an echo signal from a blood vessel wall, the echo signal firstly passes through the amplitude limiting circuit, and the high-voltage component is limited while the signal is received; signals sequentially pass through the amplification circuit and the filter circuit, finally voltage signals are converted into digital signals through the A / D conversion circuit, and after the digital signals are processed by the FPGA chip, data are sent to a mobile terminal through the Bluetooth module. The accuracy of blood pressure detection is improved.

The invention relates to the technical field of high-speed interfaces, and discloses a channel binding method, device, equipment, medium and program product.The method is applied to the receiving direction of an FPGA chip and comprises the steps that a data transmission protocol is obtained, and the number of channels is determined according to the data transmission protocol; determining a primary channel and a secondary channel based on the number of channels; when the main channel receives target data and confirms a target frame header of the target data, the main channel is controlled to send out an alignment signal; the alignment signal is transmitted to the secondary channel through the whole internet; when the secondary channel receives the alignment signal, a first-in first-out queue read pointer corresponding to the secondary channel is adjusted, so that the secondary channel is aligned with the primary channel; and after the first-in first-out queue read pointers corresponding to the secondary channels are adjusted, reading data from the first-in first-out queues corresponding to the secondary channels, and outputting the data from a data port in the receiving direction of the physical coding sub-layer. The method can meet the requirements of different protocols for the number of bound channels, and greatly improves the flexibility of channel binding.