324 results about "Fpga chip" patented technology

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

The embodiment of the invention discloses a 4K splicing processor and a 4K splicing display system. The 4K splicing processor comprises a driving circuit used for processing a 4K resolution signal, the driving circuit comprises an FPGA chip U5, TVS array chips U10, U11, U12 and U13 and DP signal line connectors CN9 and CN10; the model of the U5 is Spartan-6, the models of the U10, the U11, the U12 and the U13 are all RClamp0524P, the CN9 is connected with the U5 through the U10 and the U11, and the CN10 is connected with the U5 through the U12 and the U13; the U5 receives the input 4K resolution signal through the CN9 to process the 4K resolution signal and outputs the processed 4K resolution signal through the CN10 to achieve 4K resolution signal looping. According to the 4K splicing processor and the 4K splicing display system, the problem that 4K splicing display system equipment is complex is solved.

The invention discloses a control method of an interleaved parallel bidirectional DCDC converter. A circuit of the converter comprises three pairs of MOSFET switch tubes, three inductors and an output capacitor. The phase difference of PWM waves of the three pairs of MOSFET switch tubes is 120 degrees, and the phase difference is used for effectively reducing current ripples through staggered complementation of currents of all phases. Double closed-loop control is adopted, the DSP chip is responsible for current inner loop control, and the FPGA chip is responsible for voltage outer loop and power outer loop control. The current sharing precision is high, through flexible configuration of multiple proportionality coefficients and zero points, input fluctuation and load abrupt change interference can be accurately restrained, oscillation is avoided, stable output is ensured, and when load abrupt change or mode switching is carried out, output can be rapidly adjusted, transition time can be shortened, and overshoot can be reduced. And high dynamic response and strong robustness of the system are realized, so that complex and changeable application requirements are met.

The invention discloses a method for improving data transmission bandwidth through an FPGA. The method comprises the steps that a data packaging module of a detector main control board sends data to be transmitted to a multi-channel GTP sending end in parallel; the data acquisition card receives the data of the corresponding channels through the multi-channel GTP receiving end and recovers Data and KCOD of each channel; an FIFO read-write control module of the data acquisition card writes data recovered by multiple channels into asynchronous FIFOs corresponding to the channels through write logic, and data buffering is carried out; the FIFO read-write control module simultaneously reads cache data of a plurality of asynchronous FIFOs through read control logic to realize cross-clock domain synchronization of multi-channel data; performing CRC (cyclic redundancy check) and processing on the read multi-channel data to obtain synchronous effective transmission data; and a single-channel GTP is upgraded to a dual-channel GTP or a multi-channel GTP, so that the data transmission bandwidth is improved, and normal operation of the FPGA chip is ensured.

The invention discloses an integrated fire detection intelligent lamp for a railway tunnel. The integrated fire detection intelligent lamp comprises a multi-mode sensing module, an integrated thermal imaging array sensor, a multispectral flame sensor, a laser scattering type smoke sensor and an electrochemical CO sensor. An FPGA chip and a lightweight convolutional neural network model are arranged in the signal processing module, space-time fusion analysis is carried out on multi-modal sensing data in real time, and a fire judgment threshold is dynamically optimized through transfer learning; the dynamic ad hoc network communication module supports dual protocols of LoRaWAN and TSN; the adaptive power supply adopts an AC / DC power conversion module, integrates a piezoelectric vibration energy collection module and a thermoelectric power generation module, and combines a super capacitor and a lithium battery to realize quintuple redundant power supply; and the three-dimensional lighting array consists of a plurality of groups of independently controlled LED matrixes and is used for dynamically adjusting a lighting area and brightness distribution. The fire hazard detection sensitivity is improved through multi-dimensional data fusion, the illumination function is achieved, and the use requirement of the railway tunnel in the severe environment is met.

The invention discloses an SOC prototype verification logic division method and system based on resource constraints. The method comprises the steps that a to-be-verified SOC prototype is split into modules meeting the resource constraints of an FPGA; the split modules are tried to be combined in pairs to form modules meeting the resource constraint of the FPGA; 1 is added to the loop variable i of the finally obtained module according to the sequence of the number of the external connecting lines from large to small, and the FPGAs are distributed in the multi-FPGA verification platform; integrating the modules distributed with the FPGAs to generate a netlist file; and converting the netlist file into a bit stream file and downloading the bit stream file into the distributed FPGA. According to the method, the process of mapping SOC design to multiple FPGAs is achieved, logic division is rapidly achieved for the design, rapid time sequence convergence is achieved through reasonable arrangement of resources, the FPGA chip resource utilization rate is increased, and time sequence optimization iteration of a net list after integration is reduced.

The invention discloses a time synchronization method, a time synchronization system and a storage medium, and the method comprises the steps: receiving and fusing multi-source time signals at the same time, and obtaining a local time reference signal; calculating the frequency compensation amount of a local clock source in real time based on an LSTM model trained by using a local time reference signal; detecting whether the time signal is available, and determining to switch an atomic clock taming mode or a timekeeping mode based on a detection result; inserting a timestamp with femtosecond precision for the initial data message through the PIC to obtain a target data message; and sending the time synchronization information and the target data message to a 6G network node through a precision time protocol of the FPGA chip. According to the invention, on the basis that the satellite signal is taken as a time reference, two conditions that the satellite signal is available and unavailable are considered, and a local clock source and photon time service are adjusted in combination with a multi-source satellite signal fusion result, so that the time synchronization precision is improved, and the 6G network requirement is met.

The invention relates to a non-contact high-precision pipe network damage detection system, which relates to the technical field of underground pipe network detection, and comprises a bimodal sensing unit, a data processing unit, a self-adaptive optical unit, a protective shell and a power management module. Through cooperation of the infrared thermal imaging module and the laser scanning module, millimeter-level precision can be realized, a visible light camera or a near-infrared camera can be automatically switched according to environmental turbidity through arrangement of a light filtering switching mechanism, clear imaging in a turbid water body can be ensured, and through a built-in FPGA chip of the data processing unit, the data processing unit can be used for realizing high-definition imaging of the visible light camera or the near-infrared camera. Through cooperation of the bimodal sensing unit, the data processing unit and the adaptive optical unit, temperature field and point cloud data can be synchronously acquired, after fusion, + / -3mm damage positioning precision can be realized, and when the turbidity is greater than 200NTU, high reliability can still be maintained, the detection efficiency can be improved, and the detection precision can be improved. And the risk of manual underwater operation is thoroughly avoided.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

The invention relates to the technical field of chip design simulation verification, in particular to a memory type dynamic determination method for prototype verification and hardware simulation, and the method comprises the steps: carrying out sub-design division according to the module level of each module in a user netlist in combination with a first resource threshold sequence corresponding to an FPGA (Field Programmable Gate Array), and fitting the design logic clustering characteristics; according to the method, the hardware segmentation requirements of cross-sub-design interconnection and adaptation to multi-FPGA prototype verification are reduced, the layout and wiring difficulty is reduced, the performance and frequency of the FPGA are effectively improved, storage type allocation is realized according to the first target conversion rate and the second target conversion rate of the object and the target memory type, and the storage efficiency is improved. Relative balance and independence of various kinds of memory resources are achieved in the sub-design as much as possible, the number of FPGA chips needed for achieving the sub-design is reduced, and equivalently, the performance of the FPGA is improved.

The application relates to the technical field of chip verification, and discloses an FPGA chip DSP module bit stream verification method and device. In the method, a bit stream file generation method is used to convert configurable parameters of a DSP module from abstract test intentions into specific physical configuration files, the low efficiency of configuring bit stream files for the functions of each DSP module is avoided, then a two-stage routing analysis method is used for function verification of the DSP module, a complete signal path mapping between an SWH port and core logic of the DSP module is accurately constructed, the correctness of the functions of the DSP module itself is ensured, and the interconnection correctness of the DSP module and adjacent modules is ensured, then an initial verification platform is reconstructed based on a port mapping table, and a high-abstraction-level behavior model is combined for result comparison, the verification efficiency and reliability of the DSP module are greatly improved, and the efficiency and accuracy of bit stream verification of the FPGA chip DSP module are ensured.

The application discloses a kind of master station controller control method, device, equipment and storage medium, the method includes: FPGA chip generates bus cycle interruption and pulse output completion interruption, and bus cycle interruption and pulse output completion interruption are sent to CPU unit;CPU unit obtains the time difference between master station system clock and slave station system clock in bus cycle interruption;Obtain cycle planning data in pulse output completion interruption, and write time difference and cycle planning data into FPGA chip;FPGA chip is simultaneously controlled according to time difference and cycle planning data to bus and pulse output control.The time difference between master station system clock and slave station system clock obtained by CPU unit and cycle planning data are written into FPGA chip in the application, and FPGA chip is simultaneously controlled according to time difference and cycle planning data to bus and pulse output control, and the simultaneous control of pulse motor and bus motor is realized.

The present disclosure relates to a TCP mirror data processing method, device, chip and medium, wherein the method comprises: constructing a second buffer in the FPGA chip when it is determined according to a first current TCP mirror packet that a preset TCP reconnection condition is met; when the first buffer contains a target TCP mirror packet to be output, opening the read interface of the first buffer and the write interface of the second buffer, and closing the read interface of the second buffer and the write interface of the first buffer; when the first buffer does not contain a target TCP mirror packet to be output, closing the read interface of the first buffer and opening the read interface of the second buffer, and sending the corresponding TCP mirror packet to the server through the read interface of the second buffer. In this technical solution, the out-of-order rearrangement processing based on the heterogeneous structure is realized, and it is ensured that the normal out-of-order rearrangement operation is not affected during the reconnection, the smooth transition is realized, and the continuity and integrity of the out-of-order rearrangement processing are ensured, thereby improving the reliability and stability of the heterogeneous structure.

The utility model discloses a programmable logic device test experiment device, which relates to the field of logic device test experiments and comprises a replaceable FPGA test circuit, a phase-locked loop test circuit, a pulse width modulation test circuit, a chip power supply circuit, a serial port test circuit, a Bank area power supply test circuit, a power supply generation circuit and a liquid crystal display control circuit. According to the experimental device for testing the programmable logic device, through a mode of combining the liquid crystal display screen and the FPGA function test board, a large-scale test machine in traditional test equipment is omitted, so that a test system is more portable, comprehensive coverage test of FPGA chip functions can be realized through compiling a plurality of self-test programs, and the test efficiency is improved. Therefore, not only can the basic logic function of the FPGA be tested, but also the advanced characteristics and boundary conditions of the FPGA can be deeply verified, so that the function correctness of the FPGA chip can be more comprehensively ensured.

The invention discloses a configurable multi-specification video stream transmission method and device based on an FPGA chip AXI bus, and is applied to the technical field of data processing.The method comprises the steps that a single FPGA chip serves as a core, a user transmission instruction is received firstly, pre-stored AXI bus bandwidth allocation, PL / PS end interaction, video source access and coding and decoding parameters are combined, and a multi-specification video stream is obtained; and generating transmission mode starting and bus configuration information. Then, PS end encoding and decoding are started, a PL end preset path is triggered to be started, and video source information and bus real-time bandwidth data are obtained; through standardized conversion and bandwidth processing, comparison reference information of the size of an RGB image and a bus target bandwidth is generated, an error signal and channel adjustment information are generated based on a bandwidth dynamic random allocation control rule, channel control operation information is obtained in combination with a chip internal resource state, and finally the channel control operation information is converted into a transmission action. According to the method, adaptive parameters, calibration rules and the like are extracted, classified and generated, efficient transmission of multi-specification video streams is achieved, the total bandwidth is fixed, and the bandwidth of each path of coding is flexibly allocated.

The application discloses a FLASH application verification system based on FPGA, which comprises a PC, an FPGA application verification board and a FLASH subboard. The FPGA application verification board is provided with two FPGA chips; each FPGA chip is connected with the FLASH and can independently access the FLASH to perform verification operation; each FPGA is externally connected with a large-capacity 160Mb SRAM; and the NOR_FLASH and the SPI_FLASH can be verified by replacing the FLASH subboard. The application also discloses a verification method based on the system, which comprises the following steps: determining power-on sequence, JTAG function verification, digital logic verification and read-write function verification. The application has comprehensive verification function, strong universality and important significance for application verification of a series of FLASH.

The invention discloses a multi-path stepping motor control device and method, and relates to the field of motor control, and the device comprises a microcontroller and an FPGA chip. The microcontroller is connected with the FPGA chip; the microcontroller is used for checking whether multi-path trapezoidal acceleration and deceleration curve parameters which are input by a user and represent the motion of the stepping motor accord with the motion characteristics of the stepping motor; if the trapezoidal acceleration and deceleration curve parameters do not conform to the motion characteristics of the stepping motor, the trapezoidal acceleration and deceleration curve parameters are corrected and serve as final trapezoidal acceleration and deceleration curve parameters; if the motion characteristics of the stepping motor are met, the parameters of the trapezoidal acceleration and deceleration curve are kept unchanged and serve as final parameters of the trapezoidal acceleration and deceleration curve; the final trapezoidal acceleration and deceleration curve parameters are sent to the FPGA chip; the FPGA chip is used for generating multiple paths of pulse signals in parallel according to the final trapezoidal acceleration and deceleration curve parameters so as to drive multiple paths of stepping motors, and motor control which is simple, feasible, high in real-time performance, more efficient and low in cost is achieved.

This invention discloses a method and system for monitoring and resetting the software heartbeat of a spaceborne receiver. The system includes a dual-channel GNSS positioning module, a dual-channel orbit determination module, and an antifuse FPGA chip. Both the GNSS positioning module and the orbit determination module have corresponding primary and backup FLASH memory. The antifuse FPGA acts as the heartbeat monitoring and control center, connecting to the GNSS positioning module and the orbit determination module via GPIO interfaces. It receives the software heartbeat signals from each module and sends reset commands to faulty modules via reset pins. This solution solves the problems of poor radiation resistance, low fault identification accuracy, and low recovery efficiency in existing spaceborne receiver software fault monitoring.

The invention particularly relates to a multi-source information fusion method and system based on FPGA hardware acceleration. The method comprises the steps that sine and cosine calculation is achieved through a lookup table in a main FPGA chip, high-precision mapping can be completed in a single clock period, hardware-level acceleration is provided for point cloud coordinate conversion, and the problem that traditional CPU / GPU serial calculation is low in efficiency is solved. The slave FPGA chip is utilized to carry out block storage on multi-path image data and point cloud drawing data according to a spatial sequence, multi-path parallel processing in a data fusion process is realized, the data processing efficiency is improved, and the real-time requirement is met. In addition, lightweight fusion is realized through existence judgment of the same address, and invalid data storage is reduced.

This invention relates to a miniature sensor for engine ignition monitoring based on a thermopile infrared sensor. It includes: a housing, a thermopile infrared detector, and a power module, a main control unit, and a communication unit disposed within the housing. The main control unit is an FPGA chip containing an ARM processor and a SOC core. The power module is connected to the thermopile infrared detector, the main control unit, and the communication unit, respectively, to provide voltages for the corresponding parameters of each device. The communication unit is connected to the main control unit to send monitoring commands and the target area for engine ignition monitoring. The infrared detector is connected to the main control unit, and the main control unit controls the infrared detector to monitor the ignition plume within the target area based on the monitoring commands to obtain raw measurement data. The main control unit is also used to calculate the raw measurement data and determine the engine ignition state based on the calculation results. The miniature sensor designed in this application is lightweight, small in size, and can quickly monitor the engine ignition state.

The embodiment of the invention provides a message shunting method and device and network equipment, and relates to the technical field of communication, the method is applied to an FPGA chip, and the method comprises the following steps: receiving a to-be-shunted message, and obtaining a message feature of the to-be-shunted message; a rule table item matched with the message feature is searched from a preset core dividing rule table, the rule table item comprises first uploading information, and the first uploading information comprises a first uploading core identifier used for indicating a CPU core and a first uploading mode used for representing an uploading core selection mode; determining a target core in the CPU according to the first uploading mode and the first uploading core identifier; and sending the to-be-shunted message to the target core. By adopting the method, the performance pressure of the CPU can be reduced, and the processing performance of equipment is improved.

The utility model relates to an autonomous controllable traction power supply feeder protection measurement and control device, which comprises a CPU (central processing unit) plug-in unit, an alternating current plug-in unit, an input plug-in unit, an output plug-in unit, an operation plug-in unit, a power supply plug-in unit, a panel plug-in unit and a mother board plug-in unit which are connected through plug-in terminals. The panel plug-in and the mother board plug-in are connected through the flat wire harness. The CPU plug-in comprises a domestic CPU chip and a domestic FPGA chip, the domestic CPU chip and the domestic FPGA chip are in data communication through an LIO bus and a high-speed PCIE, and the CPU plug-in communicates with the panel plug-in through an Ethernet interface to achieve a man-machine interface function. Input quantity acquisition and switch control output are realized through interaction information of the input and output bus, the input plug-in and the output plug-in; the device provided by the utility model has strong practical value and application prospect.

The application provides an FPGA-based optical computing communication and control module and belongs to the technical field of optical computing.The development board comprising an FPGA chip, an AD / DA module, an output input interface module, a clock module and a memory module is adopted, so that the module can perform four-channel AD / DA signal processing and has rich interfaces to support high-speed information processing and transmission, thereby providing an ideal communication platform for the optical computing module and the neural network and providing the ability of real-time high-speed weight updating of the optical computing module.

This invention discloses a user-end beam control system for a KuKa dual-band multi-beam antenna, comprising: an FPGA module for receiving instruction information from a payload integrated electronics system, generating various control signals and sending them to the KuKa dual-band multi-beam antenna, and also for receiving telemetry information from the KuKa dual-band multi-beam antenna, integrating it into a telemetry data packet and sending it to the payload integrated electronics system; a clock management module for receiving a reference clock signal from an external frequency source and generating the operating clock required by the FPGA module; an interface module for providing a serial communication interface and serial driver, an LVDS control interface and driver, and a debugging interface; and a debugging module for debugging the software running within the FPGA chip. This invention can quickly and independently adjust the beam pointing of the Ku and Ka bands of the KuKa dual-band multi-beam antenna and acquire telemetry data from the KuKa dual-band multi-beam antenna in real time.

The application discloses a FPGA global reset synchronization circuit, a chip, a verification simulation system and a method. The FPGA global reset synchronization circuit comprises a clock signal channel and a reset signal channel. The clock signal channel comprises a filter and a frequency multiplier. The filter is used for filtering an input first clock signal, the frequency multiplier is used for frequency multiplication after the filtering, a second clock signal is generated, the frequency of the second clock signal is an integer multiple of the first clock signal, and the second clock signal is output to provide a clock signal for user logic in the FPGA chip. The reset signal channel comprises a cross-clock-domain transmission circuit. The cross-clock-domain transmission circuit is used for outputting an input reset signal after the cross-clock-domain transmission to provide a global reset signal for the user logic in the FPGA chip. The application does not depend on the distance of the FPGA and the length of the signal line, and is especially suitable for clock reset synchronization of a large number of FPGAs when the FPGAs are used for chip verification and simulation.

The invention discloses a low-coherence interference microstructure rapid measurement method based on an FPGA, and the method comprises the steps: enabling the FPGA to respectively receive image data and single-point light intensity data collected by a CMOS sensor and a photoelectric detector, and transmitting the two types of data to an FPGA chip internal memory; a parallel pipeline architecture of the FPGA is designed, so that interference pattern contrast can be calculated in real time and displacement point-by-point calculation can be completed while a series of image data and photoelectric detector interference analog signals are received, and the processing efficiency is remarkably improved; and calculating the position of an interference envelope peak value by adopting a gravity center method, completing three-dimensional shape detection of the microstructure, and realizing three-dimensional shape reconstruction. According to the method, the processing speed of low-coherence interference measurement can be effectively increased, the microstructure morphology can be restored at a high speed, and online detection application of low-coherence interference in the fields of semiconductor packaging, lithium battery manufacturing, ultra-precision machining and the like is facilitated.

The embodiment of the application discloses a FPGA chip inter data transmission method, device, system and storage medium, and the technical scheme provided by the application establishes a data link between a master FPGA chip and a slave FPGA chip, then the master FPGA chip and the slave FPGA chip transmit data based on the data link, since the data link only transmits data information and does not transmit control information, therefore the data transmission efficiency is improved; in addition, the user data is crossed from a user clock domain to a transmission clock domain when data is transmitted, and the received data is crossed from the transmission clock domain to the user clock domain when received, so that continuous data transmission is realized, and the data transmission rate is further improved; when multiple data links exist, a synchronous buffer is arranged at the sending end or the receiving end, so that the data of each data link is aligned, the data reliability is improved, and the problem that the data overhead is large and the high-speed data transmission is not suitable in the prior art is solved.

The utility model belongs to the technical field of programming tools, and discloses a tool for programming and debugging wireless image transmission module software, which comprises a metal platform, and a step part is arranged on the periphery of the metal platform and is used for bearing a wireless image transmission module circuit board; a clamp is mounted on one side of the metal platform, the clamp comprises a lower clamping jaw and an upper clamping jaw, the lower clamping jaw is fixed at the bottom end of the metal platform, an elastic contact pin is mounted on the upper clamping jaw, and the elastic contact pin corresponds to a pin position of an FPGA chip on a wireless image transmission module circuit board. According to the utility model, a software burning and debugging tool is customized according to the structure of the wireless image transmission module, the connection of the FPGA chip is rapidly completed and the rapid burning and debugging of the program are realized through the use of the clamp, and the elastic contact pin 23 is fixed through the double-layer PCB, so that the connection stability is improved, and the program burning and debugging efficiency of the FPGA chip is improved.

The utility model belongs to the field of block chains and the technical field of computer hardware circuit design, particularly relates to a computer mainboard hardware system supporting block chain acceleration, and aims to improve the intelligent contract execution efficiency of a block chain system through hardware architecture innovation, enhance the reliability of time and position verification of data, and improve the efficiency of the computer mainboard hardware system. And low-delay data synchronization among the nodes is realized to optimize the performance of the consensus mechanism. According to the main scheme, the system comprises a system basic function module, a peripheral interface circuit, a Beidou positioning hardware module and a reflection memory hardware module. The system basic function module comprises a CPU (Central Processing Unit) integrated with a special coprocessor, a memory unit, a storage unit, a clock unit and a power supply unit; the Beidou positioning hardware module is connected with the antenna unit through the MCU and the Beidou chip to generate time and position verification data of block chain transaction; and the reflective memory hardware module comprises an FPGA chip, a storage medium and an optical communication unit, and is connected with a plurality of block chain nodes through optical fibers to realize data synchronization.

The invention discloses a lightweight space satellite detection positioning method, a hardware architecture and a space probe, and relates to the technical field of deep space exploration. The method comprises the following steps: receiving and preprocessing a space environment image; constructing a lightweight convolutional neural network model, wherein the lightweight convolutional neural network model comprises a multi-scale convolutional feature extraction and fusion module and a decoupling multi-scale detection head module; processing the received space environment image through a multi-scale convolution feature extraction and fusion module, and generating a feature map fusing multi-scale semantics and space details; and performing parallel classification prediction, foreground prediction and bounding box regression on the fused feature map through a decoupling multi-scale detection head module, and outputting a satellite target detection result. According to the method, semantic information and spatial details of target features are enhanced through multi-scale convolution feature extraction and fusion, the detection effect of a small target is remarkably improved, and the model can be deployed on a satellite-borne FPGA chip with limited resources through deep pruning and quantitative design.