2989 results about "Fpga chip" patented technology

The complexity of user designs, the limited capacity of FPGA chips, and the limited number of chip pinouts have resulted in the development of inter-chip communication technology that necessitates the transfer of a large amount of data across a limited number of pins in the shortest amount of time. The inter-chip communication system transfers signals across FPGA chip boundaries only when these signals change values. Thus, no cycles are wasted and every event signal has a fair chance of achieving communication across chip boundaries. The inter-chip communication system includes a series of event detectors that detect changes in signal values and packet schedulers which can then schedule the transfer of these changed signal values to another designated chip. Working with a plurality of signal groups that represents signals at the separated connections, the event detector detects events (or changes in signal values). When an event has been detected, the event detector alerts the packet scheduler. The packet scheduler employs a token ring scheme as follows. When the packet scheduler receives a token and detects an event, the packet scheduler “grabs” the token and schedules the transmission of this packet in the next packet cycle. If, however, the packet scheduler receives the token but does not detect an event, it will pass the token to the next packet scheduler. At the end of each packet cycle, the packet scheduler that grabbed the token will pass the token to the next logic associated with another packet.

The invention discloses a system and a method for controlling a multi-cameral digital aerial photographic camera synchronous exposure. The system comprises an upper computer, an FPGA (Field-programmable Gate Array) chip as well as a first cameral, a second cameral, a third camera, a fourth camera and a fifth camera which are electrically connected with the FPGA chip, and the upper computer is in communication connection with the series port of the FPGA chip. The method comprises the steps as follows: receiving and pre-treating exposure signals; analyzing the exposure characteristics of different cameras and obtaining time sequence relation; regulating the time sequence of exposure signals according to the time sequence relation; outputting five types of controllable pulse triggering signals in a counting delay triggering way; triggering and controlling the first camera, the second camera, the third camera, the fourth camera and the fifth camera to synchronously execute exposure operation. The system and the method, provided by the invention, ensure the image synchronization precision of the exposure time of the multiple cameras.

The invention discloses a field programmable gate array (FPGA)-based integrated circuit testing system, and a method for testing a digital-analog hybrid integrated circuit chip provided with a digital module or using a digital module as a main module and provided with a few analog modules by using the testing system. The system mainly comprises a personal computer (PC) machine, a main control chip, a FPGA chip, configuration information storage equipment and testing vector storage equipment. The testing method is implemented by the following steps that: the main control chip configures the FPGA chip, the main control chip sends a testing command to the FPGA chip, the FPGA chip sends an excitation signal to a chip to be tested and acquires the output response of the chip to be tested, or the analog parameter module acquires analog output response, the FPGA chip compares the output response or the analog output response of the chip to be tested with the testing information and judges the consistency of the output response and the testing information, and the chip to be tested is an accepted product or a defective product is judged. The system and the method can be widely applied in the field of integrated circuit chip test.

The invention relates to a phased array radar antenna beam control device. The phased array radar antenna beam control device comprises a remote control PC (Personal Computer) computer, a user control computer module, a power supply management module, a FPGA (Field Programmable Gate Array) chip, a signal driver, a wave control conversion circuit and a controlled device which is electrically connected with the wave control conversion circuit, wherein the user control computer module remotely communicates with the remote control PC computer and are electrically connected with the FPGA chip, thepower supply management module and the wave control conversion circuit, respectively. The FPGA chip is embedded with a PowerPC hardcore and used for constructing an embedded computer; the embedded computer also comprises an Ethernet (Media Access Control), a UART (Universal Asynchronous Receiver Transmitter) controller, a DDR2SDRAM (Double Data Rate 2 Synchronous Dynamic Random Access Memory) memory module, a FLASH controller module, a parallel controller, a FPGA configuration circuit module and a clock generating circuit module. The phased array radar antenna beam control device provided by the invention has the advantage of high reliability.

A field programmable gate array has security configuration features to prevent monitoring of the configuration data for the field programmable gate array. The configuration data is encrypted by a security circuit of the field programmable gate array using a security key. This encrypted configuration data is stored in an external nonvolatile memory. To configure the field programmable gate array, the encrypted configuration data is decrypted by the security circuit of the field programmable gate array using the security key stored in the artwork of the field programmable gate array. The secret key comprises a number of bits of key information that are embedded within the photomasks used in manufacture the FPGA chip.

The invention discloses a VPX parallel DSP (Digital Signal Processing) board card based on SoC (System on a Chip) online reconstruction. An FPGA (Field Programmable Gate Array) chip is used as a board stage SoC controller; and two DSP chips are used as core operation chips of a DSP board card. During the practical configuration of the DSP chips, the FPGA chip used as the SoC controller can complete the dynamic re-configuration of work code by GE (Gigabit Ethernet) through the hardware resetting on the DSP and the switching on the starting mode; and the flexibility and the real-time performance during the DSP are greatly improved. The DSP chips receive two kinds of high-speed serial bus signals of SRIO (Serial Rapid Input Output) X4 and the GE transmitted through a VPX interface, repacking the transferred PCIE (Peripheral Component Interface Express) X2 high-speed serial bus signal through a PCIE exchange chip, and receives a data signal to be processed and a control instruction; or the DSP chips receive the GE protocol signal of a peripheral component through an RJ45 net port.

Provided is a parallel multi-core FPGA digital image real-time zooming processing method and device. The method comprises the steps that original video image data to be processed are acquired firstly. The original video image data are inputted to an FPGA chip and the number of zooming cores is confirmed, and the original video image data are divided into image sub-blocks having the same number with that of the zooming cores. Then the divided data are stored in a buffer, the data in the buffer are returned to the FPGA and parallel zooming processing is performed on each image sub-block via one zooming core respectively so that zooming is completed. All the image sub-blocks after zooming are displayed after splicing processing. The method has certain guiding effect on high throughput and high real-time application of digital video images.

The invention provides an ultra-scalable supercomputer based on MPU architecture in achieving the well-balanced performance of hundreds of TFLOPS or PFLOPS range in applications. The supercomputer system design includes the interconnect topology and its corresponding routing strategies, the communication subsystem design and implementation, the software and hardware schematic implementations. The supercomputer comprises a plurality of processing nodes powering the parallel processing and Axon nodes connecting computing nodes while implementing the external interconnections. The interconnect topology can be based on MPU architecture and the communication routing logic as required by switching logics is implemented in the FPGA chips while some modular designs for accelerating particular traffic patterns from applications and meliorating the communication overhead are able to be deployed as well.

A compact, high gain 8-element circular smart antenna is able to scan a beam azimuthally through 360°. The 8-element array is placed on a ground skirt and connected to an 8-channel beamforning board via a transfer plate. Each channel has two T/R switches, one band pass filer, one power amplifier, two low noise amplifiers, one phase shifter, and one attenuator. The 8-channel-signal is combined through power splitters/combiners and then sent to a connected radio. An FPGA chip controls the digital phase shifters, attenuators and switches for signal searching, beamforming and tracking. The smart antenna can be operated as a compact switched beam system or with an additional processor as an adaptive array system. The smart antenna is capable of tracking mobile targets, directionally communicating with desired users, suppressing interference and jamming, and enabling long range communications with high throughput and reliable connection because of its high antenna gain.

The invention discloses an FPGA (Field Programmable Gate Array)-based general matrix fixed-point multiplier. An internal structure of the multiplier consists of a control module, a conversion module, an operation module and a storage module. The control module is used for generating a control signal according to dimension of a to-be-operated matrix. The conversion module is responsible for performing conversion between a fixed-point number and a floating-point number during operation. The operation module is used for reading operation data from the storage module and the conversion module, performing fixed-point multiplication and fixed-point accumulating operation and storing a result in the storage module. The storage module is used for caching to-be-operated matrix data and result matrix data, providing an interface compatible with a bus signal and allowing access of other components on a bus. The characteristic of high fixed-point calculation efficiency in hardware is fully utilized; by using a unique operation structure, simultaneous conversion and operation of the data are realized to improve the overall operation speed, and a plurality of matrix fixed-point multipliers can be simultaneously used to perform parallel calculation; thus the fixed-point multiplication of an arbitrary dimension matrix can be supported, and meanwhile extremely high calculation efficiency is guaranteed. Compared with matrix multiplication performed by using the floating-point number, the multiplier has the advantage that the calculation efficiency is greatly improved.

The invention discloses an embedded type combined navigation system and a method thereof. The system comprises a sensor module, a data acquisition module, a data processing and calculating module and a peripheral communication interface module, wherein the sensor module comprises an optical fiber inertial navigation IMU and GNSS receiver; the data acquisition module is an FPGA module; the data processing and calculating module is a DSP chip; the sensor module and the data processing and calculating module are connected by a high-speed bus of the data acquisition module. The combined navigation method comprises the following steps: transmitting measurement data of the optical fiber inertial navigation IMU and GNSS receiver to a DSP for data processing and calculating by a bus of an FPGA; establishing an SINS/GNSS combined navigation system mathematical model for multi-level fault-tolerant combined navigation; judging according to the state of a sub system, carrying out navigation decision-making matching; and transmitting the obtained real-time speed, position and posture information to peripheral equipment by the peripheral communication interface module. The system has the advantages of high integration, abundant interfaces, high precision and good fault tolerance.

The invention discloses a field-programmable gate array (FPGA) configuration file update device. A microprocessor/microcontroller imports an FPGA configuration file from an external memory through a universal plug and play interface, and transmits the FPGA configuration file to an FPGA chip; the FPGA chip converts the FPGA configuration file into a data format capable of being identified by a nonvolatile memory, transmits the converted FPGA configuration file to the nonvolatile memory for storage, and updates the FPGA configuration file; and after a digital system is electrified again, the FPGA chip automatically reads the updated configuration file stored in the nonvolatile memory to realize automatic loading and normal operation. In the device, only when the FPGA configuration file needs to be updated, a new FPGA configuration file is written into the nonvolatile memory so as to realize the requirement of online configuration; and meanwhile, the microprocessor/microcontroller provides the interface for the external memory and reads the FPGA configuration file into the personal memory, and then the FPGA configuration file is written into the nonvolatile memory so as to realize the update of the FPGA configuration file and avoid the limitation of a special downloading line.

The invention discloses a convolutional-neural-network accelerating system based on a field-programmable gate array. The convolutional-neural-network accelerating system comprises a general processor,the field-programmable gate array, a storage module, a data bus and a control bus, wherein the general processor is a soft core of a reduced instruction set, and is responsible for starting an accelerator, being in communication with a host terminal, conducting time measurement and the like; a DDR3 DRAM serves as an external storage of the accelerator system; an AXI4-Lite bus is used for demand transmission, and an AXI4 bus is used for data transmission; the field-programmable gate array comprises multiple processing engines (PE), and each processing engine adopts a most-suitable fragment unfolding strategy to correspond to calculation of one layer in the convolutional neural network; all the processing engines are mapped onto a same FPGA chip, and therefore different layers can simultaneously work in a production line mode. Compared with an existing convolutional-neural-network accelerating system, the convolutional-neural-network accelerating system based on the field-programmable gate array can obtain higher energy efficiency benefit.

A field programmable gate array has security configuration features to prevent monitoring of the configuration data for the field programmable gate array. The configuration data is encrypted by a security circuit of the field programmable gate array using a security key. This encrypted configuration data is stored in an external nonvolatile memory. To configure the field programmable gate array, the encrypted configuration data is decrypted by the security circuit of the field programmable gate array using the security key stored in the artwork of the field programmable gate array. The secret key consists of a number of bits of key information that are embedded within the photomasks used in manufacture the FPGA chip.

The invention relates to a zinc oxide arrestor on-line monitoring system which comprises a microprocessor which is respectively connected with an A/D converting unit, a lightning stroke counting module and a GPRS communication module; the A/D converting unit is respectively connected with a leakage current sampling module and a voltage sampling module; the structure of the microprocessor comprises input/output interfaces, a counter and a serial communication interface; the input/output interfaces are connected with the A/D converting unit; the counter is connected with the lightning stroke counting module; the microprocessor is connected with the GPRS communication module; the microprocessor adopts a FPGA chip EPIC6Q240C8. The monitoring system dynamically monitors the insulating property of the zinc oxide arrestor under the operating voltage; the test results are accurate and reliable; the testing process is simple; and the test period is short; the zinc oxide arrestor on-line monitoring system is not easy to be affected by artificial and external factors, can provide long term data information of operation and performance deterioration of the zinc oxide arrestor, and has better practical value.

The invention belongs to the technical field of field programmable gate array (FPGA), and particularly relates to a circuit and a method having the function of resisting the single event upset (SEU) effect for an SRAM FPGA device. The SEU-resisting circuit comprises a read-back circuit, a fine-grained refresh circuit and a two-dimensional CRC calibration circuit. A bus state machine controls the read-back circuit to read information stored in a programming point in a read-back register in the read-back circuit, and then, the two-dimensional CRC calibration circuit calibrates the information and writes the address of the programming point generating the SEU effect in an SEU register; and an internal processor generates a fine-grained refreshing bit stream via the fine-grained refresh circuit based on the output of the SEU register, and the refreshing bit stream is written in an internal programming point of the FPGA chip via a self-configuration interface. The programming point generating the SEU error in the FPGA is refreshed again, thereby realizing the SEU-resistant function. Meanwhile, the invention also reduces the time and power consumption for reconstructing the FPGA after the SEU generation.

The invention discloses a reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc, under VPX control surface 1GEx1 signalization, a carrier board Soc controller can perform control command dynamic loading and logical function on-line reorganization on a high-performance reconfigurable FPGA (Field Programmable Gate Array), and board-level power and timer management and condition monitoring are completed; a reconfigurable FPGA chip is in interaction with front-end received signals through a standard FMC interface, and multi-function real-time digital signal processing is realized according to a loading program. Meanwhile, a dual-redundancy data bus interface is designed in a VPX connector, and a signal processing carrier board can be in data interaction with other board cards such as a master control switch card, an adjacent board card and the like in the system by a VPX dual redundancy data bus interface.

The invention discloses a system for detecting malicious circuits in an FPGA (field programmable gate array) chip by power consumption analysis. The system comprises a DC (direct current) stabilized voltage source for supplying DC power to a to-be-detected FPGA chip and an excitation applying FPGA chip; a current probe for measuring a transient current at the power end of the to-be-detected FPGA chip; an oscilloscope triggered by a trigger signal generated by the to-be-detected FPGA chip to collect the current signal measured by the current probe; the excitation applying FPGA chip for applying an excitation signal to the to-be-detected FPGA chip, and transmitting the response signal of the to-be-detected FPGA chip to a computer for further verification and comparison with an expected response value; and the computer for receiving excitation restraint compiled by a user, generating a test vector, and completing response verification, oscilloscope setting, waveform data collection, data analysis and treatment. The invention also discloses a method for detecting malicious circuits in the FPGA chip by using the above system.

The invention relates to field programmable gate array (FPGA)-based intersection queue length image detection and traffic signal control implementation, and belongs to signal processing technology, communication technology and traffic signal control technology. A digital image interested region is detected by using an FPGA chip on the basis of the conventional signal machine, and the queue length at a traffic intersection is extracted and a signal machine mainboard is communicated with an ARM7 processor so as to control a traffic signal lamp. The invention is characterized in that: an image processing algorithm circuit constructed by FPGA hardware logic analyzes and processes the acquired image signal, calculates the split green ratio according to the result and makes an image processing algorithm become hardware without a computer or a digital signal processor (DSP) and other core processors.

Systems and methods are provided for reducing power consumption of a multi-die device, such as a network processor FPGA (npFPGA). The multi-die device may include hardware resources such as FPGA dies, which may be coupled to NIC dies and/or memory dies. Power consumption of the multi-die device may be reduced by monitoring usage of hardware resources in the multi-die device, identifying hardware resources that are not in use, and gating power to the identified hardware resources. The status of processing elements (PEs) in the multi-die device may be tracked in a PE state table. Based on the PE state table, tasks from a task queue may be assigned to one or more processing elements.

Thorough mode of combining software with hardware in FPGA chip, the invention realizes protocol of virtual interface. The invention includes host interface, system on chip, Ethernet interface, and dedicated logic circuit for virtual interface. Through bus of system on chip, the system on chip is connected to Ethernet interface each other. Using communication mechanism sharing memory between host interface and system on chip realizes interlinkage and communication. Advantages are: reducing communication overhead of communication, obtaining more high transmission performance; using communication protocol in VIA lightweight level, the invention reduces data copy in communication process, shortens key path of storing data; Ethernet as transmission media is adopted at bottom layer so as to guarantee interlinkage and interoperability to current network; collaborative work between software and hardware speeds up procedure for processing protocol.

The invention discloses a method for implementing a dynamic partial reconfiguration embedded data controller chip. In the controller chip, an FPGA chip is used to implement the dynamic partial reconfiguration embedded data controller chip; the CoreConnect bus standard supporting IBM development is adopted; the CoreConnect technique can make a plurality of chip cores(IP core) mutually connected to form a new whole chip; the dynamic partial reconfiguration embedded data controller chip adopts the CoreConnect bus frame, and a PLB bus to be connected with a high-performance processor core, an internal memory controller and basic peripheral chip cores, and the reconfiguration parts are connected by an OPB bus; the reconfiguration parts can be the chip cores of the peripheral equipment as well as bottom layer arithmetic cores, and logic parts are kept unchanged; all device resources in the width occupied by a reconfiguration module belong to the reconfiguration module, and the border of the reconstructed module is determined and constant; and when communication is established between the modules, Bus Macro is used on the border.