Implementing method of dynamic local reconstructing embedded type data controller chip

Abstract

The invention discloses a method for implementing a dynamic partial reconfiguration embedded data controller chip. In the controller chip, an FPGA chip is used to implement the dynamic partial reconfiguration embedded data controller chip; the CoreConnect bus standard supporting IBM development is adopted; the CoreConnect technique can make a plurality of chip cores(IP core) mutually connected to form a new whole chip; the dynamic partial reconfiguration embedded data controller chip adopts the CoreConnect bus frame, and a PLB bus to be connected with a high-performance processor core, an internal memory controller and basic peripheral chip cores, and the reconfiguration parts are connected by an OPB bus; the reconfiguration parts can be the chip cores of the peripheral equipment as well as bottom layer arithmetic cores, and logic parts are kept unchanged; all device resources in the width occupied by a reconfiguration module belong to the reconfiguration module, and the border of the reconstructed module is determined and constant; and when communication is established between the modules, Bus Macro is used on the border.

Description

technical field [0001] The invention relates to an embedded system, in particular to an implementation method of a dynamic and partially reconfigurable embedded data controller chip, which is suitable for automatic control in industries such as electric power, transportation, and energy, and belongs to integrated circuit technology and computer technology. field. Background technique [0002] Traditional data controllers are generally implemented by general-purpose microprocessors or digital signal processor chips, whose hardware circuits are fixed, and the realized functional units cannot be changed on site. The use of programmable logic device FPGA to realize the data controller will form a field-programmable, reconfigurable "universal" new data controller. [0003] Reconfigurable system chip refers to setting one or more reconfigurable units in the chip, so that the end user can perform on-site hard programming or soft programming of part of the circuit structure of the ...

AI Technical Summary

Problems solved by technology

An FPGA programmed with a conventional SRAM can only be used to achieve static system reconfiguration. In the process of reconfiguring data, the old logic function is lost, the new logic function has not been established, and the circuit logic is broken on the time axis (which can be called system reconfiguration time slot], the system function cannot be dynamically continuous

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