218 results about "Logical part" patented technology

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

A system and method for parsing an electronic media database structure to produce tagged data that preserves the content, links, and electronic media structure. In particular, HyperText Markup Language (HTML) data is generated as an Interactive Electronic Technical Manual (IETM) (home page) linked into a relative structure of Web pages to support IETM deployment. An extraction process assesses the functionality associated with each node designated for presentation and builds a virtual Web, based on attributes stored in the IETM database. A series of Web pages with links that hierarchically presents IETM data at run time is produced. The method supports a data warehousing strategy that converts any data type eligible within the relational database. This expands support across multiple types of technical and engineering data. The preferred implementation utilizes a relative addressed pure HTML solution viewable in standard Web browsers. This open system implementation is cross platform and infrastructure independent, requiring no special server software. Retaining the hierarchical structure dictated by the relational database in HTML output enhances the supportability and maintainability of the Web implementation. Updates to this Web implementation can be incrementally applied within the hierarchy (small sections of data) or the entire logical sections of Web data.

A method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising predetermining at least one initial reading threshold; performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising said initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of said current logical page using said at least one row-specific reading threshold.

A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.

A method for analyzing and indexing an unstructured or semistructured document according to one embodiment includes receiving an unstructured or semistructured document; converting the document to one or more text streams; analyzing the one or more text streams for identifying textual contents of the document; analyzing the one or more text streams for identifying logical sections of the document; associating the textual contents with the logical sections; indexing the textual contents and their association with the logical sections; and saving a result of the indexing in a data storage device.

A method and system is provided for processing a program stream for interactive viewing, wherein the program stream includes programming content relating to a program having a plurality of program segments. The program stream is received and divided into at least one block comprising an expanse of the program stream. In accordance with an embodiment of the invention, a block is measured based upon the normal play time of the programming content, or some other predefined measurement. A determination is then made as to whether the block comprises at least one complete program segment. In accordance with an embodiment of the invention, a program segment is a logical portion of TV show or movie, such as a specific story of a news show, a scene in a movie, etc. Upon identifying one or more programming segments, these segment(s) may be made available for interactive viewing prior to receiving the end of the program. In another embodiment of the invention, a determination is made as to whether the block comprises an ending portion—but incomplete portion—of a program segment. In such instance, segment portions from multiple blocks may be accessed and appended to form a complete segment which may then be made available for interactive viewing. In yet another embodiment of the invention, content derived from blocks associated with a program segment may be combined with additional content relating to the program segment, even though the additional content is not within the plurality of blocks.

An n-bit digital image data is converted to (n+m)-bit data with a g-correction table, and displayed by the use of a (n+m)-bit D/A converter. A peripheral-driver logic section is driven with a low-voltage common power source and countermeasures to noise are taken. Data input to the D/A converter is not reversed and the power to the D/A converter is made alternating to apply an AC voltage to aligned crystal layer. A circuit is provided in order to compensate for a delay time in the driver. With this configuration, the image quality of a liquid crystal display apparatus in which the D/A converter is built is improved.

An interface detecting circuit and interface detecting method are provided, whereby operations can be carried out depending on peripheral devices connected to USB terminals, and whereby the system can be simplified and software load can be reduced. A pull-down resistor is connected to an ID terminal of a Mini-A receptacle of a peripheral device, the voltage generated by the pull-down resistor, which is pulled down by the ID terminal of the Mini-A receptacle of the peripheral device, and a pull-up resistor, which is pulled up by the ID terminal of a Mini-B receptacle of a device, is detected in an analog fashion, using a detecting section comprised of comparators, and, via a logic section, a logic output is subjected to noise cancellation in a filter section and is memorized in a register section. The operations of other devices are determined according to the states memorized in the register section.

A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.

An IC chip is provided with a wireless unit for inputting and outputting data by wireless communication, in addition to a logic section, so that the IC chip no longer needs I/O pads, leaving only power supply and ground pads. IC chips can input and output data with one another by wireless communications, which makes it possible to significantly improve the spacing relationships of various chips on a singular or even plurality of substrates.

A method for indexing a product identifier and logical parts thereof according to one embodiment of the present invention includes receiving a product identifier; splitting the product identifier into logical parts; indexing the product identifier and the individual logical parts in association with a particular document or portion thereof in an index; and storing the index. A method for processing a search query according to another embodiment of the present invention includes receiving a search query containing one or more terms; searching a search index containing complete product identifiers and variations thereof for attempting to match the one or more terms to the product identifiers or the variations thereof; and if one or more of the terms matches a complete product identifier or variation thereof, selecting and outputting an indicator of a document, or portion thereof, associated with the matching product identifier.

An electronic music stand system and methodologies relating thereto are presented. The electronic music stand system is comprised of a performer subsystem comprising a processing subsystem, librarian logic, performance logic, and communications management logic. The communications management logic provides management of communication via the communications interface with external apparatus responsive to the performance logic and the librarian logic. The user input apparatus and the display apparatus can be integrated into a touch-screen input display. The present invention also relates to a method for providing for video display of music responsive to the music data stored in a music database. The method is comprised of defining a page of music image data from the music database; defining ordered logical sections; storing the mapping in a memory for selective retrieval; and providing for the video display of the music responsive to the mapping and the storing.

A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The logic portions of the programmable logic device may be tri-stated.

A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The logic portions of the programmable logic device may be tri-stated.

A performance monitor is realized from programmable logic on the same integrated circuit as a processor. A user may use a programming and analysis tool to select a performance monitor soft core and to program it into the integrated circuit. The performance monitor is used to debug and/or monitor operation of the processor. After the debugging and/or performance monitoring, the portion of the programmable logic used to realize the performance monitor can be reconfigured and used to realize another portion of the user-specific circuit. Because the portion of the integrated circuit used to realize the performance monitor can be later used in the user-specific design, the cost of having to provide a no-longer-desired performance monitor in each integrated circuit used in the user's design is avoided. Because the performance monitor is realized from programmable logic, the performance monitor is more flexible than a conventional hardwired configurable performance monitor.

Inventive aspects include a key value store engine including non-volatile memory configured to store key-value inode descriptors each including a key and an associated value. The key value store engine can include a volatile memory to store a key hash tree and a collision hash tree. The key hash tree can include nodes each having a hash of one of the keys. The collision hash tree can include nodes each having a collided hash associated with two or more different keys. Each of the nodes of the key hash tree can include a collision flag indicating whether two or more different hashes correspond to a collided hash. The volatile memory can store a collision linked list including linked list nodes each having a key-value inode number indicating a location of a corresponding key-value inode descriptor stored in the non-volatile memory. The key value store engine can include a key value logic section.

In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.

A video recording camera system configured to record video to a non-volatile memory configured as a circular video recording buffer. In an embodiment, the video recording camera system includes a non-volatile storage medium and a processor is configured to manage at least a portion of the non-volatile storage medium as a circular buffer, replacing recorded video data stored in a subset of memory addresses corresponding to an older recorded video frame with the data corresponding to a newer video frame. In further embodiments, clip files may be partitioned from the circular buffer to prevent logical portion of the recorded video from being overwritten upon reaching a capacity of the circular recorded video buffer.

The invention discloses a method for implementing a dynamic partial reconfiguration embedded data controller chip. In the controller chip, an FPGA chip is used to implement the dynamic partial reconfiguration embedded data controller chip; the CoreConnect bus standard supporting IBM development is adopted; the CoreConnect technique can make a plurality of chip cores(IP core) mutually connected to form a new whole chip; the dynamic partial reconfiguration embedded data controller chip adopts the CoreConnect bus frame, and a PLB bus to be connected with a high-performance processor core, an internal memory controller and basic peripheral chip cores, and the reconfiguration parts are connected by an OPB bus; the reconfiguration parts can be the chip cores of the peripheral equipment as well as bottom layer arithmetic cores, and logic parts are kept unchanged; all device resources in the width occupied by a reconfiguration module belong to the reconfiguration module, and the border of the reconstructed module is determined and constant; and when communication is established between the modules, Bus Macro is used on the border.

This invention relates to technology field of cloud storage and especially relates to a cloud storage data access method. The method comprises: a step of data storing and a step of data retrieving. The data storing step comprises: converting a file to be stored into a group of data blocks to form a physical part of the file, saving a logical part of the file, which is formed by information of restoring the physical part back to original file; distributing the physical part to multiple cloud storage data centers for storage; and saving storing location information of the data blocks of the physical part in the cloud storage data centers in the logical part; the step of data retrieving comprises: acquiring the file's logical part according to a file access request; retrieving the physical part of the file from at least one of the cloud storage data centers according to the logical part information and restoring the physical part to the original file according to the logical part information. This invention also provides a cloud storage data access apparatus and system. This invention improves cloud storage data access performance, facilitates storage space saving, increases data transmission bandwidth, and strengthens data security.