77 results about "Soft core" patented technology

A cushion is provided, which relates to the technical field of home and outdoor patio leisure products, including a cover, a soft core, a power supply unit, a sounder, and a luminescent strip; the cover wraps around the soft core, the sounder is arranged in the soft core, and the luminescent strip is arranged inside the margin edge strip and / or a decorative edge of the side of the cover and powered by the power supply unit. The cushion has the function of helping soothing, relaxing, sleep and regulating the atmosphere, and has the characteristic of easy finding and positioning. The combination of the sounder and the luminescent strip not only enriches the functions of the cushion, but also improves the convenience of use.

The invention provides an SIMON encryption and decryption hardware acceleration system and method based on a Loongson soft core, and the system comprises a LoongArch processor soft core which is used for control, task scheduling and data interaction with external equipment; the SIMON encryption / decryption coprocessor module is used for executing an SIMON lightweight block encryption algorithm, completing key expansion and round function calculation and realizing encryption and decryption functions; the SRAM module is used for caching an original text, a ciphertext and intermediate data generated in the encryption and decryption process and supporting efficient data access; and the AXI bus interface module is used for high-speed data interaction between the SIMON encryption / decryption coprocessor module and the processor core and between the SIMON encryption / decryption coprocessor module and the SRAM module, and supports burst read-write operation. The method has high efficiency, flexibility and low power consumption, and can be widely applied to data encryption and transmission scenes of an embedded system and Internet of Things equipment.

The invention provides an asymmetric rigid-flex board and a processing method, and relates to a printed circuit board manufacturing technology, and the method comprises the steps: processing a core board of a flexible board; processing a hard core board; processing the PP layer; processing a gasket layer; the soft board core board, the PP layer, the gasket layer and the hard board core board are sequentially overlapped and pressed, and the soft-hard combined board is obtained through hot pressing; processing an outer-layer circuit of the soft board and an outer-layer circuit of the hard board; quickly pressing an outer layer covering film on the outer side surface of the soft board core board in the soft board area; spraying solder mask on the outer side surface of the soft core board in the hard board area and the outer side surface of the hard core board in the hard board area to form solder mask layers, and exposing and developing the solder mask layers to expose the positions of the bonding pads; and performing depth-controlled groove milling in a soft board area on the outer side of the hard board core board, and removing the gasket layer. According to the invention, the easy bending performance of the soft board area can be ensured, the welding resistance of the hard board area can be ensured, and the practicability is relatively high.

The invention provides a configuration data online upgrading method and system for an ANRIC818 digital video card, the system comprises an airborne task machine and the ANRIC818 digital video card, and the ANRIC818 digital video card comprises an FPGA (Field Programmable Gate Array), a DDR (Double Data Rate) and a FLASH. And the FPGA comprises an 818 interface IP core. The airborne task machine divides the configuration file into data blocks with preset sizes, and each data block is assembled to an FC-based 818 data frame and then is sent to the FPGA through an optical fiber cable; the FPGA receives 818 data frames through the 818 interface IP core, and ARINC818 optical fiber data communication between the airborne task machine and the FPGA of the ARINC818 video card is achieved; and the FPGA is configured with an embedded soft core module which is used for reading the received 818 data frame from the FPGA, extracting configuration file information from the 818 data frame, and then realizing read-write operation on the FLASH through an SPI (Serial Peripheral Interface) to finish an online upgrading function.

The invention provides an aerospace storage system with low cost and reliability. The system comprises an SRAM (Static Random Access Memory) FPGA (Field Programmable Gate Array) module and a FLASH FPGA module, the SRAM FPGA module comprises a CPU (Central Processing Unit) soft core, a logic copying module and an FPGA recording port; the FLASH FPGA module comprises a PROM (Programmable Read-Only Memory) read-write control module, a loading / read-back control module, a version read-back verification module, a fault judgment module and a refresh control module. According to the low-cost and reliable aerospace storage system, the situation that the system cannot be loaded due to the fact that the SRAM FPGA loads the ROM abnormally is avoided, once an error occurs in the running process of the system, the system can be restarted in time, and the position where the error occurs can be detected.

The invention discloses an intelligent heterogeneous radar hardware accelerator applied to rail transit, and belongs to the technical field of radar signal processing and integrated circuits. The accelerator is based on an SoC FPGA platform, a microprocessor soft core based on an RISC-V instruction set is constructed at an FPGA end, and an FFT calculation module and a CFAR calculation module are integrated to serve as hardware acceleration units. And the microprocessor soft core dynamically schedules each hardware acceleration unit by executing a program stored in the instruction memory, constructs a reconfigurable data path, and completes a radar signal processing flow. The method overcomes the defects of power consumption, communication bandwidth and flexibility of traditional DSP and FPGA schemes, and is particularly suitable for efficient and real-time detection and identification of roadbed structure damage in rail transit.

The utility model discloses a control system for an aviation device, and belongs to the technical field of aviation weapon control. The control system comprises a power supply control module, an SOC module, a configuration Flash, an EMMC memory, a crystal oscillator, a JTAG, a peripheral component and an external connector. An ARM processor and an FPGA are integrated in the SOC module, and a hard core processor is arranged in the ARM processor and used for executing software tasks. A soft core microprocessor and IP cores are arranged in the FPGA, the IP cores are connected with peripheral components correspondingly controlled by the IP cores one by one, and under the support of the IP cores and the peripheral components corresponding to the IP cores, transceiving control over the interfaces is achieved; the configuration Flash is used for storing a configuration file and serial loading software of the SOC module; the EMMC memory is used for storing software and data; the crystal oscillator is used for providing a clock required by the work of the SOC module; and the JTAG is used for downloading the configuration file of the SOC module to the configuration Flash. The control system provided by the utility model has strong electromagnetic compatibility, can be used in a complex electromagnetic environment, and improves the operation speed and the product reliability through the optimization of the SOC module.

The utility model provides a sound production pad, and belongs to the technical field of household and outdoor courtyard leisure articles. The sounding pad comprises an outer sleeve, a soft core and a sounder, the soft core is wrapped by the outer sleeve, the sounder is placed in the soft core, the sounder can give out white noise simulating the natural environment or specific sound facilitating relieving and sleeping, when a user leans against the cushion and closes the eyes to have a rest, the sense of reality that the user stays in the nature is achieved, and the cushion has the advantages of relieving the mind and body and helping sleeping.

A semiconductor structure includes a substrate, nanostructures, source / drain features, a gate structure, and inner spacers. The nanostructures are over the substrate and spaced apart from each other in a Z-direction. The source / drain features are electrically connected to and on opposite sides of the nanostructures in an X-direction. The gate structure extends in a Y-direction and wraps around the nanostructures. The inner spacers are between the nanostructures in the Z-direction. Each of the inner spacers includes a soft core layer and a hard liner layer wrapping around the soft core layer.

The application discloses a kind of support in-orbit program reconfiguration's satellite-borne solid-state memory, belong to electronic information field.Satellite-borne solid-state memory includes control core, data storage array, cache unit, refresh loading circuit, interface unit, program storage unit, control core realizes the control of storage array, parse host computer instruction, bad block management, wear leveling and address management, cache unit effectively prevents single event upset error.Storage array avoids the timing violation of FPGA that can appear under high main frequency and other difficult problems.Load refresh circuit uses refresh loading circuit to refresh FPGA internal program regularly, reduces the influence of single event upset.Interface unit realizes the control management of host computer to satellite-borne solid-state memory.Program storage unit selects storage carrier according to function, storage capacity size, read-write bandwidth requirement.The whole hardware design is with FPGA soft core to realize the control management function of satellite-borne solid-state memory, and special CPU hardware does not have to be designed.

The invention discloses a single event upset irradiation test method based on a modularized fifth-generation reduced instruction set soft core. The method is implemented on a ZYNQ chip. The method comprises the following steps: firstly, dividing a fifth-generation reduced instruction set soft core into a plurality of independent circuit modules according to functions, wherein the independent circuit modules comprise a decoder module, a jump processing module, an access control module, an arithmetic logic unit module, a data path module, a static memory module and a write-back circuit module; in the irradiation process, a program burnt by the ZYNQ chip outputs a running result data stream of each module to the upper computer in real time; the upper computer compares the received data with a pre-stored module expected correct value in real time; once data mismatch is found, an error event and a timestamp corresponding to the error event are immediately recorded, and circuit resources occupied by an error event occurrence bit are reversely positioned, so that module-level accurate positioning and vulnerability evaluation of errors caused by single event upset in the soft core are realized. The problem that the error source recognition rate is low when the whole soft core is tested is solved, and the fault resolution and the testing efficiency are remarkably improved.

The invention relates to the technical field of FPGA (Field Programmable Gate Array) simulation verification, in particular to an all-digital closed-loop simulation verification system based on a MicroBlaze soft core Bayer image processing FPGA, which comprises an image data generation module for processing an original image to obtain a test image data set; the simulated detector module is used for receiving configuration parameters configured by the FPGA and sending time sequence signal flow data obtained by converting the test image data set to the FPGA; the imitation storage chip module responds to a storage control signal of the FPGA, receives address data and write-in data and returns read-out data; the MicroBlaze soft core simulation module drives an FPGA (Field Programmable Gate Array) to process the time sequence signal flow data to obtain a simulation image; the image processing module processes the test image data set to generate first result data; the simulation data downloading module receives and processes the simulation image to obtain second result data; the result comparison module compares the second result data with the first result data. By means of the MicroBlaze soft core simulation module, a specific hardware platform does not need to be built, and the dynamic interaction function and the operation performance of the soft core and the FPGA are effectively verified.

The invention relates to a satellite-borne multi-carrier broadband dispersion transmitting link system and a digital pre-distortion compensation method. The system comprises a joint predistortion actuator unit, a JESD204 interface module, an RFSoC module, a multi-carrier transmitting channel, a first multiplexer, a second multiplexer, a high-speed data acquisition module, a soft core computing unit, a refreshing and reconstructing unit, a parameter read-write module and a power amplifier working point control and switch selection module. According to the invention, a joint pre-distortion actuator unit is adopted at a transmitting end to eliminate group delay distortion and imbalance influence in a satellite-borne transmitting link. Meanwhile, on the basis of compensating linear distortion, a GMP model is realized at a transmitting end based on a lookup table structure and is used for compensating the strong nonlinearity and memory characteristics of the power amplifier, and the modeling precision of the satellite power amplifier is improved. According to the invention, the vector amplitude error of the constellation diagram can be improved, the design reserved protection bandwidth between adjacent carriers of the last-stage duplexer can be reduced, and the frequency band utilization rate can be improved.

The present invention discloses a one-dimensional Gaussian fitting IP core based on FPGA and its implementation method. The present invention relates to the field of network communication technology. The one-dimensional Gaussian fitting IP core based on FPGA of the present invention includes: a communication interface, an input conversion module, a filling buffer module, a fitting parameter solving module, and an output conversion module; the communication interface includes an AXI-Stream interface and an AXI-Lite interface; this IP soft core can be directly used in an FPGA or an embedded system containing an FPGA to meet the application requirements of high-speed and miniaturized computing devices, and can be directly embedded in the design, eliminating the need for designers to develop and design for one-dimensional Gaussian fitting, reducing the development cost and shortening the cycle.

The present invention relates to a hollow turbine blade ceramic core and soft core support additive and subtractive composite processing platform, which belongs to the technical field of precision casting of hollow turbine blades for aircraft engines; it comprises a support column and a visual camera alignment module, a point laser detection module, an additive manufacturing module and a milling processing module. The support column is arranged on a workbench, and the ceramic core to be processed is mounted on the workbench through a fixture and a rotating spindle turntable; the visual camera alignment module, the point laser detection module, the additive manufacturing module and the milling processing module respectively provide four working processes: multi-station relative position calibration, ceramic core profile detection, soft core support blank preparation and soft core support milling forming, and the motion switching control of the four station modules is realized through the control of the upper computer; the present invention can realize the adaptive preparation of the soft core support on the ceramic core profile, improve the efficiency of the precise preparation of the soft core support, and reduce the influence of the dimensional accuracy caused by the clamping error.

This invention discloses a binary weighted convolutional neural network accelerator and a RISC-V system-on-a-chip. The binary weighted convolutional neural network accelerator includes an instruction parsing module, an address generation module, a finite state machine, a shift window module, a feature map storage module, a weight storage module, a multi-channel shared computing array, an accumulation module, and batch normalization and pooling modules. The RISC-V system-on-a-chip includes a FLASH module, a DDR module, an E203 RISC-V soft core module, an AXI Interconnect module, an AXI data transmission path, a cross-clock domain module, and the binary weighted convolutional neural network accelerator. This invention can significantly improve data reuse and storage retrieval efficiency, reduce resource consumption, and thus improve the overall operating efficiency of the accelerator.

The invention discloses a motor operation state monitoring method and device, a storage medium and electronic equipment, and an FPGA chip method comprises the steps: in the operation process of a motor, obtaining motor state information generated in real time in the operation process of the motor; for a pre-configured first fault identifier which can be directly observed and is high in timeliness, generating a monitoring result corresponding to the first fault identifier according to the motor state information; for a pre-configured second fault identifier which cannot be directly observed and is low in timeliness, sending motor state information to the FPGA soft core, and receiving a limit value which is calculated by the FPGA soft core in real time and is used for motor control; and based on the monitoring result or the limit value, a fault protection mechanism is triggered, and the monitoring result is sent to the micro-control unit. Therefore, by adopting the embodiment of the invention, the reliability and the safety of the motor driving system can be improved.

The present invention provides a test method and system for processor system-level design, comprising: a processor test platform based on SoC‑FPGA selects a memory and peripheral usage mode of a processor under test according to hardware source code and device conditions, detects the processor to be tested and performs interface standardization processing on it, and divides the interface of the processor to be tested according to function; the processor test platform deploys the processor to be tested in the form of a soft core in combination with the selected memory and peripheral usage mode, designs an address space mapping mechanism between a hard-core processor and the processor to be tested, constructs an FPGA project and generates a hardware configuration file; compiles the software source code and generates a software load for testing; the hard-core processor deploys the software load according to the selected memory and peripheral usage mode; provides the peripheral interface resources of the SoC‑FPGA to the processor to be tested in an exclusive or shared manner according to the memory and peripheral usage mode; and executes the software load to evaluate the complete hardware and software system.

1. Name of the product in this design: Soft Core Electronic Breast Mask (Key Temptation). 2. Purpose of this product design: To be applied to the chest for maintenance. 3. The key design features of this product are the combination of shape and pattern. 4. The image or photograph that best illustrates the design's key points: the front view. 5. This design is for a thin product, therefore the left view, right view, top view, and bottom view are omitted.

The invention provides a baseband resource management method, a baseband board, a main control board, a device and a storage medium. The method comprises the following steps: the baseband board sends soft core capability information of the baseband board to the main control board; receiving soft core configuration information sent by the main control board; wherein the soft core configuration information is generated by the main control board according to the soft core capability information of the baseband board and the soft core configuration requirement planned by the current cell; and executing soft core loading operation according to the soft core configuration information. By adopting the technical scheme of the invention, resource loading of soft core granularity is realized, unnecessary resource waste can be reduced, power consumption of a base station can be reduced, and applicability of a baseband board card to different application scenes can be improved.

The invention discloses an RISC-V soft core development method compatible with a Xilinx tool chain, and relates to the field of integrated circuit design and development, and the method comprises the steps: carrying out the preprocessing of an RISC-V soft core file in a Vivado development environment according to a Microblaze V soft core specification, obtaining a compatible soft core meeting an XSA standard, importing the compatible soft core into the Vivado development environment, and generating an XSA file in combination with a business demand, according to the method, firstly, a soft core BSP can be automatically generated for software development by utilizing a Vitis development environment, the traditional BSP and SDK development can be skipped, an application software construction link is directly entered, and the method deeply excavates and strengthens the compatibility with a Sailing platform, so that the deployment of the soft core design based on the RISC-V architecture on a Sailing FPGA is smoother, and the development efficiency is improved. The development efficiency and the product quality are obviously improved.

The application provides a multi-dimensional layered hardware Trojan evaluation method for an IP soft core, constructs a Trojan multi-dimensional feature library, performs function integrity analysis to identify a first module in which a Trojan may exist, obtains equivalent RTL level code for a module in which no anomaly is found, takes each module of the RTL level code as a node and takes the calling relationship between each module as a weight to establish an information flow graph, compares the information flow graph with the Trojan multi-dimensional feature library to obtain a second module in which a Trojan may exist, analyzes the information flow graph, and takes a module in which the calling is less than a set threshold, a module with an isolated node and a module adjacent to the isolated node in the information flow graph as a third module in which a Trojan may exist, analyzes the first module, the second module and the third module, calculates code coverage, signal flip rate, signal and clock delay anomaly, power consumption anomaly and layout blocking anomaly, and comprehensively evaluates to locate a module in which a Trojan exists in the to-be-detected IP soft core.

The present invention discloses an ADC dynamic index measurement system and method based on FPGA, which is used to solve the problems of frequent manual intervention and slow test speed in traditional methods. The system only needs simple operation during measurement to realize the measurement and display of ADC dynamic index, which can effectively shorten the measurement time. The measurement system includes a host computer, a software module and a hardware logic module. The host computer is used to measure the distribution of system control parameters and the dynamic observation of parameter indicators; the software module is implemented based on Microblaze soft core or ARM hard core, including an ADC chip configuration module and an ADC index calculation module; the hardware logic module is implemented using the logic resources of FPGA, including a clock distribution module, an IO transmission module, a data buffer conversion module, a self-test signal generation module, a data preprocessing module and a RAM storage control module.

The invention discloses a preparation process method of a soft chaplet of a ceramic core, and belongs to the field of additive manufacturing. The method comprises the steps of soft chaplet modeling and thickness definition; curved surface layering and path planning are carried out, layered slicing is carried out on the theoretical three-dimensional model of the soft core support, and a mixed layering method based on Boolean operation and a spiral slicing algorithm is adopted for layered slicing; according to a slicing result, a Zigzag path is adopted for filling, and an initial printing path of the soft core support is generated; technological parameters are optimized; and conformal printing. According to the method, the precise geometric processing capacity of Boolean operation and the continuous path generation concept of spiral slicing are combined, a mixed layering strategy is formed, and on the premise that the printing precision is guaranteed, the printing paths can be connected to the maximum extent, the idle stroke is reduced, and efficient and continuous printing is achieved.

This application discloses a digital predistortion (DPD) implementation method, system, device, and storage medium, relating to the field of radio frequency communication technology. The method includes: when the soft core receives a calibration start command, it first sends a sinusoidal calibration signal to the FPGA platform, triggering its initial calibration of the transmission link; after receiving a calibration confirmation signal from the FPGA, the soft core reads the pre-stored initial training modulation signal from its internal memory and sends it to the FPGA platform as transmission data; subsequently, it reads the feedback data after nonlinear distortion by the power amplifier from the FPGA via a high-speed bus; based on this feedback data and the initial training signal, the soft core iteratively updates the digital predistortion compensation parameters and updates the transmission data; the FPGA performs stable compensation on the power amplifier (PA) based on the updated transmission data. This method, through the collaboration of the FPGA and the soft core, tightly couples calibration, acquisition, caching, and updating, utilizes on-chip high-speed storage to avoid external memory access, and combines pipelined processing to significantly improve DPD accuracy, iteration efficiency, and resource utilization.

The valve element timer capable of being remotely controlled is additionally provided with a capacitor C5 of 220 mu, a resistor R11 of 3k and an LED, and the working state of an indicating circuit is convenient to debug. A valve soft core socket (21t2) and a valve soft core clack (21t3) are arranged on the modified valve soft core (21a); the valve soft core inserting opening (21t2) is arranged in a concave wave trough of a disc with the section defined by a cosine function curve, and the valve soft core inserting opening (21t2) is a multi-petal multi-waveform pilot valve hole; the valve soft core clack (21t3) is provided with four bosses and four fan-shaped petal grooves on a high wave crest at the disc center position of a disc of which the section is enclosed by a cosine function curve; the device changes according to different specifications and models.

The present application relates to the technical field of image compression, and particularly relates to a frame frequency switching image compression method and device, a computing device and a storage medium. The method comprises the following steps: obtaining a control instruction of frame frequency switching after compressing an image of a first frame frequency; the control instruction contains a frame frequency number of a second frame frequency to be switched; determining an execution order of receiving a target image and reconfiguring a compression soft core according to the frame frequency number of the second frame frequency and the first frame frequency; the target image is image data sent in real time by external video generation software after the first frame frequency is switched to the second frame frequency; and performing image compression on the target image by using the reconfigured compression soft core based on the execution order. The present application can ensure that the target image is received after the compression soft core is reconfigured, and the image data directly sent into the soft core can be compressed immediately, thereby effectively solving the compression frame loss problem caused by time sequence mismatch during frame frequency switching.

The application relates to the technical field of power quality monitoring, in particular to a power quality measurement system based on a RISC-V architecture, which comprises a RISC-V processor soft core, a bus module, a signal acquisition module, a DSP computing power processing module and a result output module; the signal acquisition module, the DSP computing power processing module and the result output module are sequentially connected in communication to form a data flow channel, the data flow channel is used for collecting and processing original power signals to output power quality measurement results; the RISC-V processor soft core establishes control channels with the signal acquisition module, the DSP computing power processing module and the result output module through the bus module; the DSP computing power processing module is configured with a special interaction unit, the RISC-V processor soft core directly accesses the DSP computing power processing module through the special interaction unit and stores power quality measurement results. The application realizes reasonable separation and deep cooperation of control flow and data flow in the system, and improves the overall response speed, measurement accuracy and resource utilization efficiency of the system.

The invention discloses an inverter data acquisition method and system and a computer readable storage medium, relates to the field of data acquisition, and is applied to a data acquisition unit which integrates a Linux communication protocol conversion application program and an RSIC-V soft core in advance, and the RSIC-V soft core runs a target executable program generated after cross compiling of a source program in a physical ARM chip. According to the scheme, the source program of the ARM chip is compiled into the target executable program only in a cross compiling mode, and all functions of the physical ARM chip can be completed by running the target executable program through the RSIC-V soft core; according to the invention, the inverter data transmitted by the DSP chip is collected, the inverter data is converted into the RSIC-V format data, the RSIC-V format data is stored, the RSIC-V format data is converted into the modbus format data, and the modbus format data is transmitted, so that the cost is greatly saved, the time is greatly saved, and the manpower demand is greatly reduced.

The invention relates to the technical field of encryption, and provides a dynamic encryption system and method based on an RISC-V. The system comprises a feature generation module used for generating a feature set; a configurable RISC-V processor soft core, a dynamic key generation module and a data encryption operation module are integrated in the SoC, and the data encryption operation module is connected with the dynamic key generation module and the processor soft core through a system bus. The feature generation module and the data encryption operation module establish direct data connection with the processor soft core through a symbiotic register architecture; the dynamic key generation module is used for generating a dynamic chaotic sequence based on the feature set; and the data encryption operation module is used for acquiring to-be-encrypted plaintext data, performing encryption operation on the to-be-encrypted plaintext data based on the dynamic chaotic sequence and outputting an encryption operation result. The method is based on the RISC-V architecture, the calculation overhead and efficiency are reduced, the data access and encryption speed is increased, and the method can adapt to the real-time requirement of diversified scenes.