22 results about "Soft core" patented technology

The invention discloses an intelligent heterogeneous radar hardware accelerator applied to rail transit, and belongs to the technical field of radar signal processing and integrated circuits. The accelerator is based on an SoC FPGA platform, a microprocessor soft core based on an RISC-V instruction set is constructed at an FPGA end, and an FFT calculation module and a CFAR calculation module are integrated to serve as hardware acceleration units. And the microprocessor soft core dynamically schedules each hardware acceleration unit by executing a program stored in the instruction memory, constructs a reconfigurable data path, and completes a radar signal processing flow. The method overcomes the defects of power consumption, communication bandwidth and flexibility of traditional DSP and FPGA schemes, and is particularly suitable for efficient and real-time detection and identification of roadbed structure damage in rail transit.

The application discloses a kind of support in-orbit program reconfiguration's satellite-borne solid-state memory, belong to electronic information field.Satellite-borne solid-state memory includes control core, data storage array, cache unit, refresh loading circuit, interface unit, program storage unit, control core realizes the control of storage array, parse host computer instruction, bad block management, wear leveling and address management, cache unit effectively prevents single event upset error.Storage array avoids the timing violation of FPGA that can appear under high main frequency and other difficult problems.Load refresh circuit uses refresh loading circuit to refresh FPGA internal program regularly, reduces the influence of single event upset.Interface unit realizes the control management of host computer to satellite-borne solid-state memory.Program storage unit selects storage carrier according to function, storage capacity size, read-write bandwidth requirement.The whole hardware design is with FPGA soft core to realize the control management function of satellite-borne solid-state memory, and special CPU hardware does not have to be designed.

The invention discloses a single event upset irradiation test method based on a modularized fifth-generation reduced instruction set soft core. The method is implemented on a ZYNQ chip. The method comprises the following steps: firstly, dividing a fifth-generation reduced instruction set soft core into a plurality of independent circuit modules according to functions, wherein the independent circuit modules comprise a decoder module, a jump processing module, an access control module, an arithmetic logic unit module, a data path module, a static memory module and a write-back circuit module; in the irradiation process, a program burnt by the ZYNQ chip outputs a running result data stream of each module to the upper computer in real time; the upper computer compares the received data with a pre-stored module expected correct value in real time; once data mismatch is found, an error event and a timestamp corresponding to the error event are immediately recorded, and circuit resources occupied by an error event occurrence bit are reversely positioned, so that module-level accurate positioning and vulnerability evaluation of errors caused by single event upset in the soft core are realized. The problem that the error source recognition rate is low when the whole soft core is tested is solved, and the fault resolution and the testing efficiency are remarkably improved.

The invention relates to a satellite-borne multi-carrier broadband dispersion transmitting link system and a digital pre-distortion compensation method. The system comprises a joint predistortion actuator unit, a JESD204 interface module, an RFSoC module, a multi-carrier transmitting channel, a first multiplexer, a second multiplexer, a high-speed data acquisition module, a soft core computing unit, a refreshing and reconstructing unit, a parameter read-write module and a power amplifier working point control and switch selection module. According to the invention, a joint pre-distortion actuator unit is adopted at a transmitting end to eliminate group delay distortion and imbalance influence in a satellite-borne transmitting link. Meanwhile, on the basis of compensating linear distortion, a GMP model is realized at a transmitting end based on a lookup table structure and is used for compensating the strong nonlinearity and memory characteristics of the power amplifier, and the modeling precision of the satellite power amplifier is improved. According to the invention, the vector amplitude error of the constellation diagram can be improved, the design reserved protection bandwidth between adjacent carriers of the last-stage duplexer can be reduced, and the frequency band utilization rate can be improved.

This invention discloses a binary weighted convolutional neural network accelerator and a RISC-V system-on-a-chip. The binary weighted convolutional neural network accelerator includes an instruction parsing module, an address generation module, a finite state machine, a shift window module, a feature map storage module, a weight storage module, a multi-channel shared computing array, an accumulation module, and batch normalization and pooling modules. The RISC-V system-on-a-chip includes a FLASH module, a DDR module, an E203 RISC-V soft core module, an AXI Interconnect module, an AXI data transmission path, a cross-clock domain module, and the binary weighted convolutional neural network accelerator. This invention can significantly improve data reuse and storage retrieval efficiency, reduce resource consumption, and thus improve the overall operating efficiency of the accelerator.

The invention provides a baseband resource management method, a baseband board, a main control board, a device and a storage medium. The method comprises the following steps: the baseband board sends soft core capability information of the baseband board to the main control board; receiving soft core configuration information sent by the main control board; wherein the soft core configuration information is generated by the main control board according to the soft core capability information of the baseband board and the soft core configuration requirement planned by the current cell; and executing soft core loading operation according to the soft core configuration information. By adopting the technical scheme of the invention, resource loading of soft core granularity is realized, unnecessary resource waste can be reduced, power consumption of a base station can be reduced, and applicability of a baseband board card to different application scenes can be improved.

The application provides a multi-dimensional layered hardware Trojan evaluation method for an IP soft core, constructs a Trojan multi-dimensional feature library, performs function integrity analysis to identify a first module in which a Trojan may exist, obtains equivalent RTL level code for a module in which no anomaly is found, takes each module of the RTL level code as a node and takes the calling relationship between each module as a weight to establish an information flow graph, compares the information flow graph with the Trojan multi-dimensional feature library to obtain a second module in which a Trojan may exist, analyzes the information flow graph, and takes a module in which the calling is less than a set threshold, a module with an isolated node and a module adjacent to the isolated node in the information flow graph as a third module in which a Trojan may exist, analyzes the first module, the second module and the third module, calculates code coverage, signal flip rate, signal and clock delay anomaly, power consumption anomaly and layout blocking anomaly, and comprehensively evaluates to locate a module in which a Trojan exists in the to-be-detected IP soft core.

This application discloses a digital predistortion (DPD) implementation method, system, device, and storage medium, relating to the field of radio frequency communication technology. The method includes: when the soft core receives a calibration start command, it first sends a sinusoidal calibration signal to the FPGA platform, triggering its initial calibration of the transmission link; after receiving a calibration confirmation signal from the FPGA, the soft core reads the pre-stored initial training modulation signal from its internal memory and sends it to the FPGA platform as transmission data; subsequently, it reads the feedback data after nonlinear distortion by the power amplifier from the FPGA via a high-speed bus; based on this feedback data and the initial training signal, the soft core iteratively updates the digital predistortion compensation parameters and updates the transmission data; the FPGA performs stable compensation on the power amplifier (PA) based on the updated transmission data. This method, through the collaboration of the FPGA and the soft core, tightly couples calibration, acquisition, caching, and updating, utilizes on-chip high-speed storage to avoid external memory access, and combines pipelined processing to significantly improve DPD accuracy, iteration efficiency, and resource utilization.

The present application relates to the technical field of image compression, and particularly relates to a frame frequency switching image compression method and device, a computing device and a storage medium. The method comprises the following steps: obtaining a control instruction of frame frequency switching after compressing an image of a first frame frequency; the control instruction contains a frame frequency number of a second frame frequency to be switched; determining an execution order of receiving a target image and reconfiguring a compression soft core according to the frame frequency number of the second frame frequency and the first frame frequency; the target image is image data sent in real time by external video generation software after the first frame frequency is switched to the second frame frequency; and performing image compression on the target image by using the reconfigured compression soft core based on the execution order. The present application can ensure that the target image is received after the compression soft core is reconfigured, and the image data directly sent into the soft core can be compressed immediately, thereby effectively solving the compression frame loss problem caused by time sequence mismatch during frame frequency switching.

The application relates to the technical field of power quality monitoring, in particular to a power quality measurement system based on a RISC-V architecture, which comprises a RISC-V processor soft core, a bus module, a signal acquisition module, a DSP computing power processing module and a result output module; the signal acquisition module, the DSP computing power processing module and the result output module are sequentially connected in communication to form a data flow channel, the data flow channel is used for collecting and processing original power signals to output power quality measurement results; the RISC-V processor soft core establishes control channels with the signal acquisition module, the DSP computing power processing module and the result output module through the bus module; the DSP computing power processing module is configured with a special interaction unit, the RISC-V processor soft core directly accesses the DSP computing power processing module through the special interaction unit and stores power quality measurement results. The application realizes reasonable separation and deep cooperation of control flow and data flow in the system, and improves the overall response speed, measurement accuracy and resource utilization efficiency of the system.

The invention relates to the technical field of encryption, and provides a dynamic encryption system and method based on an RISC-V. The system comprises a feature generation module used for generating a feature set; a configurable RISC-V processor soft core, a dynamic key generation module and a data encryption operation module are integrated in the SoC, and the data encryption operation module is connected with the dynamic key generation module and the processor soft core through a system bus. The feature generation module and the data encryption operation module establish direct data connection with the processor soft core through a symbiotic register architecture; the dynamic key generation module is used for generating a dynamic chaotic sequence based on the feature set; and the data encryption operation module is used for acquiring to-be-encrypted plaintext data, performing encryption operation on the to-be-encrypted plaintext data based on the dynamic chaotic sequence and outputting an encryption operation result. The method is based on the RISC-V architecture, the calculation overhead and efficiency are reduced, the data access and encryption speed is increased, and the method can adapt to the real-time requirement of diversified scenes.

A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and / or external hard logic.

The application provides a file management method based on a soft core on-board high-speed solid storage, which comprises the following steps: dividing a solid storage logical space into a metadata fixed block area and a data block area, dividing the data block area according to a fixed block size and managing the data block area according to a block number; establishing a super block, a directory table, a file table, a free block linked list and a file block number sequence of each file in a memory; serializing the above structure to generate a metadata mirror, writing the metadata mirror into the metadata fixed block area and saving multiple redundant copies; when power is restored, reading the multiple copies to make a consistency judgment, selecting an effective mirror to analyze and rebuilding a memory index structure. Through integrated storage of metadata and data, the application avoids the life and reliability risks caused by storing metadata in an independent and vulnerable medium in a traditional scheme; a multiple-copy redundancy and consistency judgment mechanism is adopted to realize quick recovery after power failure; through a rebuilding mechanism of the memory index, the consistency of a file system state and physical data is ensured, and the reliability of an on-board storage system is improved.

The invention discloses a multi-path DP light conversion signal video switching board card, and relates to the technical field of video signal conversion and transmission. The board card comprises an FPGA chip, a plurality of DP input interfaces and a plurality of optical signal output interfaces. The FPGA chip is provided with a soft core controller and a hardware IP module composed of a DP receiving module, a VDMA module, a VTC module, an HBM module, a video output module and a GT transceiver module. And the soft core controller is connected with each IP module through an AXI bus and is used for coordinating and controlling decoding of multiple paths of DP signals, video stream processing and optical signal conversion. Through cooperative work of the high-performance FPGA integrated with the HBM memory and the modular IP core, high-density signal conversion of as many as 15 paths of DP input and 20 paths of optical signal output is achieved, it is supported that multiple paths of optical signals are combined into one path of output with the highest 40 Gbps, and the technical bottlenecks of an existing single-path switching board card in expansibility, processing capacity and power consumption are solved.

The utility model belongs to the technical field of coiling machine, especially a soft core coiling machine, including coiling machine control box, the top fixedly connected with the connecting top board of coiling machine control box, the top fixedly connected with the protective housing of connecting top board, the inside rotatory connection of protective housing has the rotary seat, the fixedly connected with a plurality of mounting plates of rotary seat, and a plurality of the fixedly connected with connecting rod between the end of mounting plate, and the connecting rod rotatory connection in the top of connecting top board, the top fixedly connected with the sliding seat of mounting plate, and the sliding connection with the connecting seat on sliding seat, the top fixedly connected with first support rod of connecting seat, when completing to the coiling of article, make between support arc plate and article can be more convenient to separate, reduce in the coiling between hose or the object of coiling and carry out, because of the influence of coiling tension, lead to the inconvenient problem of hose when taking.

This invention discloses a damping polymer fluid gel intelligent cushioning packaging and item drop monitoring system, comprising a shell, a damping sensor, a signal acquisition and processing module, and an intelligent receiving terminal. The damping sensor, a polymer fluid gel with a core-shell structure, is attached to the inner wall of the shell. When subjected to impact, the sensor achieves cushioning protection through the coordinated energy dissipation of the hard shell through plastic deformation and the viscoelastic flow of the soft core, while simultaneously sensing the impact event by generating a resistance change in response to compression deformation. The signal acquisition and processing module, fixed to the outer wall of the shell, acquires the resistance change signal and identifies the impact event, then wirelessly transmits it to the intelligent receiving terminal for real-time display and alarm. This invention features a simple manufacturing process and structure, controllable cost, and combines efficient cushioning protection with visual monitoring of drop conditions, providing an innovative solution for the safety monitoring of items during logistics transportation, and possesses good practical value and promising prospects for widespread application.

A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and / or external hard logic.

The invention provides an FPGA multi-soft-core serial port communication online upgrading system for a display screen, and belongs to the technical field of hardware development, the system comprises an upper computer, the display screen and an FPGA board card, the FPGA board card comprises a plurality of soft cores and Brams used for processing data communication and online upgrading of an FPGA, and the number of the soft cores is larger than or equal to 3. When a large amount of data needs to be processed or a new function needs to be added to the FPGA, a new soft core can be continuously added. The multiple soft cores can process independent tasks at the same time, reusability and portability of an upgrade module are facilitated, the throughput of data of the whole system is improved, and the problem that a single soft core is poor in load capacity is solved.

The invention discloses a key equipment health management microsystem and a control method thereof. The microsystem comprises a health management SIP chip and a peripheral circuit module electrically connected with the health management SIP chip. An AD acquisition unit, an interface unit, a soft core unit, a processor unit and a storage unit are integrated in the health management SIP chip; the peripheral circuit module comprises a power supply module, a communication module, an Ethernet communication module and a health sound alarm module. The control method comprises the steps of micro-system deployment, operation mode determination, data acquisition and processing, health operation (fault diagnosis, life prediction and maintenance decision) and communication, solves the problems of poor universality, insufficient timeliness and the like of an existing scheme, and realizes efficient health management of key equipment.

This application discloses a method, apparatus, device, and medium for online backplane upgrades, relating to the field of computer technology. The method includes: receiving an online upgrade command and filtering out the target backplane soft core address corresponding to the online upgrade command; determining the target soft core channel and target hard core channel corresponding to the target backplane soft core address from soft core channels and hard core channels connected to the motherboard; closing the target soft core channel and opening the target hard core channel to upgrade the target backplane corresponding to the online upgrade command through the target hard core channel, obtaining an upgraded backplane; and closing the target hard core channel and opening the target soft core channel. When multiple identical backplanes exist in the same group of I2C BUS, the above solution, utilizing the target backplane soft core address and switching between soft core channels and hard core channels, enables low-cost and low-complexity backplane upgrades.

This invention discloses a real-time processing and scheduling method for infrared thermal imaging based on an FPGA-SoC architecture, specifically relating to the field of thermal imaging system technology. The method acquires raw image frames output by an infrared detector, calculates intra-frame features in real time using an image complexity evaluation algorithm, and dynamically determines the set of image processing algorithms and their priorities based on a complexity and scheduling strategy table. Corresponding processing units are invoked from the FPGA logic resource pool, and the algorithms are executed in parallel or pipelined manner to generate intermediate image data. Image data is transmitted to the SoC shared memory via the AXI4-FULL interface, while control information is written via the AXI4-Lite interface. The RISCV soft core monitors the control register, triggers image output, and refreshes the parameters for the next frame. This method possesses high real-time performance, adaptive scheduling, and hardware-software collaborative control capabilities, making it suitable for infrared thermal imaging applications in complex environments.