Automatic test platform of high-speed ADC chip and software framework design method thereof

Abstract

The invention discloses an automatic test platform of a high-speed ADC chip and a software framework design method thereof. The design method comprises the steps of step 1, FPGA underlying logic drive design: the FPGA underlying logic part completes construction of the hardware foundation, including realizing underlying logic control, foundation computation and soft core hardware configuration of the hardware module; and synchronous drive algorithm design including the tested high-speed ADC, calibration algorithm design, hardware drive design of the onboard high-precision ADC / DAC and register array and hardware FFT operation; step 2, test parameter acquisition: the FPGA soft core receives an upper computer command to control the test process and transmits the command to the FPGA hardware program to drive an external circuit to acquire data so as to obtain the test parameter value by applying the processing algorithm, wherein the test parameters are mainly divided into static parameters and dynamic parameters; and step 3, upper computer program design. The high-precision level characteristic and the high-speed data characteristic of the chip can be simultaneously measured, and "one-key acquisition" can be realized through programming control.

Description

technical field [0001] The invention belongs to the technical field of testing integrated circuit chips, and in particular relates to an automatic testing platform applied to high-speed analog-to-digital converter chips and a software structure design method thereof. Background technique [0002] High-speed ADC chips (analog-to-digital converters) are widely used in the fields of radar, optical communication, software radio and mobile communication. With the continuous improvement of the conversion rate and sampling accuracy of ADC chips, the test tasks of a large number of chips after mass production are heavy and very important, and higher requirements are placed on the existing test system; the test tasks include testing various types of ADC chips. Characteristic parameters: static characteristics, dynamic characteristics, data\clock output characteristics and power consumption characteristics, etc. [0003] At present, mass production testing of chips in the field of ch...

AI Technical Summary

Problems solved by technology

It can achieve a certain degree of rapid and automated testing of a large number of chips, but the testing scheme based on this equipment has many limitations, especially for high-speed ADC chips. The test accuracy of the static characteristics and dynamic characteristic parameters of the chip under test needs to provide adjustable frequency amplitude or high-precision analog input signal; for the data of the data output interface of the high-speed ADC chip under test, the processing core needs to provide adjustable Delayed delay IO module, and provide calibrated synchronous algorithm driver for high-speed ADC; high-speed computing core is required to ensure the fast operation of parameter processing algorithm; and corresponding upper computer control module is required to control the process or test equipment and display and store the results ; While completing the above functions, it is also necessary to ensure that the entire testing process takes a short time and is fully automatic

Images