762 results about "Synchronous dynamic random-access memory" patented technology

A circuit and method of operation for combining commands in a DRAM (dynamic random access memory) are revealed. The method applies to DRAMs having a plurality of memory banks or arrays. The method combines commands to rows on different memory banks, and the method also combines row and column commands on different memory banks. The method eliminates steps in a sequence of commands, and may significantly increase speed of input/output to a DRAM.

An apparatus for and method of enhancing the performance of a multi-port internal cached DRAM (AMPIC DRAM) by providing an internal method of data validation within the AMPIC memories themselves to guarantee that only valid requested data is returned from them, or properly marked invalid data. A modified technique for identifying bad data that has been read out of AMPIC memory devices in the system.

A system and method are provided for using dynamic random access memory and flash memory. In one example, the memory system comprises a nonvolatile memory; synchronous dynamic random access memories; circuits including a control circuit which is coupled with the nonvolatile memory and the synchronous dynamic random access memories, and controls accesses to the nonvolatile memory and the synchronous dynamic random access memories; and a plurality of input/output terminals coupled with the circuits, wherein in data transfer from the nonvolatile memory to the synchronous dynamic random access memories, error corrected data is transferred.

A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has external interconnects arranged in a manner that corresponds to interconnects of a synchronous dynamic random access memory device. The synchronous flash memory device, however, comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory. In one embodiment, the synchronous non-volatile memory device has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal, and a chip select connection (CS#) to receive a chip select signal.

A memory controller capable of estimating memory power consumption includes a memory control unit, a command dispatch device, plural bank state machines and a power-state and current-accumulation device. The memory control unit generates control signals based on a memory access command sent by a system for accessing a synchronous dynamic random access memory (SDRAM). The command dispatch device synchronously receives the control signals sent by the controller to the SDRAM. The plural bank state machines are connected to the command dispatch device to receive the control signals dispatched by the command dispatch device and accordingly determine whether to transfer its internal state or not. The power-state and current-accumulation device determines on which state the SDRAM is in accordance with states of the plural band state machines, thereby computing current consumption of the SDRAM.

A system and computer system for improving data integrity and memory performance using non-volatile media. A system includes a non-volatile mass storage unit, e.g., a flash memory device and/or a hard drive unit for instance. A memory device is used as a high speed data buffer and/or cache for the non-volatile storage unit. The memory device may be non-volatile, e.g., magnetic random access memory (MRAM) or volatile memory, e.g., synchronous dynamic random access memory (SDRAM). By buffering and/or caching the write data, fewer accesses are required to the mass storage device thereby increasing system performance. Additionally, mechanical and electrical degradation of the mass storage device is reduced. Certain trigger events can be programmed to cause data from the memory device to be written to the mass storage device. In one embodiment, the write buffer contents are preserved across reset or power loss events. In one embodiment, the mass storage unit may be a data transport layer, e.g., Ethernet, USB, Bluetooth, etc.

A programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface is provided. A programmable compensated delay apparatus includes a reference delay calibration circuit for providing a measured number of delay elements in one cycle. A programmable delay register provides a desired delay value. A conversion logic is coupled to the reference delay calibration circuit and the programmable delay register for receiving both the measured number of delay elements in one cycle and the desired delay value. The conversion logic provides a number of required delay elements. A delay circuit is coupled to the conversion logic for receiving the number of required delay elements and providing the desired delay. A SDRAM control logic provides a refresh start signal to the reference delay calibration circuit for updating the delay circuit during each DRAM refresh. The DQS clock strobe on the DDR SDRAM is applied to the delay circuit and is delayed by the desired delay.

A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.

The invention relates to a phased array radar antenna beam control device. The phased array radar antenna beam control device comprises a remote control PC (Personal Computer) computer, a user control computer module, a power supply management module, a FPGA (Field Programmable Gate Array) chip, a signal driver, a wave control conversion circuit and a controlled device which is electrically connected with the wave control conversion circuit, wherein the user control computer module remotely communicates with the remote control PC computer and are electrically connected with the FPGA chip, thepower supply management module and the wave control conversion circuit, respectively. The FPGA chip is embedded with a PowerPC hardcore and used for constructing an embedded computer; the embedded computer also comprises an Ethernet (Media Access Control), a UART (Universal Asynchronous Receiver Transmitter) controller, a DDR2SDRAM (Double Data Rate 2 Synchronous Dynamic Random Access Memory) memory module, a FLASH controller module, a parallel controller, a FPGA configuration circuit module and a clock generating circuit module. The phased array radar antenna beam control device provided by the invention has the advantage of high reliability.

A synchronous dynamic random access memory (“SDRAM”) device includes several banks of memory cell coupled to a read data path and a write data path. The read data path includes a read latch that stores a relatively large number of read data bits received in parallel from a bank of memory cells. Groups of the stored read data bits are sequentially selected by a multiplexer and applied to a read data bus. Groups of write data bits are sequentially coupled to the SDRAM device through a write data bus that is separate from the read data bus, and they are sequentially stored in input registers. When the input registers are full, the write data bits are coupled in parallel to a bank of memory cells. The number of bits in the write data bus is preferably a submultiple of the number of bits in the read data bus.

The invention discloses a multi-core and multi-threading processor-based functional macropipeline implementing method. A plurality of processors are divided into different clusters, namely a receiving cluster and a transmitting cluster; the plurality of processors have parallel structures in the receiving cluster and the transmitting cluster; the receiving cluster is responsible for receiving messages, a parallel structure is adopted in the receiving cluster, and all packet receiving tasks are completed parallelly by a plurality of threadings; and the transmitting cluster is responsible for transmitting the messages, including checking whether a new data packet transmitting task is present, acquiring queue descriptor information of the current head pointer after reading a new transmitting task, transmitting a data packet from a synchronous dynamic random access memory (SDRAM) unit specified by a descriptor to a specified transmitting buffer unit and maintaining synchronous communication between the head pointer of a queue and the receiving cluster, a parallel structure is adopted in the transmitting cluster, and all packet transmitting tasks are completed parallelly by a plurality of threadings.

A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of an encoding circuit controlled by a first test signal to output a parity bit corresponding to an information bit, a decoding circuit controlled by second test signal to output an error location detecting signal indicating an error bit in codeword, and an error correcting circuit controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.

A method and apparatus to dynamically set the insertion point of a delay line control shift register based on the current cycle time. A string of delay elements equivalent to the delay elements in a delay lock loop (DLL) are laid out in the opposite direction compared to the DLL delay elements. Both strings of delay elements receive a synchronous input signal such as an external clock signal. The output clock signal of the DLL is phase-shifted relative to the external clock signal such that data removed from a device such as a synchronous dynamic random access memory (SDRAM) device is synchronous with the external clock signal. When a DLL reset command is issued, the information from the string of delay elements is captured and used to set the insertion point of the DLL to the locked or phase-equal point. This allows the DLL to quickly lock on any frequency upon reset of the DLL.

The invention discloses a high-speed high-accuracy recorder and a designing method thereof. The high-speed high-accuracy recorder comprises a signal conditioning module, four analogue-to-digital converter (ADC) modules, four first in first out (FIFO) modules, two synchronous dynamic random access memory (SDRAM) modules, a client-server architecture control module, a synchronous coherent clock module, a high-accuracy reference voltage source module and the like, wherein the client-server architecture control module consists of an advanced RISC machine (ARM) unit and a field programmable gate array (FPGA) unit; and the synchronous coherent clock module takes a clock chip as a core. The recorder finishes the operations of 'time-interleaved' sampling, encapsulation, caching, transmission, decapsulation combination, correction, storage, uploading and the like concurrently under the control of a concurrent time sequence logic, corrects sampling data based on an inter-ADC channel mismatchingautomatic-correction polynomial to reduce gain mismatching and offset/zero mismatching among ADC channels, reduces time mismatching among the ADC channels by using a synchronous coherent clock and a serpentine curve wire-length fine-adjustment technology, and solves the problems of associated global errors produced by data loss in the high-speed 'time-interleaved' sampling by using a high-order matching technology in which the encapsulation is performed by additional timestamp sequence numbers.

An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level, where the first and second voltage levels may vary over time. In one embodiment, the input buffer includes a first and second detector circuits, an average generator circuit, and a differential amplifier. The first detector circuit receives the input signal and produces a first signal having a magnitude indicative of the first voltage level. The second detector circuit receives the input signal and produces a second signal having a magnitude indicative of the second voltage level. The average generator circuit receives the first and second signals, and uses the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level. The third voltage level defines a variable an automatically adjusted "switching point". The differential amplifier receives the input signal, the third signal, and a first and second power supply voltages. The differential amplifier amplifies a difference between the voltage magnitude of the input signal and the third voltage level in order to produce an output signal which alternates between the first and second power supply voltages. An integrated circuit is described including the input buffer coupled between one of a set of input/output pads and circuitry, wherein the circuitry may be synchronous dynamic random access memory (SDRAM) circuitry.

The invention relates to a technique for dynamically loading processor application programs and a hardware system for realizing the technique. The system mainly comprises a digital signal processor (DSP) 11, a field programmable gate array (FPGA) processor 17, a complex programmable logic device (CPLD) 16, a FLASH memory 13, a synchronous dynamic random access memory (SDRAM) 12, an interface chip14 and a power module 15, wherein fixed programs in the FLASH memory 13 comprise a DSP bootstrap program, a DSP management program and a plurality of FPGA and DSP application programs. A method for implementing the system has the characteristics that: dynamic loading and on-line updating of the FPGA application program and the DSP application program are realized by using the management program; the jump among the bootstrap program, the management program and the application programs is realized by the DSP technique so as to complete the dynamic loading function; and the FPGA is taken over bythe CPLD so as to configure a bus and the FPGA application program is loaded by combining the DSP.

A data control circuit for a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) that secures a stable reading/writing operation of DDR SDRAM data by generating an actively controllable internal data strobe signal. The data control circuit includes an internal data strobe signal generating circuit generating and outputting an internal data strobe signal a rising edge of which is located in a center part of valid DDR SDRAM data; a read data control circuit for receiving the internal data strobe signal, generated from the internal data strobe signal generating circuit as a clock input, dividing captured data into even data and odd data, and transmitting the even data and the odd data to a system bus; and a write data control circuit transmitting the internal data strobe signal input from the internal data strobe signal generating circuit to a DDR SDRAM device as a data strobe signal.