Multi-core and multi-threading processor-based functional macropipeline implementing method

A multi-threaded processor and macro-pipeline technology, which is applied in the direction of machine execution devices and concurrent instruction execution, can solve the problem of maintaining packet order, achieve the effects of ensuring packet order, improving processing speed, and solving mutual exclusion of shared units

Inactive Publication Date: 2012-01-25
XIDIAN UNIV
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  • Abstract
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  • Application Information

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Problems solved by technology

This effective method or technology must be able to solve two problems in packet processing in network processors, one is the problem of ma...

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  • Multi-core and multi-threading processor-based functional macropipeline implementing method
  • Multi-core and multi-threading processor-based functional macropipeline implementing method
  • Multi-core and multi-threading processor-based functional macropipeline implementing method

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Embodiment Construction

[0028] A parallel programming model based on a multi-core network processor according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In the drawings, like reference numerals denote like elements throughout. It should be understood that the embodiments described herein are illustrative only and should not be construed as limiting the scope of the present invention.

[0029] Such as figure 1 Shown is a schematic diagram of a multi-core multi-thread network processor architecture 100 , including a general purpose processor 102 , a packet processing microprocessor 104 , a hierarchical memory system 106 , a coprocessor system 108 , and a data exchange system 110 .

[0030]The main functions performed by the general-purpose processor 102 include system startup initialization, code loading, control and management functions, processing of some high-level protocols, and exception packet processing. Functions on the contr...

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Abstract

The invention discloses a multi-core and multi-threading processor-based functional macropipeline implementing method. A plurality of processors are divided into different clusters, namely a receiving cluster and a transmitting cluster; the plurality of processors have parallel structures in the receiving cluster and the transmitting cluster; the receiving cluster is responsible for receiving messages, a parallel structure is adopted in the receiving cluster, and all packet receiving tasks are completed parallelly by a plurality of threadings; and the transmitting cluster is responsible for transmitting the messages, including checking whether a new data packet transmitting task is present, acquiring queue descriptor information of the current head pointer after reading a new transmitting task, transmitting a data packet from a synchronous dynamic random access memory (SDRAM) unit specified by a descriptor to a specified transmitting buffer unit and maintaining synchronous communication between the head pointer of a queue and the receiving cluster, a parallel structure is adopted in the transmitting cluster, and all packet transmitting tasks are completed parallelly by a plurality of threadings.

Description

technical field [0001] The invention relates to a method for realizing a function macro pipeline based on a multi-core multi-thread processor. Background technique [0002] With the rapid growth of network bandwidth, the programmability and versatility requirements of various network entities such as routers, switches, and gateways continue to increase. It is necessary to develop more complete applications to better utilize the performance advantages of multi-core processors. To meet the needs of various high-throughput, low-latency multimedia network communications has become the main problem currently facing. However, under the current parallel processing structure of various multi-core network processors, because the flexibility and high efficiency of parallel programming have not been well demonstrated, the parallel network processing capability is limited. The network parallel processing capability needs to take into account the hardware parallel structure and the para...

Claims

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Application Information

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IPC IPC(8): G06F9/38
Inventor 李康赵庆贺雷理范勇马佩军史江义郝跃
Owner XIDIAN UNIV
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