178 results about "Detector circuits" patented technology

Various wearable health monitoring devices are described herein. Some implementations include one or more emitter chamber covers injection molded out of a first material comprising transparent glass, one or more detector chamber covers injection molded out of a second material comprising transparent glass, and a light barrier construct injection molded out of a third material over the one or more emitter chamber covers and the one or more detector chamber covers. The third material may be opaque and can comprise glass and an optically absorbing pigment. Some implementations include a circuit board, emitter(s) mounted to the circuit board and arranged within the emitter chamber cover(s), and detector(s) mounted to the circuit board and arranged within the detector chamber cover(s). The circuit board, emitter(s), detector(s), emitter chamber cover(s), and detector chamber cover(s) can form part of a sensor assembly connected to a housing of the wearable health monitoring devices.

A detector circuit having a current conversion mechanism for a power converter is provided. An output terminal of the power converter is connected to a first terminal of an inductor. The detector circuit detects a current flowing through the inductor as a detected current, and converts the detected current into a detected voltage. The detector circuit compares the detected voltage with a reference voltage to generate a comparison signal. Each time when a level of the comparison signal reaches a reference level, the detector circuit counts a count value.

Event-based sensor systems and method for operating event-based sensor systems are disclosed. A sensor system includes an array of sensor elements arranged in columns and rows, wherein each sensor element in the array of sensor elements includes, a detector circuit, an active pixel sensor (APS) circuit, and a dynamic vision sensor (DVS) circuit, the DVS circuit including an event trigger switch configured to control application of a signal on an event trigger line in response to a pixel-specific event trigger signal.

A demodulation circuit includes a slope detector circuit and a comparator circuit. The slope detector circuit is configured detect a change in the voltage and determine if the voltage rate of change meets or exceeds one of a rise threshold or a fall threshold. The comparator circuit is configured to set an upper limit and lower limit for rate of change, compare the voltage rate of change to the limits, determine that the voltage rate of change meets or exceeds the limits, if the voltage rate of change meets or exceeds the rising and falling rate of change limits, (v) set a lower limit for a falling rate of change, (vi) receive the voltage rate of change and determine that the voltage rate of change meets or exceeds the fall or rise threshold, if the voltage rate of change meets or exceeds the falling or rising rate of change.

The embodiment of the utility model provides a radiation detector module, a radiation detector and imaging equipment. The radiation detector module comprises a detector circuit board which is provided with a detector element for converting received rays emitted by a radiation source into electric signals, and the detector circuit board is provided with a first positioning hole; the collimator assembly is arranged on a transmission path of the rays and collimates the rays radiated to the detector element, and the collimator assembly is provided with a second positioning hole corresponding to the first positioning hole in position; and the frame supports the detector circuit board and the collimator assembly, the frame is provided with a positioning column, and the positioning column penetrates through the first positioning hole and the second positioning hole. According to the radiation detector module, the difficulty of alignment operation can be reduced, accumulation of alignment errors generated in multiple times of alignment operation is reduced, the alignment precision of all the components is improved, and then the detection precision of the radiation detector module is improved.

A memory device includes a test mode detector circuit that determines whether the memory device has entered a test mode based on at least one test mode entry signal received through at least one pin of a plurality of pins and generates a test mode detection signal, and a test pad connection circuit that electrically couples a first pin of the plurality of pins to a dedicated test pad of the test mode such that a signal applied to the first pin is transmitted to the dedicated test pad based on the test mode detection signal.

A Light Detection and Ranging (LIDAR) detector circuit includes a memory device comprising a first memory and a second memory, and at least one control circuit. The at least one control circuit is configured to execute first memory storage operations to store data indicated by detection signals received from one or more photodetector elements in the first memory during a first portion of a time between pulses of an emitter signal output from a LIDAR emitter element, and to execute second memory storage operations to include the data, which was stored in the first memory, in the second memory during a second portion of the time between the pulses of the emitter signal. Related devices and methods of operation are also discussed.

A processing circuit coupled to an imaging device includes a bus interface circuit configured to communicatively couple the processing circuit to the imaging device through a multipoint differential serial link; a detector circuit configured to detect a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states relating to transmission of data packets through the multipoint differential serial link; and a controller. The controller is configured to: discard data packets received after the imaging device is powered on or initialized and until the imaging device is indicated to be in an active operating state; counting a transition sequence between a first signaling state of the multipoint differential serial link and a second signaling state of the multipoint differential serial link; and instructing the imaging device to be in the active operating state after the pre-configured number of data packets have been discarded.

Provided are an iterative detection and decoding (IDD) circuit, which includes a multiple-input and multiple-output (MIMO) detector having low power consumption, an operation method of the IDD circuit, and a modem chip. The IDD circuit, which is configured to receive a signal including a symbol, includes a first detector configured to generate a first log-likelihood ratio based on the symbol by using a linear detection method, a decoding circuit configured to perform a first decoding operation based on the first log-likelihood ratio and to generate a post-log-likelihood ratio when the first decoding operation fails, and a second detector configured to, when the first decoding operation fails, generate a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method, wherein the decoding circuit is further configured to perform a second decoding operation based on the second log-likelihood ratio.

Device and method for measuring a junction temperature of a power semiconductor (3) using the resistance Rgint (32) of said semiconductor (3) comprising at least: a current injector circuit (5) injecting current pulses Iinj in the gate path of said power semiconductor (3) through the emitter of said power semiconductor, said current injector circuit (5) being driven by a digital injection control circuit (4, 6) to synchronize said current pulses within a stabilized part of ON states of the power semiconductor driver (1) PWM signal driving said power semiconductor (3), a peak detector circuit (7) to record emitter voltage peaks Ve at the terminals of the current injector circuit and generate a continuous signal Vpks dependent of the junction temperature Tj through integration of said voltage peaks, a signal conditioning circuit (8) to adapt the continuous signal Vpks dependent of the junction temperature into a range of 3V to 5V of a measurement system (9).

Circuits and methods are provided that use a comparator circuit within a multi-level converter to identify a signal that controls access to a loop circuit. A loop circuit receives multiple signals requesting multiple currents from the loop circuit. A comparator within the loop circuit determines a control signal indicating one of the multiple signals that controls the loop circuit, where the one of the signals that controls the loop circuit is associated with a lowest current from multiple currents.

A light detection and ranging (LIDAR) detector circuit includes a memory device and at least one control circuit. The memory device includes a non-transitory storage medium configured to store data indicating a detection event in a corresponding memory bin. The at least one control circuit is configured to receive a detection signal from one or more photodetector elements, identify the presence or absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, and, in response to the identification of the presence or absence of a detection event, respectively, perform one of a first memory operation or a second memory operation to update the data in the corresponding memory bin. Related circuits and operating methods are also discussed.

A control system includes a movable device, memory, and circuitry. The movable device includes a reflector; paired movable portion; and a detector to detect deflection angle of the reflector. The circuitry outputs drive signals to the paired movable portions, respectively; generates the drive signals based on variables of a symmetry of each of the drive signals and a phase difference between the drive signals; detects, from the movable device, the deflection angle of the reflector by the detector; extract an amplitude of a high-frequency component from a detection signal; store, in the memory, information in which the amplitude of the high-frequency component is associated with values of the variables of the drive signals; select a combination of the values of the variables based on the high-frequency component and the information stored in the memory; and update the drive signals based on the combination of the values of the variables selected.

This invention relates to a detector support structure, specifically a space payload detector support structure and installation method that combines vibration isolation and heat dissipation. It primarily addresses the technical problem that existing detector support structures cannot simultaneously solve the vibration isolation and heat dissipation issues of space payload detectors. The structure includes a heat sink, a flexible heat-conducting cable, a heat-conducting plate, and a bracket. The heat sink is connected to the temperature control surface of the external space payload. One end of the flexible heat-conducting cable is connected to the heat sink, and the other end is connected to the heat-conducting plate. The heat-conducting plate has a glue injection groove, a temperature probe mounting groove, and a fixing hole on its end face. The detector circuit board and the detector body are respectively disposed on the upper and lower end faces of the heat-conducting plate, and the detector pins are connected to corresponding holes on the detector circuit board. The temperature probe is installed in the temperature probe mounting hole. The bracket is connected to both the detector circuit board and the external optical platform. This detector support structure effectively combines vibration isolation and heat dissipation.

Systems and methods for use in cloud-based digital vehicle alerting are disclosed. In an example, a device includes a global positioning system (GPS) unit, a wireless transmitter, an input voltage interface, a voltage detector circuit electrically connected to the input voltage interface and configured to detect a voltage at the input voltage interface, and alerting mode logic configured to transition from a non-alerting mode to an alerting mode in response to the voltage detected by the voltage detector circuit exceeding a threshold voltage, and transition from the alerting mode back to the non-alerting mode in response to the voltage detected by the voltage detector circuit not exceeding the threshold voltage for an entire delay interval, where the wireless transmitter is configured to transmit alerting vehicle telemetry data, which includes location information generated by the GPS unit, in response to the alerting mode of the alerting mode logic.

A detector circuit includes a parametric resonator circuit comprising a first varactor and a second varactor disposed in a loop. The parametric resonator has a conductor disposed between the first varactor and the second varactor. The detector circuit further includes a voltage sensing resonator circuit aligned on the parametric resonator circuit so that at least a first portion of the resonator circuit is disposed in the loop and a second portion is disposed outside the loop in an axial view.

An ADC (50) is disclosed. It has two VTCs (110a, 110b) for converting a first and a second input voltage, respectively, to pulses with delays corresponding to the magnitudes of these voltages. It further has a pulse-detector circuit (120) coupled to outputs (114a, 114b) of the two VTCs (110a, 110b). The pulse-detector circuit (120) is configured to make a transition from a first logic state (‘0’) to a second logic state (‘F) at a first output (124a) of the pulse-detector circuit (120) in response to the start of the pulse from one of the VTCs (110a) and to make a transition from the first logic state (‘0’) to the second logic state (‘F) at a second output (124b) of the pulse-detector circuit (120) in response to the start of the pulse from the other VTC. Furthermore, the pulse-detector circuit (120) is configured to reset both the first and the second output (124a, 124b) to the first logic state (‘0’) in response to both the first output (124a) and the second output (124b) of the pulse-detector circuit (120) being set in the second logic state (‘1’). The ADC (50) further has a first TDC (130a) coupled to the first output (124a) of the pulse-detector circuit (120) and a second TDC (130b) coupled to the second output (124b) of the pulse-detector circuit (120).

An injection locked ring oscillator (ILRO) system is disclosed. The ILRO system includes an ILRO circuit configured to receive a plurality of injection control signals and a phase control signal, and to generate a plurality of output clock signals; a phase detector circuit configured to receive the output clock signals and to generate a phase output signal based on phase differences of particular pairs of the output clock signals; and a phase to voltage circuit configured to receive the phase output signal from the phase detector circuit, and to generate the phase control signal based on the phase output signal, where the phase control signal presents a negative feedback phase signal to the ILRO circuit for the phase differences in the particular pairs of the output clock signals.

A system and method for analyzing an air sample from a human uses a collection module that has a plurality of metal oxide semiconductor sensors that have different resistance responses to different gaseous compounds. A detector circuit reads the output of the sensors as analog signals for both ambient air and the air sample from the human. The ratios of the analog signals from ambient air and from the air sample can be compared to similar information from other health and unhealthy human subjects to determine the health status of the human. In one embodiment the system is used for breath analysis.

The present invention provides a security system configured on a chip to be protected, the system including fault injection detection subsystems configured on the chip, each fault injection detection subsystem having a plurality of real-time selectable sensitivity levels and including at least one hardware fault injection detector circuit disposed on the chip and / or sensitivity level control logic coupled with the hardware fault injection detector circuit, deployable on the chip and operable in real-time to transition the fault injection detection subsystem from a current sensitivity level of the plurality of selectable sensitivity levels to a next sensitivity level of the plurality of selectable sensitivity levels, for example by generating a sensitivity control signal (also referred to as a sensitivity level selection) and / or sending the sensitivity control signal to at least one hardware fault injection detector circuit in the fault injection detection subsystem. The fault injection countermeasure circuit is operated to protect the processor from fault injection attacks dynamically depending on the execution flow of the processor core.

An overload detector circuit comprises a first logic circuit and a second logic circuit. The first logic circuit receives a bitstream from a sigma-delta modulator (SDM) of a receiver channel. This circuit compares a current bit of the bitstream with a previous bit and outputs an indication of a match. The second logic circuit tracks a number of consecutive matches in the bitstream and outputs an indication of a first overload state when the number of consecutive matches meets a first threshold criterion.

An embodiment buck converter control circuit comprises an error amplifier configured to generate an error signal based on a feedback signal and a reference signal, a pulse generator circuit configured to generate a pulsed signal having switching cycles set to high and low as a function of the error signal, a driver circuit configured to generate a drive signal for an electronic switch of the buck converter as a function of the pulsed signal, a variable load, connected between two output terminals of the buck converter, configured to absorb a current based on a control signal, and a detector circuit configured to monitor a first signal indicative of an output current provided by the buck converter and a second signal indicative of a negative transient of the output current, and verify whether the second signal indicates a negative transient of the output current.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

A lighting apparatus includes a rectifier bridge circuit, a light source, a LED controller, a dimmer detector circuit and a bleeder circuit. The rectifier bridge circuit converts an AC power to a DC power. The LED controller for generates a plurality of driving currents based on the DC power to respectively control plurality of LED modules of different types. The dimmer detector circuit detects whether a dimmer is coupled to the lighting apparatus. The bleeder circuit is coupled to the dimmer detector circuit. The bleeder circuit is configured to be turned on when the dimmer detector circuit detects that the dimmer is coupled to the lighting apparatus for fixing a signal distortion for power input to the LED controller. The signal distortion is caused by the dimmer.

High speed data weighted average (DWA) to binary conversion circuits are disclosed. A latch circuit latches a first data weighted average (DWA) data word in sequence and then latches a second DWA data word. A first detector circuit identifies a first bit position in the first DWA data associated with an end of a first string of logical one bits in the first DWA data word. A second detector circuit identifies a second bit position in the second DWA data word associated with an end of a second string of logical one bits in the second DWA data word. The DWA to binary conversion circuit converts the second DWA data word to a binary word by using the first bit position and the second bit position to identify a number of logical one bits present in the second DWA data word. A binary value equal to the identified number is outputted for the binary word.

A power amplification device includes a substrate having first and second surfaces on sides opposite to each other; a first integrated circuit and a coupler that are on the first surface; and a second integrated circuit on the second surface. The first integrated circuit includes a splitter; a carrier amplifier that amplifies an inputted high-frequency signal; a peak amplifier that amplifies an inputted high-frequency signal; a first bias circuit that provides bias to the carrier amplifier; and a second bias circuit that provides bias to the peak amplifier. The second integrated circuit includes a detector circuit that outputs a control signal to control bias of the peak amplifier, and the detector circuit varies a threshold for the control signal, based on a first high-frequency signal inputted to the first integrated circuit from the outside and a signal indicating a drive level of the carrier amplifier.

An example circuit, method, and electronic device configured to filter pulses below a minimum threshold pulse width and provide delays that exhibit low variance to changes in temperature, voltage, and technology processes, are provided. The example circuit includes a first flip / flop, a second flip / flop, and a charge detector. The first flip / flop generates a first out signal and a first inverse signal based on an input signal and a first clocking signal. The second flip / flop generates an output signal and a second out signal based on the first out signal, the first inverse signal, and a second clocking signal, wherein the second clocking signal is an inverse of the first clocking signal. The charge detector circuit includes a charging capacitor to generate a charge signal based on a change in the input signal, such that pulses are filtered based on a capacitance value of the charging capacitor and a reference voltage.

The invention relates to the technical field of fire fighting equipment, in particular to a manufacturing method of a fire detector shell, the shell and a fire detector, and aims to solve the problems that in the prior art, the insulating property is remarkably reduced in a high-temperature environment, the insulating resistance value of a conventional insulating material is sharply reduced at 150-200 DEG C, and the insulating property is poor. And the normal work of the detector circuit is severely influenced. The performance of the base material and the coating is optimized through a specific formula and manufacturing steps, splicing treatment is strengthened, the problems that high-temperature insulation is reduced, flame retardance is uneven and splicing is weak are solved, and the method has the advantages that the insulation performance in the high-temperature environment is improved, it is ensured that flame retardance is evenly distributed, and sealing protection at the splicing position is enhanced.

The application relates to an omnidirectional visible light communication device, which comprises a reflector (1) and a reflecting bowl (2), the reflector (1) is located above the reflecting bowl (2) and the two have a common central axis; the reflector (1) is of a solid structure, the upper surface is a circular plane, the lower surface is a convex parabolic curved surface, the lower surface is mirror-polished and is coated with a reflecting film with a reflectivity greater than 90%; the reflecting bowl (2) is designed in a parabolic curved surface and is provided with a hole in the bottom center, the shape of the hole is circular; the reflecting bowl (2) is provided with a focusing lens group (3) at the position of the hole in the bottom center, a detector circuit board (4) is arranged below the focusing lens group (3), the detector circuit board (4) is provided with photosensitive detectors for converting optical signals into electrical signals, and the detector circuit board (4) is connected with a transceiving and processing circuit board (5) through wires. The application is not limited by the existing directivity problem any more, and direct communication is realized without aiming.

Devices and methods for measuring an analyte. A sensing device includes a sensor and a detection circuit operatively coupled to the sensor. The sensor includes a working electrode having an aptamer and an attached redox couple to electrochemically measure the analyte. The detection circuit is configured to apply a first scan having a first scan range to the sensor, and determine a position of a redox peak in the first scan. In response to the first scan range not matching the position of the redox peak, the detector circuit defines a second scan range that matches the position of the redox peak, and applies a second scan having the second scan range to the sensor.