391 results about "Detector circuits" patented technology

Various wearable health monitoring devices are described herein. Some implementations include one or more emitter chamber covers injection molded out of a first material comprising transparent glass, one or more detector chamber covers injection molded out of a second material comprising transparent glass, and a light barrier construct injection molded out of a third material over the one or more emitter chamber covers and the one or more detector chamber covers. The third material may be opaque and can comprise glass and an optically absorbing pigment. Some implementations include a circuit board, emitter(s) mounted to the circuit board and arranged within the emitter chamber cover(s), and detector(s) mounted to the circuit board and arranged within the detector chamber cover(s). The circuit board, emitter(s), detector(s), emitter chamber cover(s), and detector chamber cover(s) can form part of a sensor assembly connected to a housing of the wearable health monitoring devices.

Apparatuses and methods per row activation counter testing (PRACT). A memory includes an aggressor detector circuit, which determines a row address to be an aggressor address after the row address is accessed a number of times. In a normal mode the address is an aggressor after a first number of activations, while in a PRACT mode the address is an aggressor after a second (generally lower) number of activations. For example, when the row is accessed a first value may be added to a count in the normal mode and a second (generally larger) value in the PRACT mode. When the count crosses a threshold, the row is an aggressor.

Techniques are disclosed that relate to executing pairs of instructions. A processor may include fusion detector circuitry configured to detect a pair of fetched instructions and fuse the pair of fetched instructions into a fused instruction operation, and execution circuitry coupled to the fusion detector circuitry and configured to execute the fused instruction operation. In some embodiments the pair of instructions is executable to generate a remainder of a division operation. In some embodiments the pair of instructions is executable to compare two operands and perform a write operation based on the comparison. In some embodiments the pair of instructions is executable to perform an operation and apply a mask bit sequence to the result. The fusion detector circuitry may also be configured to obtain first and second portions of a constant value from first and second instructions and store the first and second portions in a destination register.

Apparatuses and methods per-row count based refresh target identification. A memory device stores count values associated with the word lines. An aggressor detector circuit stores a maximum of the count values and a row address associated with the maximum count value. Responsive to a targeted refresh signal, the stored count value is compared to a threshold. If the count value has crossed the threshold, then a targeted refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.

A detector circuit having a current conversion mechanism for a power converter is provided. An output terminal of the power converter is connected to a first terminal of an inductor. The detector circuit detects a current flowing through the inductor as a detected current, and converts the detected current into a detected voltage. The detector circuit compares the detected voltage with a reference voltage to generate a comparison signal. Each time when a level of the comparison signal reaches a reference level, the detector circuit counts a count value.

A driver circuit is coupled to a control circuit which is configured to control a plurality of pixels. The driver circuit includes a detector circuit and an outputting circuit. The detector circuit is configured to detect whether an error occurs or not. The outputting circuit is configured to output an enable signal to the control circuit. When the error occurs, the enable signal changes from a first level to a second level such that the control circuit stops outputting a plurality of control signals to the plurality of pixels.

Event-based sensor systems and method for operating event-based sensor systems are disclosed. A sensor system includes an array of sensor elements arranged in columns and rows, wherein each sensor element in the array of sensor elements includes, a detector circuit, an active pixel sensor (APS) circuit, and a dynamic vision sensor (DVS) circuit, the DVS circuit including an event trigger switch configured to control application of a signal on an event trigger line in response to a pixel-specific event trigger signal.

A system including a memory sub-system controller to transmit a data signal via a communication channel. The system includes a receiver to receive the data signal from the memory sub-system controller via an interface, the receiver comprising a decision feedback equalizer (DFE) sub-system. The DFE sub-system includes a first data detector circuit including a first tap circuit, where the first data detector circuit generates, using a first reference voltage, a first subset of detected values corresponding to the data signal. The DFE sub-system includes a second data detector circuit including a second tap circuit, where the second data detector circuit generates a second subset of detected bit values corresponding to the data signal using a second reference voltage.

A signal processing circuit for a spiking neural network includes an interface for converting an analog input signal to a corresponding pulse-time representation of the analog input signal. The interface includes: an analog-to-information (A / information) converter configured to: generate a modulated signal representative of one or more characteristics of an analog input signal; a feature detector circuit configured to: compare the modulated signal to a reference signal representative of a reference feature, and configured to: generate an error signal indicative of a difference between the modulated signal and the reference signal; a feature extractor circuit comprising a locked loop circuit having an input for receiving the error signal and configured to: generate an output signal representative of an occurrence of one or more features represented by the modulated signal; and an encoder circuit configured to encode the output signal into a pulse sequence for input to the spiking neural network.

A ripple voltage detector circuit comprises a pulse generator, a direct current-to-direct current (DC-DC) converter coupled to the pulse generator, and a first control loop coupled to the pulse generator and the DC-DC converter. The first control loop is configured to measure an output voltage of the DC-DC converter, determine an output ripple voltage of the output voltage, determine a ripple coefficient based on the output ripple voltage, determine a reference peak inductor current based on the ripple coefficient, and determine a peak value of an inductor current during a switching cycle, and transition a switching state of the DC-DC converter based on the reference peak inductor current and the peak value of the inductor current.

The application provides a bathtub lamp driven by wireless power transmission, which comprises a lamp holder and a lamp body wirelessly connected with the lamp holder. An active level signal of a PWM signal generated by an LED controller to control a R-LED module / G-LED module / B-LED module is modulated with a high-frequency signal corresponding to a fixed frequency generator through a modulation amplifier in the lamp holder to generate a wireless power transmission signal and amplify the wireless power transmission signal for output, the wireless transmission of the wireless power transmission signal and electric energy is realized through the cooperation of a corresponding transmitting resonator and a receiving resonator in the lamp body; the corresponding PWM signals in the respective wireless power transmission signals are extracted by a detector circuit in the lamp body and output to drive the R-LED module / G-LED module / B-LED module for variable light-emitting operations.

A battery abnormality detection device that: for an equalization circuit including a discharge circuit provided with a switch that, in a case of being switched ON, causes a battery cell to discharge, and including a detector connected to the battery cell in parallel to the discharge circuit so as to detect a voltage of the battery cell, acquires a first voltage in a case in which the switch has been switched OFF and a second voltage in a case in which the switch has been switched ON, as detected by the detector, and estimates, from a detected value of one of the acquired first voltage or second voltage, an estimated value of another of the acquired first voltage or second voltage, and determines whether or not an abnormality has occurred in the equalization circuit based on the detected value and the estimated value.

A circuit is disclosed. The circuit includes a transmitter having an input terminal arranged to receive input data and a transmission node arranged to transmit intermediate data corresponding to the input data, and a receiver having a receive node arranged to receive the intermediate data and an output terminal arranged to produce output data corresponding to the input data, the receiver further including a dV / dt detector circuit coupled to the receive node and arranged to stop the production of the output data at the output terminal when the dV / dt detector circuit detects a rate of change of voltage with respect to time greater than a predetermined threshold.

A demodulation circuit includes a slope detector circuit and a comparator circuit. The slope detector circuit is configured detect a change in the voltage and determine if the voltage rate of change meets or exceeds one of a rise threshold or a fall threshold. The comparator circuit is configured to set an upper limit and lower limit for rate of change, compare the voltage rate of change to the limits, determine that the voltage rate of change meets or exceeds the limits, if the voltage rate of change meets or exceeds the rising and falling rate of change limits, (v) set a lower limit for a falling rate of change, (vi) receive the voltage rate of change and determine that the voltage rate of change meets or exceeds the fall or rise threshold, if the voltage rate of change meets or exceeds the falling or rising rate of change.

The embodiment of the utility model provides a radiation detector module, a radiation detector and imaging equipment. The radiation detector module comprises a detector circuit board which is provided with a detector element for converting received rays emitted by a radiation source into electric signals, and the detector circuit board is provided with a first positioning hole; the collimator assembly is arranged on a transmission path of the rays and collimates the rays radiated to the detector element, and the collimator assembly is provided with a second positioning hole corresponding to the first positioning hole in position; and the frame supports the detector circuit board and the collimator assembly, the frame is provided with a positioning column, and the positioning column penetrates through the first positioning hole and the second positioning hole. According to the radiation detector module, the difficulty of alignment operation can be reduced, accumulation of alignment errors generated in multiple times of alignment operation is reduced, the alignment precision of all the components is improved, and then the detection precision of the radiation detector module is improved.

A memory device includes a test mode detector circuit that determines whether the memory device has entered a test mode based on at least one test mode entry signal received through at least one pin of a plurality of pins and generates a test mode detection signal, and a test pad connection circuit that electrically couples a first pin of the plurality of pins to a dedicated test pad of the test mode such that a signal applied to the first pin is transmitted to the dedicated test pad based on the test mode detection signal.

A Light Detection and Ranging (LIDAR) detector circuit includes a memory device comprising a first memory and a second memory, and at least one control circuit. The at least one control circuit is configured to execute first memory storage operations to store data indicated by detection signals received from one or more photodetector elements in the first memory during a first portion of a time between pulses of an emitter signal output from a LIDAR emitter element, and to execute second memory storage operations to include the data, which was stored in the first memory, in the second memory during a second portion of the time between the pulses of the emitter signal. Related devices and methods of operation are also discussed.

Systems and methods for assessing a neurological condition of a user includes detectors positioned at a surface of a skin of a wrist of a hand of the user. The detectors include a first pair of detectors configured to output a first output and a second pair of detectors configured to output a second output based on detected electrical potentials. Circuitry is configured to reduce amplitudes indicative of frequency components characteristic of ambient noise from the first output and the second output, generate data values based upon the first output and the second output, extract features from the data values including at least a feature based on relative amplitudes between the first output and the second output, and analyze the extracted features to assess the neurological condition of the user.

The utility model provides an infrared thermal imaging machine core and an infrared thermal imager. The infrared thermal imaging machine core comprises a shutter assembly and a detector assembly. The detector assembly comprises a detector body and a circuit board support. The detector body comprises a detector circuit board and a detector chip arranged on the surface of one side of the detector circuit board; the circuit board bracket is arranged on one side, deviating from the detector chip, of the detector circuit board; and the shutter assembly covers the detector assembly and is fixedly connected with the circuit board bracket to form a closed space for accommodating the detector body. The infrared thermal imaging machine core and the infrared thermal imager provided by the utility model have the advantages of small and exquisite structure, wide application range and the like.

A processing circuit coupled to an imaging device includes a bus interface circuit configured to communicatively couple the processing circuit to the imaging device through a multipoint differential serial link; a detector circuit configured to detect a plurality of sequentially occurring signaling states of the multipoint differential serial link, the plurality of sequentially occurring signaling states relating to transmission of data packets through the multipoint differential serial link; and a controller. The controller is configured to: discard data packets received after the imaging device is powered on or initialized and until the imaging device is indicated to be in an active operating state; counting a transition sequence between a first signaling state of the multipoint differential serial link and a second signaling state of the multipoint differential serial link; and instructing the imaging device to be in the active operating state after the pre-configured number of data packets have been discarded.

Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.

Provided are an iterative detection and decoding (IDD) circuit, which includes a multiple-input and multiple-output (MIMO) detector having low power consumption, an operation method of the IDD circuit, and a modem chip. The IDD circuit, which is configured to receive a signal including a symbol, includes a first detector configured to generate a first log-likelihood ratio based on the symbol by using a linear detection method, a decoding circuit configured to perform a first decoding operation based on the first log-likelihood ratio and to generate a post-log-likelihood ratio when the first decoding operation fails, and a second detector configured to, when the first decoding operation fails, generate a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method, wherein the decoding circuit is further configured to perform a second decoding operation based on the second log-likelihood ratio.

A circuit is disclosed. The circuit includes a transmitter having an input terminal arranged to receive input data and a transmission node arranged to transmit intermediate data corresponding to the input data, and a receiver having a receive node arranged to receive the intermediate data and an output terminal arranged to produce output data corresponding to the input data, the receiver further including a dV / dt detector circuit coupled to the receive node and arranged to stop the production of the output data at the output terminal when the dV / dt detector circuit detects a rate of change of voltage with respect to time greater than a predetermined threshold.

Device and method for measuring a junction temperature of a power semiconductor (3) using the resistance Rgint (32) of said semiconductor (3) comprising at least: a current injector circuit (5) injecting current pulses Iinj in the gate path of said power semiconductor (3) through the emitter of said power semiconductor, said current injector circuit (5) being driven by a digital injection control circuit (4, 6) to synchronize said current pulses within a stabilized part of ON states of the power semiconductor driver (1) PWM signal driving said power semiconductor (3), a peak detector circuit (7) to record emitter voltage peaks Ve at the terminals of the current injector circuit and generate a continuous signal Vpks dependent of the junction temperature Tj through integration of said voltage peaks, a signal conditioning circuit (8) to adapt the continuous signal Vpks dependent of the junction temperature into a range of 3V to 5V of a measurement system (9).

A device may have a reference divider circuit to divide a reference clock, a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, a loop filter circuit to filter the detector output, a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, a VCO clock divider control output pin to select a divisor of an external clock divider circuit, a divided VCO clock input pin for coupling to an output of the external clock divider circuit, a pulse-width modulation (PWM) circuit having a PWM clock input coupled to the divided VCO clock input pin, a period register to store a period value, a duty cycle register to store a duty cycle value and a pulse-width modulated output based on the period value and the duty cycle value.

Circuits and methods are provided that use a comparator circuit within a multi-level converter to identify a signal that controls access to a loop circuit. A loop circuit receives multiple signals requesting multiple currents from the loop circuit. A comparator within the loop circuit determines a control signal indicating one of the multiple signals that controls the loop circuit, where the one of the signals that controls the loop circuit is associated with a lowest current from multiple currents.

A light ranging system including a shaft having a longitudinal axis; a light ranging device configured to rotate about the longitudinal axis of the shaft, the light ranging device including a light source configured to transmit light pulses to objects in a surrounding environment, and detector circuitry configured to detect reflected portions of the light pulses that are reflected from the objects in the surrounding environment and to compute ranging data based on the reflected portion of the light pulses; a base subsystem that does not rotate about the shaft; and an optical communications subsystem configured to provide an optical communications channel between the base subsystem and the light ranging device, the optical communications subsystem including one or more turret optical communication components connected to the detector circuitry and one or more base optical communication components connected to the base subsystem.

A detector circuit for a measurement instrument is described. The detector circuit includes a first signal input, a second signal input, and an averaging sub-circuit. The first signal input is configured to receive a first complex-valued measurement signal associated with an input signal received from a device under test. The second signal input is configured to receive a second complex-valued measurement signal associated with the input signal received from the device under test. The averaging sub-circuit is configured to determine an average of the first complex-valued measurement signal and of a complex conjugate of the second complex-valued measurement signal over a predetermined number of samples, thereby obtaining a complex-valued average signal. The averaging sub-circuit is configured to generate an output signal based on the complex-valued average signal. Further, a signal processing circuit and a measurement instrument are described.

A light detection and ranging (LIDAR) detector circuit includes a memory device and at least one control circuit. The memory device includes a non-transitory storage medium configured to store data indicating a detection event in a corresponding memory bin. The at least one control circuit is configured to receive a detection signal from one or more photodetector elements, identify the presence or absence of a detection event indicated by the detection signal during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, and, in response to the identification of the presence or absence of a detection event, respectively, perform one of a first memory operation or a second memory operation to update the data in the corresponding memory bin. Related circuits and operating methods are also discussed.