120 results about "Detector circuits" patented technology

Event-based sensor systems and method for operating event-based sensor systems are disclosed. A sensor system includes an array of sensor elements arranged in columns and rows, wherein each sensor element in the array of sensor elements includes, a detector circuit, an active pixel sensor (APS) circuit, and a dynamic vision sensor (DVS) circuit, the DVS circuit including an event trigger switch configured to control application of a signal on an event trigger line in response to a pixel-specific event trigger signal.

A demodulation circuit includes a slope detector circuit and a comparator circuit. The slope detector circuit is configured detect a change in the voltage and determine if the voltage rate of change meets or exceeds one of a rise threshold or a fall threshold. The comparator circuit is configured to set an upper limit and lower limit for rate of change, compare the voltage rate of change to the limits, determine that the voltage rate of change meets or exceeds the limits, if the voltage rate of change meets or exceeds the rising and falling rate of change limits, (v) set a lower limit for a falling rate of change, (vi) receive the voltage rate of change and determine that the voltage rate of change meets or exceeds the fall or rise threshold, if the voltage rate of change meets or exceeds the falling or rising rate of change.

Provided are an iterative detection and decoding (IDD) circuit, which includes a multiple-input and multiple-output (MIMO) detector having low power consumption, an operation method of the IDD circuit, and a modem chip. The IDD circuit, which is configured to receive a signal including a symbol, includes a first detector configured to generate a first log-likelihood ratio based on the symbol by using a linear detection method, a decoding circuit configured to perform a first decoding operation based on the first log-likelihood ratio and to generate a post-log-likelihood ratio when the first decoding operation fails, and a second detector configured to, when the first decoding operation fails, generate a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method, wherein the decoding circuit is further configured to perform a second decoding operation based on the second log-likelihood ratio.

Device and method for measuring a junction temperature of a power semiconductor (3) using the resistance Rgint (32) of said semiconductor (3) comprising at least: a current injector circuit (5) injecting current pulses Iinj in the gate path of said power semiconductor (3) through the emitter of said power semiconductor, said current injector circuit (5) being driven by a digital injection control circuit (4, 6) to synchronize said current pulses within a stabilized part of ON states of the power semiconductor driver (1) PWM signal driving said power semiconductor (3), a peak detector circuit (7) to record emitter voltage peaks Ve at the terminals of the current injector circuit and generate a continuous signal Vpks dependent of the junction temperature Tj through integration of said voltage peaks, a signal conditioning circuit (8) to adapt the continuous signal Vpks dependent of the junction temperature into a range of 3V to 5V of a measurement system (9).

A control system includes a movable device, memory, and circuitry. The movable device includes a reflector; paired movable portion; and a detector to detect deflection angle of the reflector. The circuitry outputs drive signals to the paired movable portions, respectively; generates the drive signals based on variables of a symmetry of each of the drive signals and a phase difference between the drive signals; detects, from the movable device, the deflection angle of the reflector by the detector; extract an amplitude of a high-frequency component from a detection signal; store, in the memory, information in which the amplitude of the high-frequency component is associated with values of the variables of the drive signals; select a combination of the values of the variables based on the high-frequency component and the information stored in the memory; and update the drive signals based on the combination of the values of the variables selected.

This invention relates to a detector support structure, specifically a space payload detector support structure and installation method that combines vibration isolation and heat dissipation. It primarily addresses the technical problem that existing detector support structures cannot simultaneously solve the vibration isolation and heat dissipation issues of space payload detectors. The structure includes a heat sink, a flexible heat-conducting cable, a heat-conducting plate, and a bracket. The heat sink is connected to the temperature control surface of the external space payload. One end of the flexible heat-conducting cable is connected to the heat sink, and the other end is connected to the heat-conducting plate. The heat-conducting plate has a glue injection groove, a temperature probe mounting groove, and a fixing hole on its end face. The detector circuit board and the detector body are respectively disposed on the upper and lower end faces of the heat-conducting plate, and the detector pins are connected to corresponding holes on the detector circuit board. The temperature probe is installed in the temperature probe mounting hole. The bracket is connected to both the detector circuit board and the external optical platform. This detector support structure effectively combines vibration isolation and heat dissipation.

Systems and methods for use in cloud-based digital vehicle alerting are disclosed. In an example, a device includes a global positioning system (GPS) unit, a wireless transmitter, an input voltage interface, a voltage detector circuit electrically connected to the input voltage interface and configured to detect a voltage at the input voltage interface, and alerting mode logic configured to transition from a non-alerting mode to an alerting mode in response to the voltage detected by the voltage detector circuit exceeding a threshold voltage, and transition from the alerting mode back to the non-alerting mode in response to the voltage detected by the voltage detector circuit not exceeding the threshold voltage for an entire delay interval, where the wireless transmitter is configured to transmit alerting vehicle telemetry data, which includes location information generated by the GPS unit, in response to the alerting mode of the alerting mode logic.

A detector circuit includes a parametric resonator circuit comprising a first varactor and a second varactor disposed in a loop. The parametric resonator has a conductor disposed between the first varactor and the second varactor. The detector circuit further includes a voltage sensing resonator circuit aligned on the parametric resonator circuit so that at least a first portion of the resonator circuit is disposed in the loop and a second portion is disposed outside the loop in an axial view.

An ADC (50) is disclosed. It has two VTCs (110a, 110b) for converting a first and a second input voltage, respectively, to pulses with delays corresponding to the magnitudes of these voltages. It further has a pulse-detector circuit (120) coupled to outputs (114a, 114b) of the two VTCs (110a, 110b). The pulse-detector circuit (120) is configured to make a transition from a first logic state (‘0’) to a second logic state (‘F) at a first output (124a) of the pulse-detector circuit (120) in response to the start of the pulse from one of the VTCs (110a) and to make a transition from the first logic state (‘0’) to the second logic state (‘F) at a second output (124b) of the pulse-detector circuit (120) in response to the start of the pulse from the other VTC. Furthermore, the pulse-detector circuit (120) is configured to reset both the first and the second output (124a, 124b) to the first logic state (‘0’) in response to both the first output (124a) and the second output (124b) of the pulse-detector circuit (120) being set in the second logic state (‘1’). The ADC (50) further has a first TDC (130a) coupled to the first output (124a) of the pulse-detector circuit (120) and a second TDC (130b) coupled to the second output (124b) of the pulse-detector circuit (120).

The present invention provides a security system configured on a chip to be protected, the system including fault injection detection subsystems configured on the chip, each fault injection detection subsystem having a plurality of real-time selectable sensitivity levels and including at least one hardware fault injection detector circuit disposed on the chip and / or sensitivity level control logic coupled with the hardware fault injection detector circuit, deployable on the chip and operable in real-time to transition the fault injection detection subsystem from a current sensitivity level of the plurality of selectable sensitivity levels to a next sensitivity level of the plurality of selectable sensitivity levels, for example by generating a sensitivity control signal (also referred to as a sensitivity level selection) and / or sending the sensitivity control signal to at least one hardware fault injection detector circuit in the fault injection detection subsystem. The fault injection countermeasure circuit is operated to protect the processor from fault injection attacks dynamically depending on the execution flow of the processor core.

An overload detector circuit comprises a first logic circuit and a second logic circuit. The first logic circuit receives a bitstream from a sigma-delta modulator (SDM) of a receiver channel. This circuit compares a current bit of the bitstream with a previous bit and outputs an indication of a match. The second logic circuit tracks a number of consecutive matches in the bitstream and outputs an indication of a first overload state when the number of consecutive matches meets a first threshold criterion.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

High speed data weighted average (DWA) to binary conversion circuits are disclosed. A latch circuit latches a first data weighted average (DWA) data word in sequence and then latches a second DWA data word. A first detector circuit identifies a first bit position in the first DWA data associated with an end of a first string of logical one bits in the first DWA data word. A second detector circuit identifies a second bit position in the second DWA data word associated with an end of a second string of logical one bits in the second DWA data word. The DWA to binary conversion circuit converts the second DWA data word to a binary word by using the first bit position and the second bit position to identify a number of logical one bits present in the second DWA data word. A binary value equal to the identified number is outputted for the binary word.

A power amplification device includes a substrate having first and second surfaces on sides opposite to each other; a first integrated circuit and a coupler that are on the first surface; and a second integrated circuit on the second surface. The first integrated circuit includes a splitter; a carrier amplifier that amplifies an inputted high-frequency signal; a peak amplifier that amplifies an inputted high-frequency signal; a first bias circuit that provides bias to the carrier amplifier; and a second bias circuit that provides bias to the peak amplifier. The second integrated circuit includes a detector circuit that outputs a control signal to control bias of the peak amplifier, and the detector circuit varies a threshold for the control signal, based on a first high-frequency signal inputted to the first integrated circuit from the outside and a signal indicating a drive level of the carrier amplifier.

An example circuit, method, and electronic device configured to filter pulses below a minimum threshold pulse width and provide delays that exhibit low variance to changes in temperature, voltage, and technology processes, are provided. The example circuit includes a first flip / flop, a second flip / flop, and a charge detector. The first flip / flop generates a first out signal and a first inverse signal based on an input signal and a first clocking signal. The second flip / flop generates an output signal and a second out signal based on the first out signal, the first inverse signal, and a second clocking signal, wherein the second clocking signal is an inverse of the first clocking signal. The charge detector circuit includes a charging capacitor to generate a charge signal based on a change in the input signal, such that pulses are filtered based on a capacitance value of the charging capacitor and a reference voltage.

The invention relates to the technical field of fire fighting equipment, in particular to a manufacturing method of a fire detector shell, the shell and a fire detector, and aims to solve the problems that in the prior art, the insulating property is remarkably reduced in a high-temperature environment, the insulating resistance value of a conventional insulating material is sharply reduced at 150-200 DEG C, and the insulating property is poor. And the normal work of the detector circuit is severely influenced. The performance of the base material and the coating is optimized through a specific formula and manufacturing steps, splicing treatment is strengthened, the problems that high-temperature insulation is reduced, flame retardance is uneven and splicing is weak are solved, and the method has the advantages that the insulation performance in the high-temperature environment is improved, it is ensured that flame retardance is evenly distributed, and sealing protection at the splicing position is enhanced.

The application relates to an omnidirectional visible light communication device, which comprises a reflector (1) and a reflecting bowl (2), the reflector (1) is located above the reflecting bowl (2) and the two have a common central axis; the reflector (1) is of a solid structure, the upper surface is a circular plane, the lower surface is a convex parabolic curved surface, the lower surface is mirror-polished and is coated with a reflecting film with a reflectivity greater than 90%; the reflecting bowl (2) is designed in a parabolic curved surface and is provided with a hole in the bottom center, the shape of the hole is circular; the reflecting bowl (2) is provided with a focusing lens group (3) at the position of the hole in the bottom center, a detector circuit board (4) is arranged below the focusing lens group (3), the detector circuit board (4) is provided with photosensitive detectors for converting optical signals into electrical signals, and the detector circuit board (4) is connected with a transceiving and processing circuit board (5) through wires. The application is not limited by the existing directivity problem any more, and direct communication is realized without aiming.

A conductivity detector module for an ion chromatography system includes a detector unit configured to receive an eluate stream from the ion chromatography system, the detector unit including a first electrode and a second electrode in electrical contact with the eluate stream; a first current branch coupled to the first cell drive input and the first electrode and providing a first cell output; and a second current branch coupled to a second unit driving input and the second electrode and providing a second unit output, wherein the first unit driving input and the second unit driving input are equal in size and opposite in sign.

Image sensing device, comprising: pixel circuits 7. Each pixel circuit comprising: photo detector circuit comprising photo detector element 8 arranged to output time varying signal during gate period

Apparatuses, systems, and methods for clearing or resetting an access count value during a self-refresh mode. Various patterns of access to a row, sometimes called an aggressor row, may cause an increased rate of information decay in memory cells along nearby word lines, at which point they may be referred to as victim rows. Aggressor rows are identified by their access counts so that victim rows may be refreshed to prevent information decay. A memory may be placed in a self-refresh mode. During the self-refresh mode, a counter reset detector circuit clears or resets the access count value stored in counter memory cells associated with each address as it is refreshed. In this manner, potential victim rows are refreshed during the self-refresh mode along with would-be aggressor rows and fewer targeted refreshes may be issued.

A device may include: a reference divider circuit for dividing a reference clock; a phase-frequency detector circuit for detecting a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock; a loop filter circuit for filtering the detector output; a voltage-controlled oscillator (VCO) control output pin coupled to the loop filter output; a VCO clock divider control output pin for selecting the divisor of an external clock divider circuit; a divider VCO clock input pin coupled to the output of the external clock divider circuit; a pulse width modulation (PWM) circuit having a PWM clock input coupled to the divider VCO clock input pin; a period register for storing a period value; a duty cycle register for storing a duty cycle value; and a PWM output based on the period value and the duty cycle value.

Event-based sensor systems and method for operating event-based sensor systems are disclosed. A sensor system includes an array of sensor elements arranged in columns and rows, wherein each sensor element in the array of sensor elements includes, a detector circuit, an active pixel sensor (APS) circuit, and a dynamic vision sensor (DVS) circuit, the DVS circuit including an event trigger switch configured to control application of a signal on an event trigger line in response to a pixel-specific event trigger signal.

A tank level sensing system of the invention is used with a capacitive system having a pair of electrodes for capacitively coupling with a tank of fluid. A drive circuit provides a voltage drive signal to the drive electrode and a detector circuit is coupled with the sense electrode for detecting a sense voltage signal. A controller is coupled with the drive circuit and detector circuit to use the voltage drive signal and sense voltage signal for determining a fluid level of the tank. The controller varies the frequency of the voltage drive signal to the drive electrode through a plurality of frequencies and detects the sense voltage signal at the plurality of frequencies. The controller determines a plurality of endpoints at the plurality of different frequencies and selects one frequency for measurement. In one embodiment, the voltage drive signal is a sinusoidal voltage signal. In another embodiment, the plurality of frequencies includes base frequencies in a range of 1 kHz to 200 kHz that are offset with various dither frequencies. An output circuit outputs a signal reflective of the determined fluid level of the tank and provides selectable analog and digital output signals reflective of the determined fluid level of the tank.

A controller for a power converter includes a primary controller and a secondary controller. The primary controller is coupled to a primary winding of the energy transfer element and a primary switch of the power converter. The secondary controller is coupled to a secondary winding of the energy transfer element and a secondary switch, e.g., a synchronous rectifier, of the power converter. The secondary controller has a synchronous rectifier control / drive circuit, a control logic circuit, and a cross conduction detector circuit. Cross conduction is when the primary switch turns on when the secondary switch is active. The cross-conduction detector circuit produces a Disable SR signal when cross conduction event detected. The cross-conduction detector circuit detects zero voltage switching cross conduction event and a minimum conduction period cross conduction event. The SR drive circuit disables the synchronous rectifier in response to receiving the Disable SR signal.

An example apparatus (108A) includes: variable gain amplifier (VGA) circuitry (204) having: an input terminal, an output terminal, and a control terminal; and peak detector circuitry (222) having: an input terminal coupled to the output terminal of the VGA circuitry; an output terminal coupled to the control terminal of the VGA circuitry; the peak detector circuitry configured to: compare a voltage on the output (VOUT(P) - VOUT(N)) of the VGA circuitry to an offset voltage; and adjust, responsive to the comparison, a gain of the VGA circuitry.

This invention provides a long-life fiber Bragg grating temperature demodulator for space applications, comprising: a secondary power supply assembly, two mutually redundant signal processing and interface circuit boards, two mutually redundant light source drive circuit boards, two main and backup light source modules, two-channel secondary temperature control systems, and one detector circuit board. This invention is a fiber Bragg grating temperature demodulator based on SG-DBR swept-frequency laser demodulation technology. As a new generation of temperature measurement products, fiber Bragg grating temperature demodulators feature wide measurement range, flexible deployment, and light weight, making them ideal for applications requiring large-scale, multi-point temperature measurement of large, precision structures in spacecraft. To achieve multi-point temperature measurement on satellites, fiber Bragg grating temperature sensor networks can be deployed inside the satellite cabin and on antenna panels to monitor temperature changes in various parts of the satellite structure.

An integrated circuit package having integrated therein an array of acoustic to electrical transducers that produce analog audio sub-band signals, an analog detector circuit to produce for each sub-band a number of analog property signals, an analog to digital conversion circuit to digitize each of the analog property signals, and an encoder to produce for each sub-band a feature set that contains one or more features of a respective sub-band. Other aspects are also described and claimed.

An example apparatus (108A) includes: variable gain amplifier (VGA) circuitry (204) having: an input terminal, an output terminal, and a control terminal; and peak detector circuitry (222) having: an input terminal coupled to the output terminal of the VGA circuitry; an output terminal coupled to the control terminal of the VGA circuitry; the peak detector circuitry configured to: compare a voltage on the output (VOUT(P) - VOUT(N)) of the VGA circuitry to an offset voltage; and adjust, responsive to the comparison, a gain of the VGA circuitry.

Device comprising: a receive path for receiving, processing and outputting a receive radio frequency (RF) signal, wherein the receive path includes at least one low noise amplifier (LNA) and multiple signal nodes, and wherein the receive path is configurable to operate in multiple modes; at least one filter for filtering the receive RF signal;and at least one detector circuit to detect one or more levels occurring at one or more of the multiple signal nodes, wherein the device is configured to configure a sequence for the at least one LNA and the at least one filter, at least partially based on the one or more levels detected in the at least one detector circuit, wherein the device further comprises switching circuits connected to the receive path, wherein the switching circuits: in a first mode of the multiple modes are provided to cause the at least one detector circuit to detect the level of the received RF signal at an input of the at least one LNA via a first signal node of the multiple signal nodes;In a second mode of the several modes, the switching circuits are provided to cause the at least one detector circuit to detect the level of the received RF signal at an input of the at least one filter via a second signal node of the several signal nodes; and wherein in a third mode of the several modes, the switching circuits are provided to cause the at least one detector circuit to detect the level of the received RF signal at the input of the at least one LNA, wherein in the third mode the input of the at least one LNA is connected to an output of the at least one filter via a third signal node of the several signal nodes.

An example apparatus includes: variable gain amplifier (VGA) circuitry having: an input terminal, an output terminal, and a control terminal; and peak detector circuitry having: an input terminal coupled to the output terminal of the VGA circuitry; an output terminal coupled to the control terminal of the VGA circuitry; the peak detector circuitry configured to: compare a voltage on the output of the VGA circuitry to an offset voltage; and adjust, responsive to the comparison, a gain of the VGA circuitry.