953results about How to "Reduce access" patented technology

Valved ports for accessing blood vessels and other body lumens include a lock mechanism which locks the valve fully open when a needle or other access tube is placed into the port. The lock mechanism includes a latch typically comprising one or more laterally deflectable elements, such as a pair of opposed balls. The deflected elements are pushed outwardly by the needle to engage a recess in the port which locks the valve open until the needle is removed.

A system and method are disclosed for utilizing compression in database caches to facilitate access to database information. In contrast with applying compression to the database that is stored on disk, the present invention achieves performance advantages by using compression within the main memory database cache used by a database management system to manage data transfers to and from a physical database file stored on a storage system or stored on a networked attached device or node. The disclosed system and method thereby provide a significant technical advantage by increasing the effective database cache size. And this effective increase in database cache size can greatly enhance the operations-per-second capability of a database management system by reducing unnecessary disk or network accesses thereby reducing data access times.

Valved ports for accessing blood vessels and other body lumens include a lock mechanism which locks the valve fully open when a needle or other access tube is placed into the port. The lock mechanism includes a latch typically comprising one or more laterally deflectable elements, such as a pair of opposed balls. The deflected elements are pushed outwardly by the needle to engage a recess in the port which locks the valve open until the needle is removed.

A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instruction; and said data processing apparatus is operable over a period of time to access predetermined information corresponding to more instructions within said branch target cache than instructions it prefetches from said memory such that said accesses to said branch target cache develop an advance in said instruction stream with respect to accesses to said memory; and said prefetch unit is operable to access said data store and to determine if there is data corresponding to an instruction within said data store that indicates that said instruction specifies a branch operation that will be taken and will cause a change in instruction flow.

A method and apparatus for performing efficient interprocess communication (IPC) in a computer system. With this invention, a memory region called the IPC transfer region is shared among all processes of the system to enable more efficient IPC. The unique physical address of the region is mapped into a virtual address from each of the address spaces of the processes of the system. When one of the processes needs to transfer data to another of the processes, the first process stores arguments describing the data in the region using the virtual address in its address space that maps into the unique physical address. When the other or second process needs to receive the data, the second process reads the data from the second region using the virtual address in its memory space that maps into the unique physical address. With this invention, in most cases, control of the IPC transfer region occurs automatically without any kernel intervention.