Patents
Literature
Patsnap Copilot is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Patsnap Copilot

4996results about How to "Increase storage capacity" patented technology

Display apparatus

A display apparatus, that includes current driving type luminescent elements, has a driving system that takes the conduction types of TFTs to control the emission of the luminescent elements into consideration. In order to reduce driving voltage and improve display quality simultaneously, the arrangement is provided such that if the second TFT (30) which performs the "on-off" function of the current for the luminescent element (40) is of an N channel type, the potential of the common power supply line ("com") is lowered below the potential of the opposite electrode ("op") of the luminescent element (40) to obtain a higher gate voltage ("Vgcur"). In this case, if the first TFT (20) connected to the gate of the second TFT (30) is of a P channel type, when using the potential of the potential-holding electrode ("st") at the "on" state as a reference, potentials of the scanning signal ("Sgate") at the lower potential and the common power supply line ("com") are rendered of the same polarities with respect to this potential of the potential-holding electrode ("st"). Therefore, the potential of the image signal ("data") to turn "on" can be shifted within the range of the driving voltage in the display apparatus (1) in the direction to reduce resistances at the "on" states of the first TFT (20) and the second TFT (30) to reduce driving voltage and improve display quality.
Owner:INTELLECTUAL KEYSTONE TECH

Reducing the effects of noise in non-volatile memories through multiple reads

Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.
Owner:SANDISK TECH LLC

Polarization code and multi-bit even parity check code cascaded error correction coding method

The invention discloses a polarization code and multi-bit even parity check code cascaded error correction coding method. The method comprises the steps: a transmitting end encoder utilizes a multi-bit even parity check code as an outer code, and utilizes a polarization code as an inner code; a receiving end decoder decodes by utilizing a modified successive cancellation list (SCL) decoding algorithm. On the aspect of error correction performance, comparing with the prior art utilizing middle-short code length non-cascaded polarization codes of the SCL decoding algorithm, the polarization code and multi-bit even parity check code cascaded error correction coding method has the advantages that frame error rate performance of a system can be remarkably improved, and a maximum likelihood bound (ML Bound), which cannot be broken through by the SCL decoding algorithm, can be remarkably broken through. On the aspect of engineering realization, according to the polarization code and multi-bit even parity check code cascaded error correction coding method, the outer code utilizes the multi-bit even parity check code, which is simple to code; the modified SCL decoding algorithm is utilized to decode, bit decision and even parity check are combined to be carried out in a decoding process, and compared with the original SCL decoding algorithm, the method provided by the invention does not increase the decoding complexity, and facilitates the engineering realization.
Owner:HUAZHONG UNIV OF SCI & TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products