7 results about "Cvd graphene" patented technology

The application discloses an electromagnetic wave non-reciprocal transmission structure based on light-excited graphene and a transmission method thereof. The structure is composed of silicon rods with different widths placed on a silicon / silicon dioxide substrate, and large-area CVD graphene is transferred to the structure to form a graphene super surface structure. Due to the asymmetry of the structure and the excitation of the nonlinear Kerr effect, the transmission efficiency of electromagnetic waves is significantly related to the incident direction of signal light. By optimizing the structure parameters, the light-excited graphene super surface structure based on the light-excited graphene super surface structure shows a large positive and negative transmission ratio. The device structure is simple and compact, the required incident laser intensity is only 80kW / cm 2 , and is relatively easy to realize in experiments. By utilizing the optical adjustable function of graphene, the working frequency band of the non-reciprocal device can be effectively controlled, thereby flexibly realizing the optical isolation function.

The application discloses a heterojunction transistor with sub-nanometer channel length and sub-nanometer gate width and a preparation method. A PN junction heterojunction is constructed by using a single-layer CVD graphene and a single-layer CVD two-dimensional material. A vertical PN junction with a thickness less than 1 nm is used as a device channel, and the channel length is equal to the thickness of the heterojunction. A gate structure uses the edges of the graphene and the two-dimensional material layer as gate electrodes, and the gate width is equal to the thickness of the heterojunction, reaching sub-1 nm. The source electrode, the drain electrode and the gate electrode are separated into three independent terminals through gap etching. The Fermi energy level of the graphene is adjusted by the gate voltage, the barrier height of the PN junction is changed, and the switching control of the device is realized. The bottom silicon gate can also assist in the regulation to further optimize the setting range of the gate voltage. The application solves the problems of the short channel effect and the gate control of the silicon-based device, simplifies the preparation process, realizes wafer-level mass production, and meets the development needs of the ultra-miniaturization of integrated circuits.

The invention aims to provide a method capable of improving the chemical reaction activity of graphene. The method comprises the following steps: transferring CVD graphene growing on the surface of a copper foil to the surface of single crystal Ni (111) by adopting a PMMA (Polymethyl Methacrylate) film transfer method; fe atoms are inserted between graphene and single crystal Ni (111) by adopting an electron beam evaporation method. By changing the bearing substrate in direct contact with the graphene and changing the contact and interaction modes of the bearing substrate and the graphene, the chemical reaction activity of the graphene is further changed. Different from a traditional design and preparation mode of a substrate, a new intercalation metal is introduced into a graphene / metal film system, a ternary graphene / metal film system with an intercalation structure is formed, the operation method is simple, convenient and easy to implement, the cost is reasonable and controllable, and the concept is novel.

The application relates to a method for efficiently preparing CVD graphene powder. 3+ The method comprises the following steps: taking dendritic copper powder as a substrate, taking C2H2 as a carbon source, taking HNO3 or Fe as an etchant, first depositing an amorphous carbon layer on the surface of the dendritic copper powder in situ at a lower temperature, then increasing the temperature to convert the amorphous carbon into a high-quality graphene film on the surface of the dendritic copper powder in situ, then completely dissolving the copper in the dendritic copper composite powder which has grown graphene on the surface by the etchant, and finally obtaining the high-quality CVD graphene powder through filtration, deionized water washing and drying. The method can effectively prevent the fusion and growth of the dendritic copper powder at high temperature, maintain the initial high specific surface area of the dendritic copper powder, and realize efficient preparation of the CVD graphene powder.

The application discloses a graphene separation membrane, which comprises a support layer and a separation layer, and the separation layer is a double-layer graphene film with nano-pores. The application adopts a double-layer CVD graphene film as a separation layer material of a composite membrane, which better improves the problems of easy breakage, high requirement for raw materials and high cost of a single-layer CVD graphene film applied in a separation membrane field, and obviously improves the performance, and is suitable for a separation membrane of a thin film conductance method TOC analyzer. A preparation method of the graphene separation membrane is also disclosed, which prepares a double-layer graphene separation membrane by using a laminated transfer graphene film technology, avoids technical difficulties and material limitations of preparation of a large-area continuous double-layer and multi-layer CVD graphene film material, introduces high-density ordered nano-pores into the double-layer graphene film prepared by using a plasma etching method for the laminated transfer method, and guarantees the selectivity and permeability of the graphene separation membrane.

The application discloses a kind of electromagnetic protection graphene metal copper net and preparation method thereof, specifically related to electromagnetic field shielding technical field, the graphene metal copper net includes graphene metal copper net body, graphene metal copper net body is the diamond metal net structure formed by punching processing of graphene copper foil to punching machine, graphene copper foil is the graphene / metal copper composite material obtained after copper base material and graphene material are compounded, and it is prepared into metal foil structure after being laminated and being rolled by laminated rolling device.The graphene metal copper net provided by the application not only satisfies lightning protection ability and electromagnetic shielding performance integrated protection demand, but also realizes the lightweight of conventional lightning protection copper net under the premise of keeping the lightning protection effect unchanged, the preparation method of the application combines CVD graphene growth technology, laminated rolling composite technology and extension punching net-making technology, with the advantages of automation, high degree of integration, high production efficiency and stability, and low product cost.

The invention discloses a heterojunction transistor with sub-nanometer groove length and sub-nanometer gate width and a preparation method thereof, a PN junction heterojunction is constructed by single-layer CVD graphene and a single-layer CVD two-dimensional material, a vertical PN junction with sub-1nm thickness is used as a device channel, and the length of the channel is equal to the thickness of the heterojunction; the grid structure uses the graphene and the edge of the two-dimensional material layer as a grid electrode, and the grid width is equal to the thickness of the heterojunction and reaches sub-1 nm; a source electrode, a drain electrode and a grid electrode are separated into three independent terminals through gap etching, the Fermi level of graphene is adjusted through grid voltage, the barrier height of a PN junction is changed, and on-off control of the device is achieved. The bottom silicon gate can assist regulation and control to further optimize the setting range of the gate voltage. According to the invention, the problems of short channel effect and grid control of a silicon-based device are solved, the preparation process is simplified, wafer-level mass production is realized, and the development requirement of ultra-miniaturization of an integrated circuit is met.