30 results about "Loop stability" patented technology

The invention provides a permanent magnet synchronous motor rotating speed control method and system, and belongs to the technical field of motor control. The method comprises the following steps: firstly, constructing a discrete time mathematical model of a motor and an external source system comprising a lumped reference signal and lumped interference, and establishing a composite system model according to the discrete time mathematical model; then, constructing a dimensionality reduction observer to estimate an external source signal, and performing state and input transformation in combination with a regulator equation; thirdly, constructing a constraint set of the transformation system, and decomposing a state variable into a nominal component, a deterministic error component and an uncertain error component; a time-varying constraint tightening set is dynamically constructed according to the error, a model prediction control optimization problem with dynamic tightening constraint is solved online, and a nominal control quantity is obtained; and finally, combining the nominal control quantity and the estimated external source signal to synthesize an actual control voltage. According to the method, interference can be effectively suppressed, system security constraints are strictly ensured, recursion feasibility and closed-loop stability of control are ensured, and the dynamic response speed is increased.

The invention discloses a boost control circuit and control method based on current sampling, the boost control circuit comprises a boost conversion module, a current sampling module, a voltage sampling module and a control module, the input end of the current sampling module is connected with the current sampling end of the boost conversion module, and the output end of the current sampling module is connected with the first input end of the control module; the input end of the voltage sampling module is connected with the voltage output end of the boost conversion module, and the output end of the voltage sampling module is connected with the second input end of the control module; the output end of the control module is connected with the control end of the boost conversion module. According to the boost control circuit, through cooperative detection of the current sampling module and the voltage sampling module and in combination with a double-loop adjustment mechanism of the control module, the stability of a loop is improved, the control bandwidth is optimized, and therefore the situation that the dynamic performance is affected due to the stability requirement is avoided.

The invention provides a bus voltage regulation method, which comprises the following steps: S1, in the case of no overload, a DC / DC (Direct Current / Direct Current) outputs constant voltage, and a first bus voltage target value is set; s2, when the load is overloaded, the DC / DC outputs constant current, and a second bus voltage target value is set; s3, judging whether the second bus voltage target value is greater than the first bus voltage target value, if so, selecting the first bus voltage target value, otherwise, selecting the second bus voltage target value; and S4, based on the first bus voltage target value or the second bus voltage target value, multiplying the first bus voltage target value or the second bus voltage target value by a fixed coefficient to obtain a final bus voltage target value, through the method, the method can be suitable for bus voltage regulation under various load working conditions such as normal load, overload and derating, the bus voltage is more stable, and the loop stability is better.

The invention provides a power hardware-in-the-loop interface compensation method based on power amplifier parameter identification. Parameter identification is carried out on a power amplifier system, parameter information of a passive device in the power amplifier is estimated, and the robustness of the system to parameter changes is improved. Due to the existence of a filter in a power amplifier, deviation of actual power transmission and ideal power transmission characteristics is generally caused, and the amplitude and phase angle deviation caused by the filter is compensated through parameters identified in an interface method, so that the power transmission precision is improved, and the reliability of power hardware in the loop is improved. In addition, the compensated system is closer to an ideal system, is more suitable for power hardware in-loop stability analysis and verification, and particularly has remarkable advantages under the condition of parameter aging offset of the power amplifier.

The invention provides an FVF type LDO (Low Dropout Regulator) circuit. In the FVF type LDO circuit, the positive input end of an operational amplifier is coupled with a reference voltage, the negative input end and the power supply end of the operational amplifier are coupled with a circuit output voltage, and in the FVF module, a power tube is coupled between the circuit input voltage and the circuit output voltage. The control end of the source electrode following transistor is coupled with the output end of the operational amplifier, the source end of the source electrode following transistor is coupled with the negative input end of the operational amplifier, the control end of the power tube is a dominant pole, the voltage of the connection point of the power tube and the source electrode following transistor is the circuit output voltage, and the current source is coupled between the dominant pole and the ground. Compared with the mode that power input voltage is adopted to supply power to the operational amplifier, the direct influence of the power input voltage on the operational amplifier can be shielded, improvement of DC gain and loop stability is facilitated, in addition, the output impedance of the branch where the FVF module is located is reasonably designed, and the loop stability can be ensured within the wide load range.

This invention provides a method and system for controlling the speed of a permanent magnet synchronous motor, belonging to the field of motor control technology. The method first constructs a discrete-time mathematical model of the motor and an external system including lumped reference signals and lumped disturbances, and establishes a composite system model accordingly. Then, a dimension-reduced observer is constructed to estimate the external signals, and state and input transformations are performed in conjunction with regulator equations. Next, a constraint set for the transformed system is constructed, and the state variables are decomposed into nominal components, deterministic error components, and uncertain error components. Furthermore, a time-varying constraint compression set is dynamically constructed based on the errors, and an online model predictive control optimization problem with dynamically tightened constraints is solved to obtain the nominal control quantity. Finally, the nominal control quantity and the estimated external signals are combined to synthesize the actual control voltage. This invention effectively suppresses disturbances, strictly ensures system safety constraints, guarantees the recursive feasibility and closed-loop stability of the control, and improves the dynamic response speed.

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage VOFFSET as a function of load current to substantially cancel out variations in VOUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use VOFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage VOUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage VOUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

This invention discloses a novel Class-AB output buffer load compensation structure, belonging to the field of analog integrated circuits. It includes a feedforward output buffer module and a load compensation loop module. The on-chip compensation capacitor in the load compensation loop is multiplied by the loop gain under the action of the gain amplification stage, forming a very large equivalent load compensation capacitor. Simultaneously, a left-half-plane zero is introduced, thereby achieving the goal of ensuring loop stability under various load conditions without using a large external load compensation capacitor. This invention has the advantages of simple circuitry and ease of use, and is suitable for Class-AB output buffer designs with a wide load range.

The application discloses a phase-locked loop capable of realizing fast locking, comprising a waveform broadening frequency discriminator, a digital auxiliary phase discriminator, a charge pump, a filter, a VCO and a frequency divider; the application realizes greater gain by broadening the pulse width of UP or DN, and simultaneously, due to the proposed new locking mode, a new discrimination is added on the basis of the traditional size bandwidth: whether the phase error exceeds pi, the filter structure is different when the phase error exceeds pi, the loop stability does not need to be considered when the current is increased to realize greater bandwidth, so that greater current, higher upper limit and greater gain are realized on the basis of the original, simultaneously, due to the early entering of the phase tracking stage, the charging speed of the capacitor is accelerated, the establishment time is accelerated, in addition, the switching of the bandwidth and the switching of the resistance can realize the invariability of the damping coefficient, the loop stability is not affected, the robustness is better, and fast locking is realized under the condition of guaranteeing small bandwidth and good performance.

The invention discloses a fixed-time anti-interference control system and method for an eddy-current hybrid power system, and the method comprises the steps: obtaining a disturbance affine form nonlinear mathematical model of a turbine engine of the eddy-current hybrid power system through system identification, and designing a fixed-time disturbance observer to estimate the lumped interference of the system in real time; a feed-forward signal measurer is designed to measure and calculate a feed-forward quantity in real time, and a fixed-time anti-interference feed-forward composite controller is constructed based on a nonlinear backstepping method and a dynamic inverse method, so that accurate control of the rotating speed of a turbine engine in the eddy-current hybrid power system is realized. The system designs a virtual control quantity through a nonlinear backstepping method, and a controller adopts a non-smooth instruction filter and an interference and feed-forward compensation mechanism to realize effective compensation for the uncertainty of the system. The method has high control precision, good anti-interference capability and closed-loop stability, and is suitable for rotating speed control of the turbine engine in the eddy-current hybrid power system under complex working conditions.

This invention discloses an LDO circuit for improving loop stability, relating to electronic circuits, and proposes a solution to address the loop instability problem in existing technologies. An internal ESR compensation module is set up to generate a zero to compensate for the secondary pole of the power transistor's gate, and the output signal is input to the inverting input of the error amplifier through negative feedback. The buffer stage is configured with an adaptive load, which dynamically changes the gate impedance of the power transistor according to the load current. Its advantages include not requiring an external capacitor to provide a specific ESR value, and the output capacitor can be a low-cost, small-size low-ESR ceramic capacitor, reducing component specification limitations. Before the compensation zero appears, negative feedback ensures that the voltage across the added compensation resistor is equal, preventing current flow and thus avoiding DC offset, resulting in a more accurate output voltage. The power transistor gate impedance can be dynamically adjusted according to changes in load current, which is beneficial for achieving loop stability across the entire load range.

The invention relates to the technical field of radar speed measurement, and discloses a radar speed measurement method based on gain control, comprising the following steps: S1, system initialization and gain calibration: pre-testing loop stability; s2, signal transmitting and echo receiving: transmitting and receiving a dynamic gain control echo signal; s3, high-speed signal acquisition and synchronization: acquiring I / Q channel data; s4, Doppler processing and dynamic gain compensation: Doppler frequency is extracted; s5, Doppler peak value detection and speed calculation: detecting a target peak value, and calculating a target speed; s6, dynamic performance verification: carrying out a multi-target scene test and an anti-interference test; s7, boundary condition robustness test: carrying out extreme environment test and overload recovery test; and S8, calibrating and outputting data. Through real-time gain compensation of digital automatic gain control and robust Doppler processing, high-precision speed measurement can still be realized under the conditions of strong clutter, interference and rapid gain change, the stability is good, and the influence of the environment is small.

This invention discloses a method and system for event-triggered load frequency security control in multi-regional power systems. The key technical points are: addressing the problem that existing load frequency control methods generally assume continuous availability of communication links, making it difficult to maintain stable operation under DoS attack conditions, this invention models the system as a switching system when a DoS attack occurs and switches the control mode in real time based on whether the link is under DoS attack: when communication is normal, conventional learning control is executed to optimize frequency regulation performance; when an attack occurs, it switches to an anti-attack control mode, thereby maintaining closed-loop stability and suppressing frequency deviation and tie-line power fluctuations even when communication is disrupted, significantly improving system security; furthermore, this invention is based on the RL method, obtaining control strategies through online learning with the environment when the system model is unknown or parameters are uncertain, thereby minimizing control energy consumption and improving operational economy without relying on precise system dynamics.

This invention discloses a learning-based fault-tolerant control method and system for quantifiable performance of nonlinear systems, belonging to the field of automatic control technology. The method designs a learning-based fault-tolerant control algorithm that embeds an RBF network to compensate for fault dynamics when a fault occurs. Based on deterministic learning theory, an RBF network is constructed by setting neurons along a desired reference trajectory. Secondly, by analyzing the convergence characteristics of the learning-tolerant control system through sampled data, a detailed quantitative analysis of the learning accuracy and learning speed of the proposed learning-based fault-tolerant control method is performed, and calculation formulas for learning accuracy and learning speed are given. This invention establishes quantitative expressions for learning speed and learning accuracy through theoretical derivation, realizing quantitative analysis and pre-setting of fault-tolerant control performance, and achieving quantitative controllability of learning speed and approximation accuracy while ensuring the closed-loop stability of the system.

This invention relates to the field of earthquake data processing technology, specifically to a highly reliable power supply and data protection method and system for earthquake monitoring equipment. When the main power supply fails, it switches to a composite energy system consisting of a battery and a supercapacitor to ensure that critical data is not lost due to power interruption. The equipment then enters an emergency state, activating a dual-loop stability control mode: the fast loop analyzes the dynamic behavior parameters of the group submission cache write status to intelligently determine the stability of the group submission rhythm and adjust the write frequency accordingly; the slow loop monitors key indicators of the tail write status of segment files to accurately identify tail congestion risks and dynamically adjust the submission batch. Furthermore, the system continuously monitors key load indicators of the equipment, intelligently determines the sealing conflict window, and automatically triggers sealing optimization strategies when resource contention is detected. This method significantly improves the data reliability and system stability of earthquake monitoring equipment under extreme operating conditions, providing complete and accurate data support for earthquake early warning.

This invention discloses an adaptive capacitor-compensated FVF-type low-dropout linear regulator based on multiple feedback loops, belonging to the field of integrated circuit technology. The invention includes an output power transistor, a first feedback loop, and a second feedback loop. The input terminal of the first feedback loop is coupled to the output node, and the output terminal is coupled to the control terminal of the output power transistor, used to respond to changes in load current. The input terminal of the second feedback loop is coupled to the output node, and the output terminal is coupled to the first feedback loop. It includes an impedance element, which, together with the load capacitance at the output node, forms a zero-point generation network to generate zeros whose frequency varies with the load capacitance, thus compensating for the poles of the first feedback loop. This invention achieves loop stability without requiring large-value Miller compensation capacitors by introducing adaptive zeros associated with the load capacitance, significantly reducing chip area and improving loop bandwidth and transient response performance.

The invention provides an FVF type low dropout regulator. The FVF type low dropout linear regulator comprises a bias loop and a fast response loop, the fast response loop comprises a source electrode following transistor, a power tube, a transmission circuit and a buffer circuit, a first end of the power tube is coupled with a power supply input voltage, a second end of the power tube is coupled with a source end of the source electrode following transistor and a circuit output voltage, and the buffer circuit is coupled with the source electrode following transistor. The transmission circuit can transmit power supply disturbance to the input end of the buffer circuit, one part of voltage ripples at the control end of the power tube are generated by the power supply ripples through gate-source voltage, the other part of the voltage ripples are generated by the buffer circuit, and the polarities of the two parts of voltage ripples are opposite, so that the two parts of voltage ripples can be at least partially counteracted. Therefore, the influence of the power supply ripple on the output end of the circuit is reduced, and the circuit has better loop stability.

The application discloses a multi-region power system event-triggered load frequency safety control method and system, and the technical scheme points are as follows: in view of the problem that the existing load frequency control method generally assumes that the communication link is continuously available and is difficult to maintain stable operation under the condition of DoS attack, the system is modeled as a switching system when the DoS attack exists, and the control mode is switched in real time according to whether the link is subjected to the DoS attack: the conventional learning control is executed to optimize the frequency regulation performance when the communication is normal; the anti-attack control mode is switched to when the attack occurs, so that the closed-loop stability can be maintained and the frequency deviation and the tie-line power fluctuation can be inhibited under the condition that the communication is blocked, and the system safety is significantly improved; in addition, based on the RL method, the control strategy is obtained by online learning through interaction with the environment under the condition that the system model is unknown or the parameters are uncertain, so that the control energy minimization and the operation economy are realized without depending on the accurate system dynamics.

The invention discloses a stability guarantee and online performance optimization method of a mesh network control system, and relates to the technical field of wireless network control. The method comprises the following steps: firstly, establishing a switching system model considering any time-varying and fluctuating transmission time delay, wherein the switching system model is used for accurately describing the influence of fine-grained time delay on stability and control performance; by analyzing stability conditions under different candidate time delays in a long time domain formed by a plurality of control periods, a stabilization data flow model for guaranteeing stability is provided, and the network capacity capable of realizing loop stability can be maximized. The importance of information physical system sensitivity indication control data flow is designed by considering a switching system model, network configuration and an online physical state under any time delay. And finally, a priority-based scheduling strategy is adopted, network resources are efficiently utilized to improve the control performance of the whole system on the premise of guaranteeing the stability, and stability guarantee and online control performance optimization are realized.

The application provides an automatic gain control method based on an ADC architecture and a SERDES system, comprising obtaining a clock signal and a digital signal output by an analog-to-digital conversion module, determining a clock period and a clock period quantity according to the clock signal, determining a first accumulated value and a second accumulated value according to the digital signal, a first threshold value and a second threshold value, and determining a count accumulated value according to the first accumulated value and the second accumulated value, if the clock period quantity reaches a third threshold value, determining a current round amplitude error according to the count accumulated value and the clock period quantity, determining a current round gain value according to the current round amplitude error, a last round gain value and a bandwidth parameter, and adjusting an input signal of the analog-to-digital conversion module according to the current round gain value. The application completes amplitude error estimation in the SERDES system through extremely low power consumption and complexity, and balances amplitude adjustment speed and loop stability through setting of the bandwidth parameter.

The application discloses a multivariate process adaptive control method based on multi-source consistency gating, relates to the technical field of industrial control systems, and comprises the following contents: in-situ optical signals, power supply electrical parameters, cavity pressure and gas flow time are aligned and quality pre-inspected, and output measurement health score, health type label, working condition deviation index and calibration window available flag; constrained perturbation is applied to the selected actuator in the non-product calibration window and calibration acceptance is carried out, calibration data package and low-dimensional correction candidate are generated; based on the correction candidate gating update and small-step correction, a standby virtual sensor is constructed and weighted fusion is carried out according to the health degree, disturbance-free switching, amplitude limiting control and frozen rollback are realized; an audit chain is formed and compliance determination, back switching and maintenance exit are carried out. The scheme maintains closed-loop stability under optical link degradation or cross-condition, reduces shutdown calibration and misadjustment risk, and improves production continuity and traceability.

The application discloses a pre-oscillation stability monitoring active damper for grid-connected power electronic systems and belongs to the technical field of power electronics. The pre-oscillation stability monitoring active damper comprises a direct-current voltage control loop stability energy storage, a stability monitoring loop, a wide-frequency pulse disturbance injection through phase-locked synchronization, grid impedance and inverter impedance based on fundamental wave separation and FFT calculation, an activation signal generated by using an MPC criterion, a virtual resistance started according to the activation signal, and a closed-loop optimization dynamic adjustment of the virtual resistance to make the system stability margin approach a critical value. The application realizes pre-oscillation intervention, solves the problems of response delay, high energy consumption and poor compatibility of traditional schemes, and simulation shows that the harmonic suppression response time is less than or equal to 20 ms and THD is reduced to 0.57%.

The application discloses a kind of based on numerical range multi-converter system stability evaluation method.Method includes: whether the open loop stability condition is satisfied by the equivalent admittance matrix of the admittance matrix transfer function of the converter side of multi-converter system;The numerical range of the equivalent admittance matrix of the admittance matrix transfer function of the network side and the converter side of multi-converter system is established;When meeting the open loop stability condition, then whether the closed loop stability condition is satisfied by the numerical range of multi-converter system, if meeting, then evaluate multi-converter system stability.The application is based on numerical range analysis framework, without global modeling, can realize the fast evaluation of small signal stability of multi-converter system.The application shows stronger criterion applicability and engineering reliability in large-scale, high proportion converter access power system, provides more effective technical means and theoretical basis for the design, planning, operation and control of multi-converter power system.

This invention belongs to the field of signal synchronization technology in digital communication systems. It discloses a high-speed parallel bit synchronization loop design method based on FPGA. This invention adopts a collaborative design of parallel Farrow filter banks and grouped Gardner error detectors to significantly improve the throughput of bit synchronization loop calculation and overcome the limitation of FPGA clock rate on data processing. Through mean aggregation and k-fold phase error amortization mechanism, the multiple errors generated by parallel calculation are converged to a unified control word, which not only retains the efficiency of parallel architecture but also ensures loop stability. A parallel shift memory space and address pointer linkage mechanism is adopted, and the initial read position pointer is dynamically adjusted through feedback from a numerically controlled oscillator to achieve symbol phase deviation compensation without large-scale data copying. A 3*k depth parallel memory space is implemented through a shift register chain. With the multiplier multiplexing strategy, it is more friendly to hardware resources and easier to deploy in mainstream FPGA hardware.

The invention discloses a phase-locked loop circuit, a chip and electronic equipment. The circuit includes: a phase detection unit that compares a phase difference between a reference clock and a feedback clock to generate an error signal; the charge pump unit comprises a first charge pump and a second charge pump and is used for converting the error signal into a control current signal; the filtering unit is used for filtering the control current signal to generate a first control voltage signal; the signal scaling unit is used for carrying out amplitude scaling on the first control voltage signal so as to generate second control voltage signals with different amplitude ranges; the voltage-controlled oscillation unit generates an output clock signal according to the second control voltage signal; the frequency division unit performs frequency division on the output clock signal to generate a feedback clock signal. According to the invention, based on a double charge pump structure, on the premise that a loop transmission function is not changed, the same loop stability can be maintained, the physical size of the filter capacitor can be significantly reduced, and full-on-chip integration of the phase-locked loop is facilitated.

The present application belongs to the field of converter technology, and particularly relates to a switching DC converter control method with high response speed characteristics. The method of the present application mainly obtains a current signal by obtaining a voltage difference of a secondary filter, then compares a load feedback voltage with a reference signal to obtain an error signal, and compares the error signal with the current signal to generate a pulse signal for controlling the switching DC converter. The present application has the beneficial effect of obtaining high load switching response speed and high loop stability for a DC converter with a secondary or more filters.

The application discloses a dead time processing method and device of a converter and the converter. The method comprises the following steps: obtaining a change slope of a secondary side current for the first time after a main switch tube of the converter is turned off; obtaining a zero-crossing point moment of an excitation inductance current of a primary side of the converter based on the change slope of the secondary side current; obtaining a time difference between the zero-crossing point moment and a turn-off moment of a clamping tube of the converter; and determining a dead time of the primary side of the converter based on the time difference, wherein the dead time is a time period from the turn-off moment of the clamping tube to a turn-on moment of the main switch tube of the converter. The application solves the technical problems of poor loop stability of the converter caused by sudden change of the dead time when the converter is converted from a DCM mode to a CCM mode and the main switch tube failing to be turned on when the voltage at a switching node is at a lowest point.

The present application discloses a fast-response switch power supply control circuit and a control method thereof. A triangular wave signal associated with inductor current information is obtained by a triangular wave generation circuit; the triangular wave signal is calculated with an error compensation signal by the capacitor circuit to obtain a first compensation signal; a comparator compares the first compensation signal with an output voltage feedback signal to obtain a comparison result to control the turning-on of the power switch transistor. The present application has the beneficial effects of good loop stability and fast dynamic response of the system without requiring a sampling circuit to sample the inductor current information in the case of using a relatively simple circuit.

The application discloses a three-loop low-dropout linear voltage regulator circuit based on double power tubes, relates to the technical field of power management chips, and solves the mutual trade-off problem of loop stability, loop bandwidth and output transient response of a low-dropout linear voltage regulator without an off-chip capacitor in the prior art; the circuit comprises a power supply rejection enhancement module, a first loop module, a second loop module, a third loop module and a double power tube module, the double power tube module is used for adjusting an output end voltage according to the first loop module, the second loop module, the third loop module and the power supply rejection enhancement module, and determining the output of the voltage regulator circuit; the system's load capacity is improved, a large output capacitor or a large compensation capacitor is not needed, and the problem of stability and loop bandwidth can also be adaptively solved.

The present application belongs to the technical field of analog integrated circuit, and particularly relates to a ring oscillator circuit for a multiphase Buck converter. The present application proposes a new ring oscillator circuit to solve the problem that when the Buck converter needs to change the working phase, the traditional ring oscillator cannot keep the uniform phase difference, resulting in the increase of the output ripple of the multiphase Buck converter and the deterioration of the loop stability. The ring oscillator circuit is composed of a logic control module and a ring oscillator module, and the oscillator module is composed of a differential operational amplifier unit and a multiplexer (MUX). The present application can realize the adaptive uniform phase difference of the output clock according to the number of phases when the phase is cut, and solve the problem of the non-uniform phase difference of the output clock caused by the traditional circuit.