3661 results about "Simple circuit" patented technology

Roughly described, a phase-change memory such as a chalcogenide-based memory is programmed optically and read electrically. No complex electrical circuits are required for programming the cells. On the other hand, this memory can be read by electrical circuitry directly. The read out speed is much faster than for optical disks, and integrated circuit chips made this way are more compatible with other electrical circuits than are optical disks. Thus memories according to the invention can have simple, low power-consuming, electrical circuits, and do not require slow and power-hungry disk drives for reading. The invention therefore provides a unique low power, fast read/write memory with simple electrical circuits.

A protection circuit is provided for protecting a secondary battery from overcharging and excessive discharge current by a simple circuit. The protection circuit is provided with a connection terminal (T3) for connecting the secondary battery (6); a connection terminal (T1) for connecting a charging device for charging the secondary battery (6) and/or a load device driven by a discharge current from the secondary battery (6); a bimetal switch (SW1) that is provided between the connection terminals (T1, T3) and turned off in the case of exceeding a specified temperature set beforehand; a heater (R2) for heating the bimetal switch (SW1); and an integrated circuit (IC1) for turning the bimetal switch (SW1) off by causing the heater (R2) to generate heat if a voltage applied to the connection terminal (T3) by the secondary battery (6) exceeds a preset reference voltage.

A current resonant DC-DC converter of multi-output type is provided which comprises an output-regulatory MOS-FET 40 connected between a secondary winding 5c of a transformer 5 and a smoothing capacitor 16 in a second rectifying smoother 17, and an output control circuit 41 for controlling the on-off operation of output-regulatory MOS-FET 40 based on voltage V_O2 from smoothing capacitor 16 in second rectifying smoother 17. By turning the on-off operation of output-regulatory MOS-FET 40 in synchronization with switching frequency of first or second MOS-FETs 1, 2, an ideal cross regulation among respective DC outputs can be obtained, providing the inexpensive converter with simple circuit alteration capable of producing highly stable DC outputs with high power conversion efficiency, high accuracy and less power conversion loss.

The invention provides a dynamic interconnected control system and a control method for a solar battery pack, which comprises a plurality of MOS switch units, a connection terminal array and a control unit, wherein MOS switches are connected in series to form an array; each electric node of the MOS switch array is connected with a corresponding node of the connection terminal; the MOS switches are electrically connected with a control unit; and the control unit controls switch-on/switch-off of the MOS switches according to the state of the solar battery unit connected with the connection terminal array. The method comprises the following steps of: connecting a plurality of MOS switch units in series; connecting each solar battery unit and an MOS switch in parallel and electrically connecting the solar battery unit and the control unit; using the control unit to monitor the state of each solar battery unit and controlling the switch-on/switch-off of the MOS switches according to the state of the solar battery unit. The dynamic interconnected control system and the control method for the solar battery pack provided by the invention solve the problem that the entire system is affected when a single solar battery unit fails by using a very simple circuit structure.

Inductive position sensors and circuit configurations are disclosed for the measurement of linear, rotary, or curved position along a motion axis. The simplified sensor structures combine one or two parts of a movable core element with a simple planar substrate having first and second inductances connected in series. Movement of the core element in parallel to the planar substrate causing the impedance of at least one of the inductances to change. Simple circuit configurations are taught by which the impedance change is converted into a useful output signal that indicates position along the motion axis.

Systems and methods for providing a buck-boost converter with an improved efficiency are disclosed. The buck-boost converter disclosed operates in 5 different modes, namely in buck mode, half frequency buck mode, half frequency buck-boost mode, half frequency boost mode, and in boost mode. In half frequency buck mode, buck-boost mode, and in half frequency boost mode the switching frequency is halved compared to the switching frequency of buck or boost mode. A simple circuit implementation by adding two offset voltages in ramp signals or PWM comparators enables to halve the switching frequency if required.

Response of a variable frequency switching constant on-time or adaptive on-time controlled power converter to a large step-up or step-down change in load is improved with a simple circuit that detects magnitude and polarity of a change in output voltage and initiates, extends or terminates conduction of power pulses from an input source through said power converter. Both the amplitude and duration of undershoot or overshoot of the transient response are reduced or, alternatively, the capacitance of an output filter may be significantly reduced and still provide comparable transient performance. The fast adaptive on-time control is applicable to multi-phase power converters using phase managers or one or more phase-locked loops for interleaving of power pulses.

The invention discloses a relay fault detecting circuit belonging to the field of relays and comprising a power supply module which can provide a low-voltage DC power supply and a high-voltage AC power supply, a relay module, a control module and a signal feedback module, wherein the control module and the relay module are respectively provided with the low-voltage DC power supply by the power supply module; the control module is connected with the control end of the relay module, and the connecting and disconnecting of the switching end of the relay module is controlled by a driving control signal of the control module; one end of the switching end of the relay module is connected with the output end of the high-voltage AC power supply of the power supply module, and the other end is a load connecting end which is connected with the control module through a signal feedback circuit; and the control module is used for detecting and controlling the fault of the relay module through comparing the driving control signal with a feedback signal. The invention can judge the fault that a relay cannot be connected or disconnected, can simultaneously detect faults of a plurality of relays and has simple circuit design and convenient use.

A semiconductor integrated circuit device has a MISFET and a body biasing circuit. The MISFET has a source electrode and a drain electrode of a first conductivity type and a gate electrode, and the MISFET is formed in a well of a second conductivity type. The body biasing circuit generates a voltage in the well by passing a prescribed current in a forward direction into a diode which is formed from the well and the source electrode of the MISFET.

The invention discloses a device and a method for measuring square wave modulated photoelectric volume pulse wave. A microprocessor outputs square waves which have different frequencies and form a double ratio relationship; the square waves drive at least two light-emitting diodes; the light from the light-emitting diodes are received by a photosensitive device after passing through tested finger; the photosensitive device converts the light into a voltage signal; the voltage signal is converted into a predefined amplitude value voltage signal by a current/voltage conversion amplifier; an analogue-to-digital converter converts the predefined amplitude value voltage signal into a digital signal; the microprocessor processes the digital signal to obtain photoelectric volume pulse wave and valley value and peak value thereof, and gets spectrum value by the valley value and the peak value. The measurement method comprises the following steps of: separating the digital signal to obtain the photoelectric volume pulse wave and removing interference of background light by the microprocessor; getting the valley value and the peak value according to the photoelectric volume pulse wave; and calculating the valley value and the peak value to obtain light absorbance difference, and obtaining the spectrum value by the light absorbance difference. The accurate measurement, simple circuit and low cost are realized.

The invention provides a shifting register unit and a driving method thereof, a shifting register and a display device. The shifting register unit comprises a grid driving signal output end, a clock signal end, a pull-up transistor, a pull-down transistor, a pull-down node control module and a pull-up node control module, wherein the pull-down node control module controls the potential of a pull-down node to be a low potential in an input stage, controls shutoff of the pull-down transistor in an output stage, and controls turn-on of the pull-down transistor in a resetting stage, so that the grid driving signal output end outputs a low level; the pull-up node control module controls the potential of a pull-up node to be pulled up to a high potential in an input stage, and controls turn-on of the pull-up transistor in an output stage, so that the grid driving signal output end outputs a clock signal, controls the potential of the pull-up node to be pulled down to a low level in a resetting stage, and controls shutoff of the pull-up transistor in a remaining stage. By adopting a simple circuit structure, a two-way scanning function is realized so as to reduce the power consumption.

The invention relates to a configurable frequency synthesis circuit based on a delay locked loop. The circuit comprises the delay locked loop, a frequency synthesizer and a configuring SRAM, wherein, the delay locked loop consists of a phase discriminator, a controller and a variable delay chain; and the frequency synthesizer consists of a frequency doubling synthesizer and a frequency division synthesizer. The phase discriminator receives a reference clock and a feedback clock and outputs comparison signals and locking signals after phase demodulation comparison; the comparison signals and the locking signals are processed by the controller, and the controller outputs control voltage then in order to enable the variable delay chain to generate N phase clocks that are output to the frequency synthesizer; and the frequency doubling synthesizer and the frequency division synthesizer enable the set/reset time of a R/S trigger in the frequency doubling synthesizer to generate frequency doubling clock signals under the control of the configuring SRAM, and lead the set/reset time of the R/S trigger in the frequency division synthesizer to generate frequency division clock signals. The configurable frequency synthesis circuit has simple circuit organization, flexibly changes a frequency synthesis coefficient by changing the code flow value in the embedded configuring SRAM so as to obtain a frequency division coefficient and a frequency doubling coefficient as required, and can be applied to a field programmable logic array.

In a recordable optical disc apparatus, the efficiency of the work necessary for optimizing the write pulse condition (write strategy) is improved and the read compatibility among drive units is ensured by a minimum addition of circuitry. An edge shift amount or a read signal and a binarized result are stored in an external memory as digital data and are later processed by analysis software in a host PC. The write pulse shape and power conditions can be optimized to individual optical disc media in a short time by means of a simple circuit. Further, by optimizing the write pulse shape and power condition in view of the PRML class or the difference in NA of the head, any deterioration of read compatibility can be avoided.

A battery remaining capacity calculating method, a battery remaining capacity calculating device, and a battery remaining capacity calculating program that make it possible to estimate the remaining capacity of a secondary battery with high accuracy using a relatively simple circuit configuration. An output voltage value of the secondary battery is measured, a use mode of the secondary battery is divided into a high consumption mode in which the output voltage value is not lower than a threshold value and a low consumption mode in which the output voltage value is lower than the threshold value, a remaining capacity in the low consumption mode is calculated on a basis of a predetermined reference voltage curve as a discharge characteristic of the secondary battery and the output voltage value, and a remaining capacity in the high consumption mode is calculated supposing that there is little change in the remaining capacity at a time of change from the low consumption mode to the high consumption mode. In the high consumption mode, the remaining capacity may be calculated on a basis of a reference remaining capacity as a remaining capacity before the use mode change, a start voltage as an output voltage at a time of a start of the high consumption mode, a predetermined cutoff voltage of the secondary battery, and the output voltage value.

The present invention relates to an automatic balance charging device for charging series storage battery, which is arranged on each battery of the series storage battery one to one. The balance charging device comprises an accurate voltage balance current shunt [1] and a limiting fuse [2] in series. The present invention enables the battery of the series storage battery to obtain balance charging in long term automatically, thereby greatly prolonging the real service life of the storage battery. The present invention is characterized by simple circuit, small volume, low cost and good using effect, thereby being applicable to various series storage battery which can automatically solve the balance charging problem without any measures.

The invention discloses an automatic cutting control system and an automatic cutting control method for a coal cutter. The control system comprises a controller, a data storage device, a working condition detection apparatus for the coal cutter and a control host. The working condition detection apparatus for the coal cutter comprises a walking displacement detection unit, an angle detection unit one for detecting the swing angle of a right rocker arm, an angle detection unit two for detecting the inclination angle of a working face, an angle detection unit three for detecting the swing angle of a left rocker arm, and an angle detection unit four for detecting the upward or downward angle of the coal cutter. A left height adjustment oil cylinder and a right height adjustment oil cylinder are both controlled by the controller. The control method comprises the steps of: 1) learning and memorizing the cutting trace of the currently working coal seam; 2) accomplishing the automatic coal cutting according to the memorized trace, and adjusting the memorized trace in real time; 3) repeating step 2) until all the exploration processes of the currently working coal seal is finished. The system of the invention is advantageous by a simple circuit, a reasonable design, a convenient control method, and good application effect, and can realize the automatic cutting control of the coal cutter.

There is disposed a TFT for detecting characteristic having the same characteristic as a pixel TFT disposed at a pixel. The TFT for detecting characteristic detects a gate on voltage for driving the pixel TFT. The TFT for detecting characteristic is driven so as to agree with the pixel TFT in a period of the on state. This provides a display device that is capable of driving the pixel TFT at its optimum driving voltage with a simple circuit configuration, even when the characteristic of the pixel TFT is subjected to temperature change, aged change, and individual variations.

A protective circuit for a secondary battery pack advantageously having a simple circuit configuration while maintaining the safety of banks in the circuit. Each protective circuit has banks adapted to be charged or to discharge voltage, each bank being coupled to a controller that senses the charging or discharging voltage of the bank and outputs a predetermined value if overcharging or over-discharging is sensed. A level shifter is adapted to shift the voltage output from the controller to an adjusted voltage approximately equal to the voltage output from one of the other controllers. A switching means controls the stopping of charging or discharging of the banks.

The invention discloses a 10G single-fiber bidirectional optical module, which comprises a burst laser driver, a burst light power indicator, a microcontroller, a single-fiber bidirectional optical device, an avalanche photoelectric diode bias control circuit, a limiting amplifier, a receiving end light power monitor and an SFP+ connector, wherein the microcontroller is mainly used for controlling the burst laser driver and the limiting amplifier; the single-fiber bidirectional optical device is connected between the burst laser driver and the limiting amplifier to realize conversion between electrical signals and light signals; and the avalanche photoelectric diode bias control circuit supplies a high bias voltage to a receiving end avalanche photoelectric diode and performs voltage compensation on the receiving end avalanche photoelectric diode according to the temperature property. The 10G single-fiber bidirectional optical module has the advantages of low design cost, simple circuit design and capability of meeting the requirement of a 10G EPON ONU symmetrical scheme.

The invention discloses an ASIP based on an extensible processor architecture and a realizing method thereof, which mainly solve the problem of high circuit complexity and large resource consumption in the prior art. Aiming at the extensible processor architecture after optimization, the invention adopts a five-level-pipeline realizing method, and adopts a data orientation technology and a branch non-execution strategy to solve data hazards and control hazards in pipeline treatment respectively. The ASIP comprises an instruction fetch unit, a decoding unit, an execution unit, a memory access unit, a write-back unit, a pipeline control unit, a timer and an interrupt controller. According to the ASIP and the method, the characteristics of a pipeline processor and an FPGA (field-programmable gate array) are considered sufficiently, the pipeline structure is partitioned reasonably, and the hardware resources of the FPGA are utilized to the utmost extent; and the ASIP and the method have the advantages of simple circuit design, low resource consumption, high processor performance and low power consumption, and are highly suitable for large-scale parallel processing.