453 results about "Limiting amplifier" patented technology

The present disclosure relates to a high-speed and / or power-saving bi-directional transceiver. The transceiver generally includes a (burst) laser driver; an output power monitoring and indicating circuit; control logic (e.g., a microcontroller unit); bi-directional optics; a photodiode bias control circuit; a limiting amplifier; and a receiver optical power monitoring circuit. Optionally, the present transceiver includes a small form factor pluggable (SFP+) connector housing. In addition, the power-saving bi-directional transceiver generally includes a transmitter (TX) energy-saving circuit, a TX burst holding circuit, a receiver (RX) energy-saving circuit, a RX continuous holding circuit and the control logic.

The invention discloses an optical line terminal (OLT) optical module, which comprises an optical device, a passive optical network (PON) data signal driver, a PON data signal amplitude limiting amplifier and an optical time domain reflectometer (OTDR) data processing module, wherein the optical device comprises a wavelength division multiplexer (WDM). The OLT optical module can simplify a network wiring structure, and compared with the prior art, reduces OTDR equipment and the WDM as well as the wiring difficulties and network cost of a PON system.

The invention discloses a 10G single-fiber bidirectional optical module, which comprises a burst laser driver, a burst light power indicator, a microcontroller, a single-fiber bidirectional optical device, an avalanche photoelectric diode bias control circuit, a limiting amplifier, a receiving end light power monitor and an SFP+ connector, wherein the microcontroller is mainly used for controlling the burst laser driver and the limiting amplifier; the single-fiber bidirectional optical device is connected between the burst laser driver and the limiting amplifier to realize conversion between electrical signals and light signals; and the avalanche photoelectric diode bias control circuit supplies a high bias voltage to a receiving end avalanche photoelectric diode and performs voltage compensation on the receiving end avalanche photoelectric diode according to the temperature property. The 10G single-fiber bidirectional optical module has the advantages of low design cost, simple circuit design and capability of meeting the requirement of a 10G EPON ONU symmetrical scheme.

A field effect transistor (FET) driver circuit includes an error amplifier for providing a FET control signal and a current limiting amplifier for preventing excessive current flow through the FET. The current limiting amplifier generates an overcurrent signal when an excessive current is detected. In response to the overcurrent signal, a voltage control circuit adjusts the voltage at the output of the error amplifier to turn off the FET. Meanwhile, a pulldown circuit at an input of the error amplifier adjusts the voltage provided to that input to cause the error amplifier to provide an output voltage that also tends to turn off the FET. If a buffer is present at that input to the error amplifier, a second pulldown circuit is placed at the input to the buffer to maintain a stable unity gain across the buffer.

A radar warning receiver is implemented in low cost integrated circuit form utilizing only one analog component, namely a limiting amplifier. By taking the output of the limiting amplifier and utilizing monobit sampling of the output it has been found that one can provide an integrated circuit single chip radar warning receiver using delay correlation to extract frequency, amplitude and modulation type from signals at or below the noise level.

The invention discloses an amplitude detection circuit with a direct current offset elimination function. The amplitude detection circuit has a differential structure, and consists of a direct current offset elimination circuit, an amplitude limiting amplification circuit, an amplitude detection circuit, a current addition circuit and a filtering circuit, wherein the direct current offset elimination circuit comprises a plurality of direct current offset suppressors with a low-pass filtering function; the amplitude limiting amplification circuit comprises a plurality of amplitude limiting amplifiers; and the amplitude detection circuit comprises a plurality of amplitude detection units. A differential radio frequency signal is amplified to be saturated by a plurality of stages of cascaded amplitude limiting amplifiers, the output of each stage of amplitude limiting amplifier is detected by the amplitude detection units, output detected amplitude values are transmitted to the current addition circuit for addition, and the sum is filtered by the low-pass filtering circuit to obtain output voltage related to the amplitude of the input signal. The circuit can be adapted to the requirements of high monolithic integration level of a radio frequency chip, and is applied to a high-integration level zero-intermediate frequency receiver with the requirement of signal amplitude detection.

An optical distributor includes an optical-signal input port, a light receiving device, a light emitting device, a light splitter, and optical signal output ports. The light receiving device converts an optical light signal input to the optical-signal input port into an electric signal. The light emitting device converts the electric signal into an optical signal. The optical splitter 14 splits the converted optical signal into two optical signals. The optical-signal output ports output the split optical signals. The light receiving device includes a light receiving element, a pre-amplifier, and a limiting amplifier. The light emitting device includes a light-source drive element and a light emitting element.

A modulated carrier signal is produced from a phase modulation signal in a phase locked loop in a polar modulator. This carrier signal is converted via a limiting amplifier to a square-wave signal, which is supplied to an amplifier. At the same time, an amplitude modulation signal at one input is connected to a control input of a controllable current source. The controllable current source is designed to emit a supply current at a current output as a function of the amplitude modulation signal at the control input. The current output of the controllable current source is connected to a supply input of the amplifier. The supply current for the amplifier is thus modulated on the basis of the amplitude information to be transmitted. The processing of the amplitude information within the current domain makes it possible to produce the polar modulator according to the invention as an integrated circuit, using CMOS technology.

An optical transceiver having an integrated optical time domain reflectometer monitoring unit and methods for using the same are disclosed. The disclosure relates to an optical transceiver comprising an optical device comprising a wavelength division multiplexing system (WDM), a data signal driver, a data signal limiting amplifier, and an optical time domain reflectometer (OTDR) data processing module. Furthermore, the optical transceiver is particularly advantageous in an optical line terminal (OLT) and / or a passive optical network (PON). The integrated OTDR data processing module can protect the optical transceiver, ensure successful monitoring data, simplify network wiring and decrease system and network costs by decreasing the number of OTDR modules and WDM units.

The invention discloses a circuit for protecting an APD receiver. The circuit comprises the APD receiver, wherein the bias input end of the APD receiver is grounded through a first decoupling capacitor and a second decoupling capacitor, the bias input end of the APD receiver is connected with a first output end of a mirror image circuit, the input end of the mirror image circuit is connected with the output end of a boost control circuit, and the input end of the boost control circuit is connected with a microprocessor; the second output end of the mirror image circuit is grounded through a first resistor and meanwhile connected to the microprocessor; the microprocessor is connected with a signal losing LOS end of a limiting amplifier which is connected with a trans-impedance amplifier (TIA), the TIA is connected with the output end of the APD receiver, a second resistor is connected between the bias input end of the APD receiver and the first output end of the mirror image circuit, and the resistance value of the second resistor ranges from 10 K ohm to 100 K ohm. Through the circuit, an APD can be effectively protected against damage, the risk that a module loses efficacy is reduced, and the service life of the optical module is prolonged.

The invention discloses a switchable various three-phase chaotic combined circuit, comprising a first to a third anti-phase integrators, an anti-phase limiting amplifie, a first to a fourth anti-phase amplifiers, an anti-phase plus amplifier and a switch-able circuit. The invention is used as follows: among four groups of jumper devices of the switchable circuit, a first jumper device, a fifth jumper device, a ninth jumper device and a thirteenth jumper device are communicated to form an output double-vortex chaotic attractor circuit; among the four groups of jumper devices, a second jumper device, a sixth jumper device, a tenth jumper device and a fourteenth jumper device are communicated to form an output single-vortex chaotic attractor circuit; among the four groups of jumper devices, a third jumper device, a seventh jumper device, an eleventh jumper device and a fifteenth jumper device are communicated to form an output single-sealed chaotic attractor circuit; and among the four groups of jumper devices, the fourth jumper device, the eighth jumper device, the twelfth jumper device and the sixteenth jumper device are communicated to form an output double-vortex chaotic attractor circuit.

An apparatus for detecting an arc fault. The apparatus comprises a current detector for detecting the amount of change of current flowing on the wire and generating a signal proportional to the amount of change; a signal transformer for passing a high frequency component of the signal outputted from the current detector, and limiting a level of the signal not to exceed a fixed signal level; a first level limit amplifier for amplifying a signal outputted from the signal transformer so as to limit the level of the outputted signal; a signal level detector for determining whether a input signal exceeds a fixed first voltage and generating a detection signal; a pulse generator for transforming the detection signal outputted from the signal level detector into a form of normalized pulse; a first arc determination unit for counting a pulse signal outputted from the pulse generator for a predetermined time, determining whether the arc has been occurred and generating an arc detection signal; and a circuit breaker for breaking the conductive wire when the are detection signal is generated.

The invention relates to the field of flow detection and provides an anti-strong fixed interference digital signal processing system of a vortex flowmeter, which comprises a vortex flow sensor, a charge amplifier, a passive low pass filter, a limiting amplifier, an active low pass filter, a voltage follower, a power supply module, a DSP chip, an LCD module, a keyboard module, a communication module, an EEPROM and an active crystal oscillator. The system processes the output signal of the vortex flow sensor by using a method of notch filtering and FFT-based power spectrum analysis and carries out spectral calibration, acceleration algorithm, limiting filtering and average treatment after obtaining the frequency of the vortex signal so as to eliminate the influences of strong fixed interference and obtain the value of the frequency of the vortex signal quickly and accurately.

A transimpedance amplifier (TIA) circuit usable for burst mode communications is provided. The TIA circuit includes a TIA stage, a limiter-amplifier, and a DC restoration loop. The invention overcomes problems of the prior art relating to burst communications, such as a DC level in the output signal which can change from burst to burst and a duty-cycle distortion in large signals. This is achieved by using a DC restoration loop that ensures achieving zero DC potential within variable acquisition periods.

The present invention discloses an optical module of an in-band pass through monitoring signal based on amplitude modulation, belonging to the field of communication technology. The optical module comprises a low speed baseband amplitude modulation circuit, a laser driving circuit, a laser, an electro-absorption signal modulation circuit, an electro-absorption modulator, an avalanche photodiode, a transconductance amplifier, an amplitude limiting amplifier, a mirror current circuit, and a low-frequency demodulation circuit. Compared with a conventional optical module, according to the optical module of the invention, a monitoring signal is loaded to the envelope of a bearing service signal through amplitude modulation and shares cable and channel resources with a bearing service signal, the channel resource is saved, the monitoring signal of the pass through is unrelated to a bearing service signal protocol, and the use flexibility is high. Since a low speed baseband signal amplitude modulation and demodulation unit is integrated in the optical module, the additional adding of an optical function unit is not needed, the pass through of the monitoring signal can be realized, and the optical module is a most cost-effective solution for an application scene with the need of monitoring signal transmission.

The present invention provides an equalizer filter for compensating a received distorted signal for frequency dependent signal modifications introduced by a transmission channel, the received signal having an amplitude. The filter comprises at least one amplifying compensation stage having a gain and a saturation level, at least one limiting amplifier, and gain control means for controlling the gain of the at least one amplifying compensation stage, the gain control means comprising at least one comparator circuit comparing filtered input and output signals of the limiting amplifier, the at least one comparator circuit comprising a bias current source. The bias current source is adapted to deliver a variable current.

The invention relates to the technical field of optical fiber communication, in particular to an optical fiber transceiver module based on plastic fiber and a plastic optical fiber communication system. The optical fiber transceiver module comprises an optical receiver and an optical sender, wherein the optical sender comprises an optical sending module for sending optical signals with the wavelengths being in a visible optical band and an optical sending module driver for driving the optical sending module to light; the optical receiver comprises an optical receiving module for converting input optical signals with the wavelengths being in the visible optical band into electric signals and a limiting amplifier for limiting and amplifying the electric signals output by the optical receiving module. The invention adopts the optical sending module with the working wavelength being in the visible optical band and a photoelectric detector with large detection area so that the optical fiber transceiver module can be applied to the plastic optical fiber communication.

The invention discloses a nonlinear amplification-retransmission optimal power allocation method. The method comprises the following steps: an ideal amplitude-limiting amplifier model is constructed into a linear model with a Gaussian distortion noise option by using a linearized theory; according to the linear model, the chain equivalent single-to-noise rate of each nonlinear relay, devoted to a target receiver, is calculated; in order to obtain the optimal signal-to-noise rate performance, a maximum-combination-ratio receiver which is capable of realizing the nonlinear distortion is also designed; then, an optimal relay power allocation mathematical model is built, although the optimal power allocation problem is not a convex problem is found by analyzing a curve structure of signal to noise rate and power, the optimal relay power allocation problem can be converted into a convex optimization problem by limiting the maximum emission power; and finally, an optimal power allocation scheme is provided by utilizing a lagrangian multiplier method. A theoretical analysis and simulation result indicates that the method disclosed by the invention is superior to an optimal power allocation algorithm has no sense to nonlinear distortion, and has the capability of effectively improving the system capacity.

The invention discloses a dual-rate optical signal receiving device, which comprises a dual-rate optical receiving component, a dual-rate limiting amplifier circuit unit, and a data shunt unit. The dual-rate optical receiving component also comprises an optical detector and a dual-rate transimpedance amplifier; the dual-rate limiting amplifier circuit unit also comprises a dual-rate limiting amplifier; and the data shunt unit also comprises a 1:2 data fan-out device and a low-pass filter circuit. Due to the adoption of the technical scheme, through two optical signal receiving circuits formed by time division multiplexing on data at different rates, the received data is divided into two data channels at different rates through a data shunt device. Therefore, an easily realized physical layer solution is provided for the dual-rate time division multiplexed data.

The invention discloses a high-speed CMOS monolithically integrated optical receiver with full bandwidth single-ended-to-differential, comprising a high bandwidth adjustment type cascode transimpedance amplifier used for converting a current signal output by a photoelectric detector into a voltage signal and preliminarily amplifying the voltage signal; a single-ended-to-differential device provided with a negative capacitance circuit and used for achieving single-ended-to-differential conversion and increasing a bandwidth and an amplified voltage signal; a DC offset eliminating unit used for eliminating a DC offset of an interleaved active feedback limiting amplifier caused by an unbalanced signal output by the single-ended-to-differential device and ensuring a uniform common mode level for the interleaved active feedback limiting amplifier; the interleaved active feedback limiting amplifier, used for amplifying the voltage signal output by the high bandwidth adjustment type cascode transimpedance amplifier to a voltage level required by a digital processing unit; and an output buffer stage used for providing driving ability. While improving the circuit gain, the high-speed CMOS monolithically integrated optical receiver disclosed by the invention is used for expanding the working bandwidth and overcoming the shortcomings in the prior art.

The invention discloses a burst light signal receiving apparatus which comprises: a light receiving assembly and an amplitude limit amplifier circuit unit. The light receiving assembly further comprises: a photo-detector, a transimpedance amplifier, a direct current reservation circuit 1 and a direct current offset circuit. The amplitude limit amplifier circuit unit further comprises: a group of alternating current coupling capacitors, an amplitude limit amplifier and a direct current reservation circuit 2. By using a technical scheme of the invention, the input burst light signals in a certain dynamic scope can be returned to the available burst light signals in a short time. The technical scheme of the invention can be used in a burst light signal receiver of a XENPAK passive optical network (10 GEPON).

A device for detecting arc fault consists of current detector for detecting current variation and for generating its proportional signal, signal converter for limiting signal level, the first level limit amplifier, signal level detector for generating detection signal, pulse generator for forming normalization pulse, the first arc determining unit for counting pulse signal to judge whether arc is occurred or not and for generating arc detection signal, as well as breaker for cutting off wire when arc detection signal is generated.

The threshold voltage adjusting unit comprises: a feedback comparison module used for receiving the feedback quantity, and according to the variation of feedback quantity, determining the adjusting direction of the threshold voltage; a adjusting module used for getting the adjusted threshold voltage according to the adjusting direction of the threshold voltage and the adjusting step length; a D / A converter used for making D / A conversion for the threshold voltage and outputting the converted threshold. The invention can adjust the threshold voltage along with the variation of the signal and reduce the effects from noise to the threshold voltage so as to effectively reduce the error code rate.

The invention discloses a high-speed CMOS monolithic integration light receiver front end of a cross coupling structure. The high-speed CMOS monolithic integration light receiver front end comprises a photoelectric detector of a completely-symmetric structure, a trans-impedance amplifier of a difference structure, a direct current excursion eliminating unit, a three-stage sequence cascaded difference limiting amplifier and an output buffer stage; the trans-impedance amplifier of the difference structure is used for converting current signals output by the photoelectric detector into voltage signals and conducting preliminary amplification; the direct current excursion eliminating unit is used for eliminating direct current excursion led in by non-balanced signals at the input end of the trans-impedance amplifier and enables common mode levels at the output end of the trans-impedance amplifier to be coincident; the three-stage sequence cascaded difference limiting amplifier is used for amplifying the voltage signals output by the trans-impedance amplifier to be at the voltage level needed by a digital processing unit. Through the adoption of the cross coupling structure, the noise in-phase counteraction technology and the parallel type active inductor design, a high-speed and high-sensitivity standard CMOS monolithic integration light receiver can be achieved.

The invention discloses a dual-rate receiving device in an optical transceiver, which is suitable for the optical transceiver, and comprises a dual-rate optical receiving module, a dual-rate amplitude limiting amplifying circuit unit, a first rate amplitude limiting amplifier data path and a second rate amplitude limiting amplifier data path, wherein signals output by the dual-rate amplitude limiting amplifying circuit unit are respectively input into the first rate amplitude limiting amplifier data path and the second rate amplitude limiting amplifier data path so as to obtain data with different rates, and the data with the different rates are output to a system host machine. By using the technical scheme, the system host machine can receive data from the amplitude limiting amplifier data path with a corresponding working rate, has higher receiving sensitivity for high-rate and low-rate optical data signals and can receive optical signals formed by time division multiplex (TDM) for dual-rate data with lower cost.

A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to maintain a constant input impedance. The predriver includes a limiting amplifier that provides isolation between the power amplifier and the RF input. A DC feedback circuit is used by the predriver that maintains the DC level of the inverters to a desired level.

The invention discloses a passive optical network terminal which relates to the Ethernet passive optical network (EPON) technology. The novel passive optical network terminal integrates a photoelectric conversion circuit of a common optical network terminal and an MAC protocol processing circuit of the passive optical network into an SFP package. The self-contained MAC Ethernet passive optical network terminal SFP is characterized by comprising an optical transceiver BOSA (1), a laser driver LDD (3-1), a limiting amplifier LA (3-2), a PON protocol chip and peripheral circuit (4), an Ethernet serial parallel conversion chip SERDES (5), and a control unit MCU (2). The invention mainly protects the idea of integrating a common photoelectric conversion optical module and a PONMAC chip in the SFP package and realizes the circuit.

Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on / off as needed, reducing power consumption.