36 results about "Unity gain" patented technology

The invention relates to the technical field of chip detection, and discloses a high-reliability power supply chip circuit fault detection system, which comprises a built-in self-test architecture integrated in a low dropout regulator chip, and the built-in self-test architecture is provided with a first test mode and a second test mode which are switched based on a mode switching control circuit. The detection module is used for detecting key performance parameters of an error amplifier sub-circuit in a low dropout linear regulator chip, the detection module is used for measuring the direct current loop gain, the offset voltage, the common mode rejection ratio and the power supply ripple rejection ratio of the amplifier in the first test mode, and the detection module is used for measuring the unity gain bandwidth of the amplifier in the second test mode. According to the invention, through the design of a built-in self-test architecture and two test modes, abnormal states such as differential circuit imbalance and feedback loop fault can be identified in a bare chip stage, chips with poor performance are rejected in advance, and the LDO chip is ensured to reach a ppb-magnitude high reliability standard.

The invention relates to the technical field of emergency protection circuits, and provides an EEG pre-amplification circuit and brain-computer interface equipment. The buffers are connected in parallel, and the corresponding input ends of the buffers are connected with the electrode sensors; the buffer is a four-channel unity gain buffer; the input end of the electrostatic protection diode array is connected with the positive electrode and the negative electrode of a preset power supply, and the input end is further connected between the corresponding input ends of the buffers and the electrode sensor; the first filtering capacitor is connected with the first voltage stabilizing capacitor in parallel, the second filtering capacitor is connected with the second voltage stabilizing capacitor in parallel, the input ends of the first filtering capacitor and the first voltage stabilizing capacitor are connected with the positive electrode of a preset power supply, and the input ends of the first filtering capacitor and the first voltage stabilizing capacitor are connected with a preset grounding end; the input ends of the first filtering capacitor and the first voltage stabilizing capacitor are connected with the negative electrode of the preset power supply, and the input ends are connected with the preset grounding end, so that the power supply noise corresponding to the preset power supply is minimized.

Systems and methods for amplifying signals propagated along a span of cable that imposes a loss tilt, and such that the loss tilt is canceled so as to provide unity gain, by modulating amplification as a function of frequency of an amplifier adjacent the span.

An asymmetric two-phase SRDAB DC-DC power converter apparatus having two SRDAB power conversion modules connected in parallel between an input voltage and an output voltage. The first module is optimized for operation at a minimum converter gain by selecting a first transformer turn ratio such that the first module has a near unity gain at the minimum converter gain and will take a majority of the power at the minimum gain, and the second module is optimized for operation at a maximum converter gain by selecting a second turn ratio such that the second module has a near unity gain at the maximum converter gain and will take a majority of the power at the maximum gain. The first module is operated under voltage mode control and the second module is operated under current mode control. The power converter apparatus provides flatter full-load efficiency without additional components.

Systems and methods for amplifying signals propagated along a span of cable that imposes a loss tilt, and such that the loss tilt is canceled so as to provide unity gain, by modulating amplification as a function of frequency of an amplifier adjacent the span.

The present disclosure relates to a multi-path amplifier circuit and method comprising a first amplification path and a second amplification path coupled in parallel for an input voltage, the first path comprises a first amplifier stage, a second amplifier stage, and a notch filter located between a first node coupled to the second amplifier stage and a second node coupled to an output of the first amplifier stage, and a control unit, the control unit is configured to open the first path and couple the first node to the second node through the unity gain amplifier for a first duration after detecting a change in the common mode of the input voltage.

The invention provides a DC-DC converter and a chip. The DC-DC converter comprises a pulse width modulation signal generator, a lower tube conduction time generation circuit, an external frequency generation circuit, a unit gain negative feedback circuit, a first comparator, a control circuit, an upper tube, an inductor and a lower tube. The lower tube conduction time generating circuit outputs a ramp voltage to the in-phase input end of the first comparator according to the PWM signal and the lower tube conduction time ending signal; the external frequency generation circuit outputs a triangular wave voltage to the unit gain negative feedback circuit according to an external clock signal, a frequency synchronization disable signal and a lower tube conduction time ending signal; the unity gain negative feedback circuit outputs a reference voltage to the inverted input end of the first comparator according to the triangular wave voltage when the frequency synchronization enable signal is at a high level; and the first comparator outputs a lower tube conduction time ending signal to the control circuit, the lower tube conduction time generating circuit and the external frequency generating circuit respectively.

A circuit (100) includes a programmable gain amplifier (PGA 102) having a PGA output. The circuit (100) further includes a delta-sigma modulator (104) having an input coupled to the PGA output. The circuit (100) also includes a digital filter (114) and a dynamic range enhancer (DRE) circuit (110). The digital filter (114) is coupled to the delta-sigma modulator output and to the PGA (102). The DRE circuit (110) is configured to monitor a signal level of the delta-sigma modulator output. In response to the signal level being less than a DRE threshold, the DRE circuit (110) is configured to program the PGA to a gain level greater than unity gain and to cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA (102).

The invention discloses a second-order Sallen Key filtering successive approximation analog-to-digital converter design method and system, and relates to the technical field of analog-to-digital conversion. Comprising the steps that a second-order Sallen Key low-pass filter is selected, and the gain and the quality factor of an operational amplifier are determined; obtaining a second-order Sallen Key low-pass filter topological structure which comprises a resistor R1, a resistor R2, a capacitor C1, a capacitor C2 and an operational amplifier used for unity gain configuration; obtaining a transfer function according to the parameters of the second-order Sallen Key low-pass filter; determining a capacitance value, and then obtaining a resistance value based on the capacitance value and a second-order Sallen Key low-pass filter design formula; obtaining the minimum gain bandwidth product and slew rate of the required operational amplifier according to the cut-off frequency and the signal amplitude; and obtaining a DAC architecture, and obtaining a digital-to-analog converter DAC according to the SAR ADC precision index. By optimizing the structure and parameters of the filter, the anti-aliasing performance and the signal conversion precision of the ADC are improved, and the power consumption and the cost are reduced at the same time.

Systems and methods for pixel-circuit supply voltage noise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes: a front-end circuit having a photodiode configured to generate electrical charges that accumulate at a floating diffusion FD0 as a photodiode voltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion FDC configured to store a common floating diffusion voltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

Multi-path amplifier circuit The present description relates to a multi-path amplifier circuit (300) comprising: first and second amplification paths (201, 202) of an input voltage, connected in parallel, the first path comprising a first amplifier stage (216, 218, 220), a second amplifier stage (226) and a band-stop filter (NOTCH FILTER) between a first node (NOMF, NVOPF) connected to the second amplifier stage (226) and a second node (NVOMI, NVOPI) connected to an output of the first amplifier stage (216, 218, 220); and a control unit (321) configured to, following detection of a change in common mode of the input voltage and for a first duration, open said first path (201) and connect the first node (NVOMF, NVOPF) to the second node (NVOMI, NVOPI) with a unity gain amplifier (320). Figure for abstract: Fig. 2

This application discloses a current-sensing amplifier circuit and calibration method, including: an input module, a reference voltage module, an amplifier, a feedback module, a first switch, and a second switch; the input module and the first switch are sequentially connected to the non-inverting input terminal of the amplifier; the input module and the second switch are sequentially connected to the inverting input terminal of the amplifier; the input module is used to switch between providing a non-zero detection voltage or a zero detection voltage to the amplifier; the inverting input terminal of the amplifier is also connected to the output terminal of the amplifier through the feedback module; the reference voltage module is connected in parallel with the first switch, and the reference voltage module is used to switch between directly outputting the reference voltage or outputting the reference voltage by voltage division; the feedback module is used to switch between providing unity gain or fixed gain to the amplifier. The embodiments of this application can accurately calibrate the detection voltage.

To improve accuracy of measurement of transient thermal resistance in a very short period of time immediately after stop of a heating current.SOLUTION: A transient thermal resistance measuring device 100 includes a heating power supply device 1 for supplying a heating current Ih to a semiconductor device 8 to be measured, a measuring power supply device 2 for supplying a measuring current Im to the semiconductor device 8 to be measured, a voltage measuring device 3 for measuring a voltage Vm between both ends of the semiconductor device 8 to be measured, and a constant current circuit 30 provided in a flow path of the measuring current Im. The constant current circuit 30 includes a transistor, a shunt resistor, a predetermined operational amplifier, and a predetermined voltage source. The predetermined operational amplifier controls the current value of the measurement current Im flowing between the main terminals of the transistor via the control terminal of the transistor so that the voltage across the shunt resistor becomes equal to the output voltage of the predetermined voltage source. The predetermined operational amplifier has a unity gain frequency greater than or equal to 4MHz and a slew rate greater than or equal to 2V / μ s.SELECTED DRAWING: Figure 1

A transient thermal resistance measurement device 100 comprises: a heating power supply device 1 for supplying a heating current Ih to a semiconductor device 8 to be measured; a measurement power supply device 2 for supplying a measurement current Im to the semiconductor device 8 to be measured; a voltage measurement device 3 for measuring a voltage Vm across the semiconductor device 8 to be measured; and a constant current circuit 30 provided in a flow path of the measurement current Im. The constant current circuit 30 comprises: a transistor; a shunt resistor; a prescribed operational amplifier; and a prescribed voltage source. The prescribed operational amplifier controls, via a control terminal of the transistor, the current value of the measurement current Im flowing between main terminals of the transistor such that the voltage across the shunt resistor becomes equal to the output voltage of the prescribed voltage source. The prescribed operational amplifier has a unity gain frequency of 4 MHz or higher and a slew rate of 2 V / μs or higher.

The present invention discloses a unity gain buffer shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses a unity gain buffer to reduce current mismatch in the charge pump, while the active loop filter uses a unity gain buffer in the circuit, which increases the effective capacitance of the active loop filter.

A circuit includes a Sallen-Key filter and a programmable gain amplifier coupled to the Sallen-Key filter, the Sallen-Key filter including a source follower implementing a unity gain amplifier. The circuit is capable of implementing a programmable gain that decouples the bandwidth of the circuit from its gain setting via adjustment of a current mirror replication ratio in the programmable gain amplifier. The programmable gain amplifier can include a differential voltage-to-current converter, a current mirror pair, and a programmable output gain stage. At least one leg in the Sallen-Key filter and the programmable gain amplifier can include transistors arranged in the same circuit configuration.

A biasing circuit for a capacitive transducer comprises: a high impedance element (Rpd) for coupling between a terminal of the capacitive transducer and a reference voltage (Vref); and a unity gain circuit coupled in parallel with at least two back-to-back diodes, where when the bias circuit is used, the coupled unity gain circuit and one terminal of the at least two back-to-back diodes are coupled to the one terminal of the capacitive transducer.

Systems and methods for pixel-circuit supply voltage noise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes: a front-end circuit having a photodiode configured to generate electrical charges that accumulate at a floating diffusion FD0 as a photodiode voltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion FDC configured to store a common floating diffusion voltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

The invention discloses a method for correcting design errors of a CMOS (complementary metal oxide semiconductor) operational amplifier, which comprises the following steps: firstly, according to preset performance indexes, the performance indexes mainly comprise unity gain bandwidth, phase margin and slew rate; the method comprises the following steps: performing initial design on a CMOS operational amplifier by adopting a conventional design process to obtain initial circuit parameters; performing circuit simulation on the initial circuit, and obtaining an actual unit gain frequency, an actual phase margin and an actual slew rate obtained by simulation; calculating an error factor according to the performance index and the simulation result; and correcting the design parameters by using the error factors, and finally recalculating the size of each MOS tube according to the corrected design parameters to complete design error correction. According to the method, performance errors caused by process deviation, model inaccuracy or manual design simplification are identified and corrected in a mode of combining simulation and theoretical calculation, so that the final circuit performance meets or is superior to a preset index.

An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, a capacitive load CL coupled to the output port Vout, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt.

The present invention relates to an active EMI filter with bidirectional electromagnetic interference suppression ability, which includes a first suppression unit and a second suppression unit. The first end of the first suppression unit is connected to the grid side, and the second end of the first suppression unit is grounded; the first end of the second suppression unit is connected to the primary side of the power converter, and the second end of the first suppression unit is grounded. In the present invention, a current transformer extracts the interference current from the bus for the active EMI filter to reconstruct the interference current; a sampling resistor converts the extracted interference current into an interference voltage for the operational amplifier to achieve voltage regulation; the operational amplifier inverts the interference voltage and adjusts the amplitude, and then uses it for interference current injection and cancellation; the injection branch converts the interference voltage output by the operational amplifier into an interference current and injects it into the bus to achieve the suppression of the interference current. The proposed bidirectional active EMI filter adopts a dual CSCC scheme, and through unity gain control, bidirectional suppression of interference can be achieved.

A low current, adaptively-biased switched resistor digital-to-analog converter (RDAC) circuit, method and apparatus are provided with a coarse trim ladder and a fine trim ladder connected with a plurality of NFET switches to generate an output reference voltage from an input supply voltage, where the bulk semiconductor substrate regions for the NFET switches in at least the fine trim ladder are driven by a unity gain buffer which is connected in feedback to receive the output reference voltage and to generate a buffered reference voltage which is directly connected to bulk semiconductor regions of the NFET switches, thereby providing a low current, low circuit area solution with reduced leakage current and temperature variation.

Embodiments of the present disclosure relate to a negative impedance circuit and corresponding devices. The negative impedance circuit includes: a differential circuit stage; a positive feedback path from an output of the differential circuit stage to a first input of the differential circuit stage; a negative feedback path from the output of the differential circuit stage to a second input of the differential circuit stage. The negative feedback path includes a first transistor and a unity gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unity gain path being coupled to ground via a reference impedance. The positive feedback path includes a second transistor. The first transistor and the second transistor are coupled in a current mirror arrangement and have respective control electrodes configured to be driven by the output of the differential circuit stage, wherein the negative impedance circuit induces a negative impedance at the first input of the differential circuit stage.

Circuitry 200a for coupling to a capacitive transducer 230, e.g. a MEMS transducer, comprises unity gain circuitry, a set of back-to-back diodes 210, and a negative feedback loop. The unity gain circu

Disclosed is a receiver of a serial interface, comprising, a first multiplexer configured to select one of a data signal and a first reference voltage in response to an enable signal, a second multiplexer configured to select one of the first reference voltage and a second reference voltage in response to the enable signal, a comparator receiving an output of the first multiplexer to a positive input terminal and an output of the second multiplexer to a negative input terminal, and a reference generator configured to generate the second reference voltage and to generate the first reference voltage from the second reference voltage using an unity gain buffer.

Systems and methods are disclosed for amplifying a signal propagating along a span of a cable to which a loss tilt is applied and such that the loss tilt is counteracted by modulating a frequency-varying amplification of an amplifier adjacent to the span in order to provide unity gain.

A voltage delivery network includes a first unity gain amplifier and a second unity gain amplifier configured in a back-to-back connection topology to receive a first voltage and a second voltage at a first node and a second node, respectively, and jointly output a third voltage at a third node. The network delivery network further includes a first resistor inserted between the third node and the second node; and a first capacitor inserted between the second node and a DC (direct current) node.

Provided is a circuit device including: an oscillation circuit configured to generate an oscillation signal; a waveform shaping circuit configured to shape the oscillation signal into a clock signal having a rectangular wave; a low-pass filter configured to smooth the clock signal and generate a detection voltage corresponding to a duty of the clock signal; and a differential amplifier configured to output a bias voltage based on a difference between the detection voltage and a reference voltage to an input node of the waveform shaping circuit, in which a unity gain frequency of the differential amplifier is lower than a cutoff frequency of the low-pass filter.

Systems and methods for pixel circuit supply noise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes a front-end circuit having a photodiode configured to generate charge accumulated at a floating diffusion FD0 as a photodiode voltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion (FDC) configured to store a common floating diffusion voltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes a voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

A sample-and-hold circuit with improved performance is described. The sample-and-hold circuit comprises first and second differential input terminals receiving distinct first and second differential input voltages. The sample-and-hold circuit also includes first and second unity gain buffers receiving, respectively, the first and second differential input voltages from the first and second differential input terminals. The sample-and-hold circuit includes an amplifier comparing received voltages and amplifying results of the comparison. The amplifier generates a feedback voltage which regulates outputs of the first and second unity gain buffers. The feedback voltage is based on a reference voltage and a common mode voltage that is provided from the first and second unity gain buffers.