23 results about "Unity gain" patented technology

The invention relates to the technical field of chip detection, and discloses a high-reliability power supply chip circuit fault detection system, which comprises a built-in self-test architecture integrated in a low dropout regulator chip, and the built-in self-test architecture is provided with a first test mode and a second test mode which are switched based on a mode switching control circuit. The detection module is used for detecting key performance parameters of an error amplifier sub-circuit in a low dropout linear regulator chip, the detection module is used for measuring the direct current loop gain, the offset voltage, the common mode rejection ratio and the power supply ripple rejection ratio of the amplifier in the first test mode, and the detection module is used for measuring the unity gain bandwidth of the amplifier in the second test mode. According to the invention, through the design of a built-in self-test architecture and two test modes, abnormal states such as differential circuit imbalance and feedback loop fault can be identified in a bare chip stage, chips with poor performance are rejected in advance, and the LDO chip is ensured to reach a ppb-magnitude high reliability standard.

Systems and methods for amplifying signals propagated along a span of cable that imposes a loss tilt, and such that the loss tilt is canceled so as to provide unity gain, by modulating amplification as a function of frequency of an amplifier adjacent the span.

Systems and methods for amplifying signals propagated along a span of cable that imposes a loss tilt, and such that the loss tilt is canceled so as to provide unity gain, by modulating amplification as a function of frequency of an amplifier adjacent the span.

A circuit (100) includes a programmable gain amplifier (PGA 102) having a PGA output. The circuit (100) further includes a delta-sigma modulator (104) having an input coupled to the PGA output. The circuit (100) also includes a digital filter (114) and a dynamic range enhancer (DRE) circuit (110). The digital filter (114) is coupled to the delta-sigma modulator output and to the PGA (102). The DRE circuit (110) is configured to monitor a signal level of the delta-sigma modulator output. In response to the signal level being less than a DRE threshold, the DRE circuit (110) is configured to program the PGA to a gain level greater than unity gain and to cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA (102).

Systems and methods for pixel-circuit supply voltage noise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes: a front-end circuit having a photodiode configured to generate electrical charges that accumulate at a floating diffusion FD0 as a photodiode voltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion FDC configured to store a common floating diffusion voltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

This application discloses a current-sensing amplifier circuit and calibration method, including: an input module, a reference voltage module, an amplifier, a feedback module, a first switch, and a second switch; the input module and the first switch are sequentially connected to the non-inverting input terminal of the amplifier; the input module and the second switch are sequentially connected to the inverting input terminal of the amplifier; the input module is used to switch between providing a non-zero detection voltage or a zero detection voltage to the amplifier; the inverting input terminal of the amplifier is also connected to the output terminal of the amplifier through the feedback module; the reference voltage module is connected in parallel with the first switch, and the reference voltage module is used to switch between directly outputting the reference voltage or outputting the reference voltage by voltage division; the feedback module is used to switch between providing unity gain or fixed gain to the amplifier. The embodiments of this application can accurately calibrate the detection voltage.

To improve accuracy of measurement of transient thermal resistance in a very short period of time immediately after stop of a heating current.SOLUTION: A transient thermal resistance measuring device 100 includes a heating power supply device 1 for supplying a heating current Ih to a semiconductor device 8 to be measured, a measuring power supply device 2 for supplying a measuring current Im to the semiconductor device 8 to be measured, a voltage measuring device 3 for measuring a voltage Vm between both ends of the semiconductor device 8 to be measured, and a constant current circuit 30 provided in a flow path of the measuring current Im. The constant current circuit 30 includes a transistor, a shunt resistor, a predetermined operational amplifier, and a predetermined voltage source. The predetermined operational amplifier controls the current value of the measurement current Im flowing between the main terminals of the transistor via the control terminal of the transistor so that the voltage across the shunt resistor becomes equal to the output voltage of the predetermined voltage source. The predetermined operational amplifier has a unity gain frequency greater than or equal to 4MHz and a slew rate greater than or equal to 2V / μ s.SELECTED DRAWING: Figure 1

A transient thermal resistance measurement device 100 comprises: a heating power supply device 1 for supplying a heating current Ih to a semiconductor device 8 to be measured; a measurement power supply device 2 for supplying a measurement current Im to the semiconductor device 8 to be measured; a voltage measurement device 3 for measuring a voltage Vm across the semiconductor device 8 to be measured; and a constant current circuit 30 provided in a flow path of the measurement current Im. The constant current circuit 30 comprises: a transistor; a shunt resistor; a prescribed operational amplifier; and a prescribed voltage source. The prescribed operational amplifier controls, via a control terminal of the transistor, the current value of the measurement current Im flowing between main terminals of the transistor such that the voltage across the shunt resistor becomes equal to the output voltage of the prescribed voltage source. The prescribed operational amplifier has a unity gain frequency of 4 MHz or higher and a slew rate of 2 V / μs or higher.

The present invention discloses a unity gain buffer shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses a unity gain buffer to reduce current mismatch in the charge pump, while the active loop filter uses a unity gain buffer in the circuit, which increases the effective capacitance of the active loop filter.

A circuit includes a Sallen-Key filter and a programmable gain amplifier coupled to the Sallen-Key filter, the Sallen-Key filter including a source follower implementing a unity gain amplifier. The circuit is capable of implementing a programmable gain that decouples the bandwidth of the circuit from its gain setting via adjustment of a current mirror replication ratio in the programmable gain amplifier. The programmable gain amplifier can include a differential voltage-to-current converter, a current mirror pair, and a programmable output gain stage. At least one leg in the Sallen-Key filter and the programmable gain amplifier can include transistors arranged in the same circuit configuration.

Systems and methods for pixel-circuit supply voltage noise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes: a front-end circuit having a photodiode configured to generate electrical charges that accumulate at a floating diffusion FD0 as a photodiode voltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion FDC configured to store a common floating diffusion voltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

The invention discloses a method for correcting design errors of a CMOS (complementary metal oxide semiconductor) operational amplifier, which comprises the following steps: firstly, according to preset performance indexes, the performance indexes mainly comprise unity gain bandwidth, phase margin and slew rate; the method comprises the following steps: performing initial design on a CMOS operational amplifier by adopting a conventional design process to obtain initial circuit parameters; performing circuit simulation on the initial circuit, and obtaining an actual unit gain frequency, an actual phase margin and an actual slew rate obtained by simulation; calculating an error factor according to the performance index and the simulation result; and correcting the design parameters by using the error factors, and finally recalculating the size of each MOS tube according to the corrected design parameters to complete design error correction. According to the method, performance errors caused by process deviation, model inaccuracy or manual design simplification are identified and corrected in a mode of combining simulation and theoretical calculation, so that the final circuit performance meets or is superior to a preset index.

An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, a capacitive load CL coupled to the output port Vout, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt.

A low current, adaptively-biased switched resistor digital-to-analog converter (RDAC) circuit, method and apparatus are provided with a coarse trim ladder and a fine trim ladder connected with a plurality of NFET switches to generate an output reference voltage from an input supply voltage, where the bulk semiconductor substrate regions for the NFET switches in at least the fine trim ladder are driven by a unity gain buffer which is connected in feedback to receive the output reference voltage and to generate a buffered reference voltage which is directly connected to bulk semiconductor regions of the NFET switches, thereby providing a low current, low circuit area solution with reduced leakage current and temperature variation.

Circuitry 200a for coupling to a capacitive transducer 230, e.g. a MEMS transducer, comprises unity gain circuitry, a set of back-to-back diodes 210, and a negative feedback loop. The unity gain circu

Disclosed is a receiver of a serial interface, comprising, a first multiplexer configured to select one of a data signal and a first reference voltage in response to an enable signal, a second multiplexer configured to select one of the first reference voltage and a second reference voltage in response to the enable signal, a comparator receiving an output of the first multiplexer to a positive input terminal and an output of the second multiplexer to a negative input terminal, and a reference generator configured to generate the second reference voltage and to generate the first reference voltage from the second reference voltage using an unity gain buffer.

A voltage delivery network includes a first unity gain amplifier and a second unity gain amplifier configured in a back-to-back connection topology to receive a first voltage and a second voltage at a first node and a second node, respectively, and jointly output a third voltage at a third node. The network delivery network further includes a first resistor inserted between the third node and the second node; and a first capacitor inserted between the second node and a DC (direct current) node.

Provided is a circuit device including: an oscillation circuit configured to generate an oscillation signal; a waveform shaping circuit configured to shape the oscillation signal into a clock signal having a rectangular wave; a low-pass filter configured to smooth the clock signal and generate a detection voltage corresponding to a duty of the clock signal; and a differential amplifier configured to output a bias voltage based on a difference between the detection voltage and a reference voltage to an input node of the waveform shaping circuit, in which a unity gain frequency of the differential amplifier is lower than a cutoff frequency of the low-pass filter.

Systems and methods for pixel circuit supply noise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes a front-end circuit having a photodiode configured to generate charge accumulated at a floating diffusion FD0 as a photodiode voltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion (FDC) configured to store a common floating diffusion voltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes a voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

The invention provides a Buffer-i n-loop-based novel error feedback noise shaping SAR ADC circuit structure, which comprises a noise feedback connector connected to the input end of a CDAC capacitor and one side of an input signal sampling capacitor, and is characterized in that the noise feedback connector comprises a gain amplifier and a residual voltage sampling capacitor; the residual voltage sampling capacitor is connected with the output of the gain amplifier through a switch; the CDAC capacitor is connected in parallel with the residual voltage sampling capacitor through a switch; and the CDAC capacitor is connected in series with the input end of the unity gain buffer through a switch. Through decoupling of a CDAC and a sampling capacitor in an NS-SAR ADC loop, noise shaping and fusion with other shaping modes are realized by adopting noise feedback connection.

Methods, systems, and devices for voltage drivers with configurable pull-up and pull-down amplifiers are described. For example, a driver may be configured with a pull-up (e.g., sourcing) amplifier and a pull-down (e.g., sinking) amplifier in a unity gain configuration, with outputs of such amplifiers being tied in an electrically parallel arrangement. The pull-down amplifier may be tied to a relatively low voltage to support a lower end of a sinking voltage regulation range, and the pull-up amplifier may be tied with a relatively higher voltage to support a lower end of a sourcing voltage regulation range that is higher than the lower end of the sinking voltage regulation range. Such an arrangement may implement various techniques to enable one of the pull-down amplifier or the pull-up amplifier, which also may disable the other of the pull-down amplifier or the pull-up amplifier.

A linear amplifier with correction circuit is provided. According to one aspect, a linear amplifier includes a high current output stage configured to produce an output voltage and current to deliver power to a load. An output correction circuit receives the output voltage from the high current output stage and produces an error current proportional to a voltage drop across the high current output stage. An input stage receives at least one input and produces a first input current. A current-to-voltage resistor receives produces a first voltage that depends on the first input current and the error current. A first unity gain voltage buffer receives the first voltage from the current-to-voltage resistor and outputs a second voltage that is input to the high current output stage. The first voltage is compensated by the error current to reduce the voltage drop across the high current output stage.

The invention discloses a DC error correction circuit applied to a V2COT control DC / DC converter, and the circuit comprises a primary error amplifier A1 which is used for amplifying an error between a feedback voltage VFB and a reference voltage Vref; the band-gap voltage buffer A2 is used for outputting band-gap buffer voltage during soft start; the secondary error amplifier A3 is used for amplifying the error between the output VC1 of the primary error amplifier and the band gap voltage VBG; the reference voltage buffer A4 is used for outputting a reference buffer voltage; and the unity gain driving buffer A5 is used for buffering the output VC1 of the secondary amplifier A3 and outputting the final modulation voltage VC. The feedback voltage VFB and the feedback voltage VC are compared to send out a signal for conducting the high-side power tube, the conducting time is determined by the COT timing module, and therefore output voltage stabilization is achieved. The DC error correction short circuit is easy to integrate, can ensure that the output voltage is highly consistent with a set value, and greatly improves the precision of the output voltage of the DC / DC converter.