Systems and methods for pixel-circuit supply voltagenoise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes: a front-end circuit having a photodiode configured to generate electrical charges that accumulate at a floating diffusion FD0 as a photodiodevoltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion FDC configured to store a common floating diffusionvoltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.
This application discloses a current-sensing amplifier circuit and calibration method, including: an input module, a reference voltage module, an amplifier, a feedback module, a first switch, and a second switch; the input module and the first switch are sequentially connected to the non-inverting input terminal of the amplifier; the input module and the second switch are sequentially connected to the inverting input terminal of the amplifier; the input module is used to switch between providing a non-zero detection voltage or a zero detection voltage to the amplifier; the inverting input terminal of the amplifier is also connected to the output terminal of the amplifier through the feedback module; the reference voltage module is connected in parallel with the first switch, and the reference voltage module is used to switch between directly outputting the reference voltage or outputting the reference voltage by voltage division; the feedback module is used to switch between providing unity gain or fixed gain to the amplifier. The embodiments of this application can accurately calibrate the detection voltage.
The invention discloses a method for correcting design errors of a CMOS (complementary metaloxidesemiconductor) operational amplifier, which comprises the following steps: firstly, according to preset performance indexes, the performance indexes mainly comprise unity gain bandwidth, phase margin and slew rate; the method comprises the following steps: performing initial design on a CMOSoperational amplifier by adopting a conventional design process to obtain initial circuit parameters; performing circuit simulation on the initial circuit, and obtaining an actual unit gain frequency, an actual phase margin and an actual slew rate obtained by simulation; calculating an error factor according to the performance index and the simulation result; and correcting the design parameters by using the error factors, and finally recalculating the size of each MOS tube according to the corrected design parameters to complete design error correction. According to the method, performance errors caused by process deviation, model inaccuracy or manual design simplification are identified and corrected in a mode of combining simulation and theoretical calculation, so that the final circuit performance meets or is superior to a preset index.
An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, a capacitive load CL coupled to the output port Vout, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt.
A voltage delivery network includes a first unity gainamplifier and a second unity gainamplifier configured in a back-to-back connection topology to receive a first voltage and a second voltage at a first node and a second node, respectively, and jointly output a third voltage at a third node. The network delivery network further includes a first resistor inserted between the third node and the second node; and a first capacitor inserted between the second node and a DC (direct current) node.
Methods, systems, and devices for voltage drivers with configurable pull-up and pull-down amplifiers are described. For example, a driver may be configured with a pull-up (e.g., sourcing) amplifier and a pull-down (e.g., sinking) amplifier in a unity gain configuration, with outputs of such amplifiers being tied in an electrically parallel arrangement. The pull-down amplifier may be tied to a relatively low voltage to support a lower end of a sinking voltage regulation range, and the pull-up amplifier may be tied with a relatively higher voltage to support a lower end of a sourcing voltage regulation range that is higher than the lower end of the sinking voltage regulation range. Such an arrangement may implement various techniques to enable one of the pull-down amplifier or the pull-up amplifier, which also may disable the other of the pull-down amplifier or the pull-up amplifier.
A linear amplifier with correction circuit is provided. According to one aspect, a linear amplifier includes a high current output stage configured to produce an output voltage and current to deliver power to a load. An output correction circuit receives the output voltage from the high current output stage and produces an error current proportional to a voltage drop across the high current output stage. An input stage receives at least one input and produces a first input current. A current-to-voltage resistor receives produces a first voltage that depends on the first input current and the error current. A first unity gain voltage buffer receives the first voltage from the current-to-voltage resistor and outputs a second voltage that is input to the high current output stage. The first voltage is compensated by the error current to reduce the voltage drop across the high current output stage.
The invention discloses a DC error correction circuit applied to a V2COT control DC / DC converter, and the circuit comprises a primary error amplifier A1 which is used for amplifying an error between a feedback voltage VFB and a reference voltage Vref; the band-gap voltage buffer A2 is used for outputting band-gap buffer voltage during soft start; the secondary error amplifier A3 is used for amplifying the error between the output VC1 of the primary error amplifier and the band gap voltage VBG; the reference voltage buffer A4 is used for outputting a reference buffer voltage; and the unity gain driving buffer A5 is used for buffering the output VC1 of the secondary amplifier A3 and outputting the final modulation voltage VC. The feedback voltage VFB and the feedback voltage VC are compared to send out a signal for conducting the high-side power tube, the conducting time is determined by the COT timing module, and therefore output voltage stabilization is achieved. The DC error correction short circuit is easy to integrate, can ensure that the output voltage is highly consistent with a set value, and greatly improves the precision of the output voltage of the DC / DC converter.